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Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcn
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6c75cc62
L		 12013-10-12 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
4 default case.
5 (OP_E_register): Move v_bnd_mode alongside m_mode.
6 * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
7 Drop Reg16 and Disp16. Add NoRex64.
8 (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
9 * i386-tbl.h: Re-generate.
10
0e1c2434
SK		 112013-10-10 Sean Keys <skeys@ipdatasys.com>
12
13 * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
14 table.
15 * xgate-dis.c (print_insn): Refactor to work with table change.
16
7903e530
RM		 172013-10-10 Roland McGrath <mcgrathr@google.com>
18
9ce09ba2
RM		 19 * i386-dis.c (oappend_maybe_intel): New function.
20 (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
21 (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
22 (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
23
2b4e983c
RM		 24 * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
25 possible compiler warnings when the union's initializer is
26 actually meant for the 'preg' enum typed member.
27 * crx-opc.c (REG): Likewise.
28
7903e530
RM		 29 * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
30 Remove duplicate const qualifier.
31
79e0e31d
JB		 322013-10-08 Jan Beulich <jbeulich@suse.com>
33
34 * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
35 (clflush): Use Anysize instead of Byte|Unspecified.
36 (prefetch*): Likewise.
37 * i386-tbl.h: Re-generate.
38
45099dfa
CF		 392013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
40
41 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
42
916fae91
L		 432013-09-30 H.J. Lu <hongjiu.lu@intel.com>
44
45 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
46 * i386-init.h: Regenerated.
47
c7b0bd56
SE		 482013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
49
50 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
51 * i386-init.h: Regenerated.
52
cc9afea3
AM		 532013-09-20 Alan Modra <amodra@gmail.com>
54
55 * configure: Regenerate.
56
e3f9e852
RS		 572013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
58
59 * s390-opc.txt (clih): Make the immediate unsigned.
60
74db7efb
NC		 612013-09-04 Roland McGrath <mcgrathr@google.com>
62
63 PR gas/15914
64 * arm-dis.c (arm_opcodes): Add udf.
65 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
66 (thumb32_opcodes): Add udf.w.
67 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
68
c8094e01
AK		 692013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
70
71 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
72 For the load fp integer instructions only the suppression flag was
73 new with z196 version.
74
7e105031
NC		 752013-08-28 Nick Clifton <nickc@redhat.com>
76
77 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
78 immediate is not suitable for the 32-bit ABI.
79
fb6f3895
MR		 802013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
81
82 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
83 replacing NODS.
84
9aff4b7a
NC		 852013-08-23 Yuri Chornoivan <yurchor@ukr.net>
86
87 PR binutils/15834
88 * aarch64-asm.c: Fix typos.
89 * aarch64-dis.c: Likewise.
90 * msp430-dis.c: Likewise.
91
5e0dc5ba
RS		 922013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
93
94 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
95 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
96 Use +H rather than +C for the real "dext".
97 * mips-opc.c (mips_builtin_opcodes): Likewise.
98
0f35dbc4
RS		 992013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
100
101 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
102 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
103 and OPTIONAL_MAPPED_REG.
104 * mips-opc.c (decode_mips_operand): Likewise.
105 * mips16-opc.c (decode_mips16_operand): Likewise.
106 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
107
79ceb7cb
L		 1082013-08-19 H.J. Lu <hongjiu.lu@intel.com>
109
110 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
111 (PREFIX_EVEX_0F3A3F): Likewise.
112 * i386-dis-evex.h (evex_table): Updated.
113
ee5734f0
RS		 1142013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
115
116 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
117 VCLIPW.
118
d6787ef9
EB		 1192013-08-05 Eric Botcazou <ebotcazou@adacore.com>
120 Konrad Eisele <konrad@gaisler.com>
121
122 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
123 bfd_mach_sparc.
124 * sparc-opc.c (MASK_LEON): Define.
125 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
126 (letandleon): New macro.
127 (v9andleon): Likewise.
128 (sparc_opc): Add leon.
129 (umac): Enable for letandleon.
130 (smac): Likewise.
131 (casa): Enable for v9andleon.
132 (cas): Likewise.
133 (casl): Likewise.
134
14daeee3
RS		 1352013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
136 Richard Sandiford <rdsandiford@googlemail.com>
137
138 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
139 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
140 (print_vu0_channel): New function.
141 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
142 (print_insn_args): Handle '#'.
143 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
144 * mips-opc.c (mips_vu0_channel_mask): New constant.
145 (decode_mips_operand): Handle new VU0 operand types.
146 (VU0, VU0CH): New macros.
147 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
148 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
149 Use "+6" rather than "G" for QMFC2 and QMTC2.
150
3ccad066
RS		 1512013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
152
153 * mips-formats.h (PCREL): Reorder parameters and update the definition
154 to match new mips_pcrel_operand layout.
155 (JUMP, JALX, BRANCH): Update accordingly.
156 * mips16-opc.c (decode_mips16_operand): Likewise.
157
df34fbcc
RS		 1582013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
159
160 * micromips-opc.c (WR_s): Delete.
161
fc76e730
RS		 1622013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
163
164 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
165 New macros.
166 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
167 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
168 (mips_builtin_opcodes): Use the new position-based read-write flags
169 instead of field-based ones. Use UDI for "udi..." instructions.
170 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
171 New macros.
172 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
173 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
174 (WR_SP, RD_16): New macros.
175 (RD_SP): Redefine as an INSN2_* flag.
176 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
177 (mips16_opcodes): Use the new position-based read-write flags
178 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
179 pinfo2 field.
180 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
181 New macros.
182 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
183 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
184 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
185 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
186 (micromips_opcodes): Use the new position-based read-write flags
187 instead of field-based ones.
188 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
189 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
190 of field-based flags.
191
26545944
RS		 1922013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
193
194 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
195 (WR_SP): Replace with...
196 (MOD_SP): ...this.
197 (mips16_opcodes): Update accordingly.
198 * mips-dis.c (print_insn_mips16): Likewise.
199
a8d92fc6
RS		 2002013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
201
202 * mips16-opc.c (mips16_opcodes): Reformat.
203
6a819047
RS		 2042013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
205
206 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
207 for operands that are hard-coded to $0.
208 * micromips-opc.c (micromips_opcodes): Likewise.
209
344c74a6
RS		 2102013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
211
212 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
213 for the single-operand forms of JALR and JALR.HB.
214 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
215 and JALRS.HB.
216
41989114
RS		 2172013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
218
219 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
220 instructions. Fix them to use WR_MACC instead of WR_CC and
221 add missing RD_MACCs.
222
6d075bce
RS		 2232013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
224
225 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
226
4f6ffcd3
PB		 2272013-07-29 Peter Bergner <bergner@vnet.ibm.com>
228
229 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
230
43234a1e
L		 2312013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
232 Alexander Ivchenko <alexander.ivchenko@intel.com>
233 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
234 Sergey Lega <sergey.s.lega@intel.com>
235 Anna Tikhonova <anna.tikhonova@intel.com>
236 Ilya Tocar <ilya.tocar@intel.com>
237 Andrey Turetskiy <andrey.turetskiy@intel.com>
238 Ilya Verbin <ilya.verbin@intel.com>
239 Kirill Yukhin <kirill.yukhin@intel.com>
240 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
241
242 * i386-dis-evex.h: New.
243 * i386-dis.c (OP_Rounding): New.
244 (VPCMP_Fixup): New.
245 (OP_Mask): New.
246 (Rdq): New.
247 (XMxmmq): New.
248 (EXdScalarS): New.
249 (EXymm): New.
250 (EXEvexHalfBcstXmmq): New.
251 (EXxmm_mdq): New.
252 (EXEvexXGscat): New.
253 (EXEvexXNoBcst): New.
254 (VPCMP): New.
255 (EXxEVexR): New.
256 (EXxEVexS): New.
257 (XMask): New.
258 (MaskG): New.
259 (MaskE): New.
260 (MaskR): New.
261 (MaskVex): New.
262 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
263 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
264 evex_rounding_mode, evex_sae_mode, mask_mode.
265 (USE_EVEX_TABLE): New.
266 (EVEX_TABLE): New.
267 (EVEX enum): New.
268 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
269 REG_EVEX_0F38C7.
270 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
271 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
272 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
273 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
274 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
275 MOD_EVEX_0F38C7_REG_6.
276 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
277 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
278 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
279 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
280 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
281 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
282 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
283 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
284 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
285 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
286 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
287 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
288 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
289 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
290 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
291 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
292 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
293 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
294 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
295 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
296 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
297 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
298 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
299 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
300 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
301 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
302 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
303 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
304 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
305 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
306 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
307 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
308 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
309 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
310 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
311 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
312 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
313 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
314 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
315 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
316 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
317 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
318 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
319 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
320 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
321 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
322 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
323 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
324 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
325 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
326 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
327 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
328 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
329 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
330 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
331 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
332 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
333 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
334 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
335 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
336 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
337 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
338 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
339 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
340 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
341 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
342 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
343 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
344 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
345 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
346 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
347 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
348 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
349 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
350 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
351 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
352 PREFIX_EVEX_0F3A55.
353 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
354 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
355 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
356 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
357 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
358 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
359 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
360 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
361 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
362 VEX_W_0F3A32_P_2_LEN_0.
363 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
364 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
365 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
366 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
367 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
368 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
369 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
370 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
371 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
372 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
373 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
374 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
375 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
376 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
377 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
378 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
379 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
380 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
381 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
382 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
383 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
384 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
385 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
386 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
387 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
388 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
389 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
390 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
391 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
392 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
393 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
394 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
395 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
396 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
397 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
398 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
399 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
400 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
401 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
402 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
403 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
404 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
405 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
406 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
407 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
408 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
409 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
410 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
411 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
412 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
413 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
414 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
415 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
416 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
417 (struct vex): Add fields evex, r, v, mask_register_specifier,
418 zeroing, ll, b.
419 (intel_names_xmm): Add upper 16 registers.
420 (att_names_xmm): Ditto.
421 (intel_names_ymm): Ditto.
422 (att_names_ymm): Ditto.
423 (names_zmm): New.
424 (intel_names_zmm): Ditto.
425 (att_names_zmm): Ditto.
426 (names_mask): Ditto.
427 (intel_names_mask): Ditto.
428 (att_names_mask): Ditto.
429 (names_rounding): Ditto.
430 (names_broadcast): Ditto.
431 (x86_64_table): Add escape to evex-table.
432 (reg_table): Include reg_table evex-entries from
433 i386-dis-evex.h. Fix prefetchwt1 instruction.
434 (prefix_table): Add entries for new instructions.
435 (vex_table): Ditto.
436 (vex_len_table): Ditto.
437 (vex_w_table): Ditto.
438 (mod_table): Ditto.
439 (get_valid_dis386): Properly handle new instructions.
440 (print_insn): Handle zmm and mask registers, print mask operand.
441 (intel_operand_size): Support EVEX, new modes and sizes.
442 (OP_E_register): Handle new modes.
443 (OP_E_memory): Ditto.
444 (OP_G): Ditto.
445 (OP_XMM): Ditto.
446 (OP_EX): Ditto.
447 (OP_VEX): Ditto.
448 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
449 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
450 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
451 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
452 CpuAVX512PF and CpuVREX.
453 (operand_type_init): Add OPERAND_TYPE_REGZMM,
454 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
455 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
456 StaticRounding, SAE, Disp8MemShift, NoDefMask.
457 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
458 * i386-init.h: Regenerate.
459 * i386-opc.h (CpuAVX512F): New.
460 (CpuAVX512CD): New.
461 (CpuAVX512ER): New.
462 (CpuAVX512PF): New.
463 (CpuVREX): New.
464 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
465 cpuavx512pf and cpuvrex fields.
466 (VecSIB): Add VecSIB512.
467 (EVex): New.
468 (Masking): New.
469 (VecESize): New.
470 (Broadcast): New.
471 (StaticRounding): New.
472 (SAE): New.
473 (Disp8MemShift): New.
474 (NoDefMask): New.
475 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
476 staticrounding, sae, disp8memshift and nodefmask.
477 (RegZMM): New.
478 (Zmmword): Ditto.
479 (Vec_Disp8): Ditto.
480 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
481 fields.
482 (RegVRex): New.
483 * i386-opc.tbl: Add AVX512 instructions.
484 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
485 registers, mask registers.
486 * i386-tbl.h: Regenerate.
487
1d2db237
RS		 4882013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
489
490 PR gas/15220
491 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
492 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
493
a0046408
L		 4942013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
495
496 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
497 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
498 PREFIX_0F3ACC.
499 (prefix_table): Updated.
500 (three_byte_table): Likewise.
501 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
502 (cpu_flags): Add CpuSHA.
503 (i386_cpu_flags): Add cpusha.
504 * i386-init.h: Regenerate.
505 * i386-opc.h (CpuSHA): New.
506 (CpuUnused): Restored.
507 (i386_cpu_flags): Add cpusha.
508 * i386-opc.tbl: Add SHA instructions.
509 * i386-tbl.h: Regenerate.
510
7e8b059b
L		 5112013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
512 Kirill Yukhin <kirill.yukhin@intel.com>
513 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
514
515 * i386-dis.c (BND_Fixup): New.
516 (Ebnd): New.
517 (Ev_bnd): New.
518 (Gbnd): New.
519 (BND): New.
520 (v_bnd_mode): New.
521 (bnd_mode): New.
c623f86c
L		 522 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
523 MOD_0F1B_PREFIX_1.
524 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 525 (dis tables): Replace XX with BND for near branch and call
526 instructions.
527 (prefix_table): Add new entries.
528 (mod_table): Likewise.
529 (names_bnd): New.
530 (intel_names_bnd): New.
531 (att_names_bnd): New.
532 (BND_PREFIX): New.
533 (prefix_name): Handle BND_PREFIX.
534 (print_insn): Initialize names_bnd.
535 (intel_operand_size): Handle new modes.
536 (OP_E_register): Likewise.
537 (OP_E_memory): Likewise.
538 (OP_G): Likewise.
539 * i386-gen.c (cpu_flag_init): Add CpuMPX.
540 (cpu_flags): Add CpuMPX.
541 (operand_type_init): Add RegBND.
542 (opcode_modifiers): Add BNDPrefixOk.
543 (operand_types): Add RegBND.
544 * i386-init.h: Regenerate.
545 * i386-opc.h (CpuMPX): New.
546 (CpuUnused): Comment out.
547 (i386_cpu_flags): Add cpumpx.
548 (BNDPrefixOk): New.
549 (i386_opcode_modifier): Add bndprefixok.
550 (RegBND): New.
551 (i386_operand_type): Add regbnd.
552 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
553 Add MPX instructions and bnd prefix.
554 * i386-reg.tbl: Add bnd0-bnd3 registers.
555 * i386-tbl.h: Regenerate.
556
b56e23fb
RS		 5572013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
558
559 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
560 ATTRIBUTE_UNUSED.
561
e7ae278d
RS		 5622013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
563
564 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
565 special rules.
566 * Makefile.in: Regenerate.
567 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
568 all fields. Reformat.
569
c3c07478
RS		 5702013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
571
572 * mips16-opc.c: Include mips-formats.h.
573 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
574 static arrays.
575 (decode_mips16_operand): New function.
576 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
577 (print_insn_arg): Handle OP_ENTRY_EXIT list.
578 Abort for OP_SAVE_RESTORE_LIST.
579 (print_mips16_insn_arg): Change interface. Use mips_operand
580 structures. Delete GET_OP_S. Move GET_OP definition to...
581 (print_insn_mips16): ...here. Call init_print_arg_state.
582 Update the call to print_mips16_insn_arg.
583
ab902481
RS		 5842013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
585
586 * mips-formats.h: New file.
587 * mips-opc.c: Include mips-formats.h.
588 (reg_0_map): New static array.
589 (decode_mips_operand): New function.
590 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
591 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
592 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
593 (int_c_map): New static arrays.
594 (decode_micromips_operand): New function.
595 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
596 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
597 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
598 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
599 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
600 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
601 (micromips_imm_b_map, micromips_imm_c_map): Delete.
602 (print_reg): New function.
603 (mips_print_arg_state): New structure.
604 (init_print_arg_state, print_insn_arg): New functions.
605 (print_insn_args): Change interface and use mips_operand structures.
606 Delete GET_OP_S. Move GET_OP definition to...
607 (print_insn_mips): ...here. Update the call to print_insn_args.
608 (print_insn_micromips): Use print_insn_args.
609
cc537e56
RS		 6102013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
611
612 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
613 in macros.
614
7a5f87ce
RS		 6152013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
616
617 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
618 ADDA.S, MULA.S and SUBA.S.
619
41741fa4
L		 6202013-07-08 H.J. Lu <hongjiu.lu@intel.com>
621
622 PR gas/13572
623 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
624 * i386-tbl.h: Regenerated.
625
f2ae14a1
RS		 6262013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
627
628 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
629 and SD A(B) macros up.
630 * micromips-opc.c (micromips_opcodes): Likewise.
631
04c9d415
RS		 6322013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
633
634 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
635 instructions.
636
5c324c16
RS		 6372013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
638
639 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
640 MDMX-like instructions.
641 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
642 printing "Q" operands for INSN_5400 instructions.
643
23e69e47
RS		 6442013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
645
646 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
647 "+S" for "cins".
648 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
649 Combine cases.
650
27c5c572
RS		 6512013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
652
653 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
654 "jalx".
655 * mips16-opc.c (mips16_opcodes): Likewise.
656 * micromips-opc.c (micromips_opcodes): Likewise.
657 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
658 (print_insn_mips16): Handle "+i".
659 (print_insn_micromips): Likewise. Conditionally preserve the
660 ISA bit for "a" but not for "+i".
661
e76ff5ab
RS		 6622013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
663
664 * micromips-opc.c (WR_mhi): Rename to..
665 (WR_mh): ...this.
666 (micromips_opcodes): Update "movep" entry accordingly. Replace
667 "mh,mi" with "mh".
668 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
669 (micromips_to_32_reg_h_map1): ...this.
670 (micromips_to_32_reg_i_map): Rename to...
671 (micromips_to_32_reg_h_map2): ...this.
672 (print_micromips_insn): Remove "mi" case. Print both registers
673 in the pair for "mh".
674
fa7616a4
RS		 6752013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
676
677 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
678 * micromips-opc.c (micromips_opcodes): Likewise.
679 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
680 and "+T" handling. Check for a "0" suffix when deciding whether to
681 use coprocessor 0 names. In that case, also check for ",H" selectors.
682
fb798c50
AK		 6832013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
684
685 * s390-opc.c (J12_12, J24_24): New macros.
686 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
687 (MASK_MII_UPI): Rename to MASK_MII_UPP.
688 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
689
58ae08f2
AM		 6902013-07-04 Alan Modra <amodra@gmail.com>
691
692 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
693
b5e04c2b
NC		 6942013-06-26 Nick Clifton <nickc@redhat.com>
695
696 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
697 field when checking for type 2 nop.
698 * rx-decode.c: Regenerate.
699
833794fc
MR		 7002013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
701
702 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
703 and "movep" macros.
704
1bbce132
MR		 7052013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
706
707 * mips-dis.c (is_mips16_plt_tail): New function.
708 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
709 word.
710 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
711
34c911a4
NC		 7122013-06-21 DJ Delorie <dj@redhat.com>
713
714 * msp430-decode.opc: New.
715 * msp430-decode.c: New/generated.
716 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
717 (MAINTAINER_CLEANFILES): Likewise.
718 Add rule to build msp430-decode.c frommsp430decode.opc
719 using the opc2c program.
720 * Makefile.in: Regenerate.
721 * configure.in: Add msp430-decode.lo to msp430 architecture files.
722 * configure: Regenerate.
723
b9eead84
YZ		 7242013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
725
726 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
727 (SYMTAB_AVAILABLE): Removed.
728 (#include "elf/aarch64.h): Ditto.
729
7f3c4072
CM		 7302013-06-17 Catherine Moore <clm@codesourcery.com>
731 Maciej W. Rozycki <macro@codesourcery.com>
732 Chao-Ying Fu <fu@mips.com>
733
734 * micromips-opc.c (EVA): Define.
735 (TLBINV): Define.
736 (micromips_opcodes): Add EVA opcodes.
737 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
738 (print_insn_args): Handle EVA offsets.
739 (print_insn_micromips): Likewise.
740 * mips-opc.c (EVA): Define.
741 (TLBINV): Define.
742 (mips_builtin_opcodes): Add EVA opcodes.
743
de40ceb6
AM		 7442013-06-17 Alan Modra <amodra@gmail.com>
745
746 * Makefile.am (mips-opc.lo): Add rules to create automatic
747 dependency files. Pass archdefs.
748 (micromips-opc.lo, mips16-opc.lo): Likewise.
749 * Makefile.in: Regenerate.
750
3531d549
DD		 7512013-06-14 DJ Delorie <dj@redhat.com>
752
753 * rx-decode.opc (rx_decode_opcode): Bit operations on
754 registers are 32-bit operations, not 8-bit operations.
755 * rx-decode.c: Regenerate.
756
ba92f7fb
CF		 7572013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
758
759 * micromips-opc.c (IVIRT): New define.
760 (IVIRT64): New define.
761 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
762 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
763
764 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
765 dmtgc0 to print cp0 names.
766
9daf7bab
SL		 7672013-06-09 Sandra Loosemore <sandra@codesourcery.com>
768
769 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
770 argument.
771
d301a56b
RS		 7722013-06-08 Catherine Moore <clm@codesourcery.com>
773 Richard Sandiford <rdsandiford@googlemail.com>
774
775 * micromips-opc.c (D32, D33, MC): Update definitions.
776 (micromips_opcodes): Initialize ase field.
777 * mips-dis.c (mips_arch_choice): Add ase field.
778 (mips_arch_choices): Initialize ase field.
779 (set_default_mips_dis_options): Declare and setup mips_ase.
780 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
781 MT32, MC): Update definitions.
782 (mips_builtin_opcodes): Initialize ase field.
783
a3dcb6c5
RS		 7842013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
785
786 * s390-opc.txt (flogr): Require a register pair destination.
787
6cf1d90c
AK		 7882013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
789
790 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
791 instruction format.
792
c77c0862
RS		 7932013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
794
795 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
796
c0637f3a
PB		 7972013-05-20 Peter Bergner <bergner@vnet.ibm.com>
798
799 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
800 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
801 XLS_MASK, PPCVSX2): New defines.
802 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
803 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
804 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
805 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
806 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
807 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
808 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
809 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
810 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
811 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
812 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
813 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
814 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
815 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
816 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
817 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
818 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
819 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
820 <lxvx, stxvx>: New extended mnemonics.
821
4934fdaf
AM		 8222013-05-17 Alan Modra <amodra@gmail.com>
823
824 * ia64-raw.tbl: Replace non-ASCII char.
825 * ia64-waw.tbl: Likewise.
826 * ia64-asmtab.c: Regenerate.
827
6091d651
SE		 8282013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
829
830 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
831 * i386-init.h: Regenerated.
832
d2865ed3
YZ		 8332013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
834
835 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
836 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
837 check from [0, 255] to [-128, 255].
838
b015e599
AP		 8392013-05-09 Andrew Pinski <apinski@cavium.com>
840
841 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
842 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
843 (parse_mips_dis_option): Handle the virt option.
844 (print_insn_args): Handle "+J".
845 (print_mips_disassembler_options): Print out message about virt64.
846 * mips-opc.c (IVIRT): New define.
847 (IVIRT64): New define.
848 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
849 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
850 Move rfe to the bottom as it conflicts with tlbgp.
851
9f0682fe
AM		 8522013-05-09 Alan Modra <amodra@gmail.com>
853
854 * ppc-opc.c (extract_vlesi): Properly sign extend.
855 (extract_vlensi): Likewise. Comment reason for setting invalid.
856
13761a11
NC		 8572013-05-02 Nick Clifton <nickc@redhat.com>
858
859 * msp430-dis.c: Add support for MSP430X instructions.
860
e3031850
SL		 8612013-04-24 Sandra Loosemore <sandra@codesourcery.com>
862
863 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
864 to "eccinj".
865
17310e56
NC		 8662013-04-17 Wei-chen Wang <cole945@gmail.com>
867
868 PR binutils/15369
869 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
870 of CGEN_CPU_ENDIAN.
871 (hash_insns_list): Likewise.
872
731df338
JK		 8732013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
874
875 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
876 warning workaround.
877
5f77db52
JB		 8782013-04-08 Jan Beulich <jbeulich@suse.com>
879
880 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
881 * i386-tbl.h: Re-generate.
882
0afd1215
DM		 8832013-04-06 David S. Miller <davem@davemloft.net>
884
885 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
886 of an opcode, prefer the one with F_PREFERRED set.
887 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
888 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
889 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
890 mark existing mnenomics as aliases. Add "cc" suffix to edge
891 instructions generating condition codes, mark existing mnenomics
892 as aliases. Add "fp" prefix to VIS compare instructions, mark
893 existing mnenomics as aliases.
894
41702d50
NC		 8952013-04-03 Nick Clifton <nickc@redhat.com>
896
897 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
898 destination address by subtracting the operand from the current
899 address.
900 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
901 a positive value in the insn.
902 (extract_u16_loop): Do not negate the returned value.
903 (D16_LOOP): Add V850_INVERSE_PCREL flag.
904
905 (ceilf.sw): Remove duplicate entry.
906 (cvtf.hs): New entry.
907 (cvtf.sh): Likewise.
908 (fmaf.s): Likewise.
909 (fmsf.s): Likewise.
910 (fnmaf.s): Likewise.
911 (fnmsf.s): Likewise.
912 (maddf.s): Restrict to E3V5 architectures.
913 (msubf.s): Likewise.
914 (nmaddf.s): Likewise.
915 (nmsubf.s): Likewise.
916
55cf16e1
L		 9172013-03-27 H.J. Lu <hongjiu.lu@intel.com>
918
919 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
920 check address mode.
921 (print_insn): Pass sizeflag to get_sib.
922
51dcdd4d
NC		 9232013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
924
925 PR binutils/15068
926 * tic6x-dis.c: Add support for displaying 16-bit insns.
927
795b8e6b
NC		 9282013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
929
930 PR gas/15095
931 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
932 individual msb and lsb halves in src1 & src2 fields. Discard the
933 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
934 follow what Ti SDK does in that case as any value in the src1
935 field yields the same output with SDK disassembler.
936
314d60dd
ME		 9372013-03-12 Michael Eager <eager@eagercon.com>
938
795b8e6b 939 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 940
dad60f8e
SL		 9412013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
942
943 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
944
f5cb796a
SL		 9452013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
946
947 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
948
21fde85c
SL		 9492013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
950
951 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
952
dd5181d5
KT		 9532013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
954
955 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
956 (thumb32_opcodes): Likewise.
957 (print_insn_thumb32): Handle 'S' control char.
958
87a8d6cb
NC		 9592013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
960
961 * lm32-desc.c: Regenerate.
962
99dce992
L		 9632013-03-01 H.J. Lu <hongjiu.lu@intel.com>
964
965 * i386-reg.tbl (riz): Add RegRex64.
966 * i386-tbl.h: Regenerated.
967
e60bb1dd
YZ		 9682013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
969
970 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
971 (aarch64_feature_crc): New static.
972 (CRC): New macro.
973 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
974 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
975 * aarch64-asm-2.c: Re-generate.
976 * aarch64-dis-2.c: Ditto.
977 * aarch64-opc-2.c: Ditto.
978
c7570fcd
AM		 9792013-02-27 Alan Modra <amodra@gmail.com>
980
981 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
982 * rl78-decode.c: Regenerate.
983
151fa98f
NC		 9842013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
985
986 * rl78-decode.opc: Fix encoding of DIVWU insn.
987 * rl78-decode.c: Regenerate.
988
5c111e37
L		 9892013-02-19 H.J. Lu <hongjiu.lu@intel.com>
990
991 PR gas/15159
992 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
993
994 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
995 (cpu_flags): Add CpuSMAP.
996
997 * i386-opc.h (CpuSMAP): New.
998 (i386_cpu_flags): Add cpusmap.
999
1000 * i386-opc.tbl: Add clac and stac.
1001
1002 * i386-init.h: Regenerated.
1003 * i386-tbl.h: Likewise.
1004
9d1df426
NC		 10052013-02-15 Markos Chandras <markos.chandras@imgtec.com>
1006
1007 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1008 which also makes the disassembler output be in little
1009 endian like it should be.
1010
a1ccaec9
YZ		 10112013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1012
1013 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1014 fields to NULL.
1015 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1016
ef068ef4 10172013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 1018
1019 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1020 section disassembled.
1021
6fe6ded9
RE		 10222013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1023
1024 * arm-dis.c: Update strht pattern.
1025
0aa27725
RS		 10262013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1027
1028 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1029 single-float. Disable ll, lld, sc and scd for EE. Disable the
1030 trunc.w.s macro for EE.
1031
36591ba1
SL		 10322013-02-06 Sandra Loosemore <sandra@codesourcery.com>
1033 Andrew Jenner <andrew@codesourcery.com>
1034
1035 Based on patches from Altera Corporation.
1036
1037 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1038 nios2-opc.c.
1039 * Makefile.in: Regenerated.
1040 * configure.in: Add case for bfd_nios2_arch.
1041 * configure: Regenerated.
1042 * disassemble.c (ARCH_nios2): Define.
1043 (disassembler): Add case for bfd_arch_nios2.
1044 * nios2-dis.c: New file.
1045 * nios2-opc.c: New file.
1046
545093a4
AM		 10472013-02-04 Alan Modra <amodra@gmail.com>
1048
1049 * po/POTFILES.in: Regenerate.
1050 * rl78-decode.c: Regenerate.
1051 * rx-decode.c: Regenerate.
1052
e30181a5
YZ		 10532013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1054
1055 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1056 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1057 * aarch64-asm.c (convert_xtl_to_shll): New function.
1058 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1059 calling convert_xtl_to_shll.
1060 * aarch64-dis.c (convert_shll_to_xtl): New function.
1061 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1062 calling convert_shll_to_xtl.
1063 * aarch64-gen.c: Update copyright year.
1064 * aarch64-asm-2.c: Re-generate.
1065 * aarch64-dis-2.c: Re-generate.
1066 * aarch64-opc-2.c: Re-generate.
1067
78c8d46c
NC		 10682013-01-24 Nick Clifton <nickc@redhat.com>
1069
1070 * v850-dis.c: Add support for e3v5 architecture.
1071 * v850-opc.c: Likewise.
1072
f5555712
YZ		 10732013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1074
1075 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1076 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1077 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 1078 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 1079 alignment check; change to call set_sft_amount_out_of_range_error
1080 instead of set_imm_out_of_range_error.
1081 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1082 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1083 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1084 SIMD_IMM_SFT.
1085
2f81ff92
L		 10862013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1087
1088 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1089
1090 * i386-init.h: Regenerated.
1091 * i386-tbl.h: Likewise.
1092
dd42f060
NC		 10932013-01-15 Nick Clifton <nickc@redhat.com>
1094
1095 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1096 values.
1097 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1098
a4533ed8
NC		 10992013-01-14 Will Newton <will.newton@imgtec.com>
1100
1101 * metag-dis.c (REG_WIDTH): Increase to 64.
1102
5817ffd1
PB		 11032013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1104
1105 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1106 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1107 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1108 (SH6): Update.
1109 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1110 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1111 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1112 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1113
a3c62988
NC		 11142013-01-10 Will Newton <will.newton@imgtec.com>
1115
1116 * Makefile.am: Add Meta.
1117 * configure.in: Add Meta.
1118 * disassemble.c: Add Meta support.
1119 * metag-dis.c: New file.
1120 * Makefile.in: Regenerate.
1121 * configure: Regenerate.
1122
73335eae
NC		 11232013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1124
1125 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1126 (match_opcode): Rename to cr16_match_opcode.
1127
e407c74b
NC		 11282013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1129
1130 * mips-dis.c: Add names for CP0 registers of r5900.
1131 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1132 instructions sq and lq.
1133 Add support for MIPS r5900 CPU.
1134 Add support for 128 bit MMI (Multimedia Instructions).
1135 Add support for EE instructions (Emotion Engine).
1136 Disable unsupported floating point instructions (64 bit and
1137 undefined compare operations).
1138 Enable instructions of MIPS ISA IV which are supported by r5900.
1139 Disable 64 bit co processor instructions.
1140 Disable 64 bit multiplication and division instructions.
1141 Disable instructions for co-processor 2 and 3, because these are
1142 not supported (preparation for later VU0 support (Vector Unit)).
1143 Disable cvt.w.s because this behaves like trunc.w.s and the
1144 correct execution can't be ensured on r5900.
1145 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1146 will confuse less developers and compilers.
1147
a32c3ff8
NC		 11482013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1149
fb098a1e
YZ		 1150 * aarch64-opc.c (aarch64_print_operand): Change to print
1151 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1152 in comment.
1153 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1154 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1155 OP_MOV_IMM_WIDE.
1156
11572013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1158
1159 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1160 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1161
62658407
L		 11622013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1163
1164 * i386-gen.c (process_copyright): Update copyright year to 2013.
1165
bab4becb 11662013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1167
bab4becb
NC		 1168 * cr16-dis.c (match_opcode,make_instruction): Remove static
1169 declaration.
1170 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1171 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1172
bab4becb 1173For older changes see ChangeLog-2012
252b5132 1174\f
bab4becb 1175Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1176
1177Copying and distribution of this file, with or without modification,
1178are permitted in any medium without royalty provided the copyright
1179notice and this notice are preserved.
1180
252b5132 1181Local Variables:
2f6d2f85
NC		 1182mode: change-log
1183left-margin: 8
1184fill-column: 74
252b5132
RH		 1185version-control: never
1186End:
GDB Binutils - Deliverables
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