Commit | Line | Data |
---|---|---|
6df22cf6 JB |
1 | 2020-07-06 Jan Beulich <jbeulich@suse.com> |
2 | ||
3 | * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, | |
4 | PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68, | |
5 | PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, | |
6 | PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA, | |
7 | PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE, | |
8 | PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, | |
9 | PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, | |
10 | PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC, | |
11 | PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1, | |
12 | PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, | |
13 | PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, | |
14 | PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B, | |
15 | PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C, | |
16 | PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, | |
17 | PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, | |
18 | PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, | |
19 | PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, | |
20 | PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6, | |
21 | PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, | |
22 | PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, | |
23 | PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, | |
24 | PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, | |
25 | PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, | |
26 | PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF, | |
27 | PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE, | |
28 | PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F, | |
29 | PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF, | |
30 | EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2, | |
31 | EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2, | |
32 | EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete. | |
33 | (prefix_table): Add EXxEVexR to FMA table entries. | |
34 | (OP_Rounding): Move abort() invocation. | |
35 | * i386-dis-evex.h (evex_table): Reference VEX table for opcodes | |
36 | 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9, | |
37 | 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8, | |
38 | 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9, | |
39 | 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C, | |
40 | 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897, | |
41 | 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7, | |
42 | 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7, | |
43 | 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF, | |
44 | 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44, | |
45 | 0F3ACE, 0F3ACF. | |
46 | * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, | |
47 | PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68, | |
48 | PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, | |
49 | PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA, | |
50 | PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE, | |
51 | PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, | |
52 | PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, | |
53 | PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC, | |
54 | PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1, | |
55 | PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, | |
56 | PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, | |
57 | PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B, | |
58 | PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C, | |
59 | PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, | |
60 | PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, | |
61 | PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, | |
62 | PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, | |
63 | PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6, | |
64 | PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, | |
65 | PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, | |
66 | PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, | |
67 | PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, | |
68 | PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, | |
69 | PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF, | |
70 | PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE, | |
71 | PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F, | |
72 | PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF): | |
73 | Delete table entries. | |
74 | * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, | |
75 | EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, | |
76 | EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): | |
77 | Likewise. | |
78 | ||
39e0f456 JB |
79 | 2020-07-06 Jan Beulich <jbeulich@suse.com> |
80 | ||
81 | * i386-dis.c (EXqScalarS): Delete. | |
82 | (vex_len_table): Replace EXqScalarS by EXqVexScalarS. | |
83 | * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS. | |
84 | ||
5b872f7d JB |
85 | 2020-07-06 Jan Beulich <jbeulich@suse.com> |
86 | ||
87 | * i386-dis.c (safe-ctype.h): Include. | |
88 | (EXdScalar, EXqScalar): Delete. | |
89 | (d_scalar_mode, q_scalar_mode): Delete. | |
90 | (prefix_table, vex_len_table): Use EXxmm_md in place of | |
91 | EXdScalar and EXxmm_mq in place of EXqScalar. | |
92 | (intel_operand_size, OP_E_memory, OP_EX): Remove uses of | |
93 | d_scalar_mode and q_scalar_mode. | |
94 | * i386-dis-evex-w.h (vmovss): Use EXxmm_md. | |
95 | (vmovsd): Use EXxmm_mq. | |
96 | ||
ddc73fa9 NC |
97 | 2020-07-06 Yuri Chornoivan <yurchor@ukr.net> |
98 | ||
99 | PR 26204 | |
100 | * arc-dis.c: Fix spelling mistake. | |
101 | * po/opcodes.pot: Regenerate. | |
102 | ||
17550be7 NC |
103 | 2020-07-06 Nick Clifton <nickc@redhat.com> |
104 | ||
105 | * po/pt_BR.po: Updated Brazilian Portugugese translation. | |
106 | * po/uk.po: Updated Ukranian translation. | |
107 | ||
b19d852d NC |
108 | 2020-07-04 Nick Clifton <nickc@redhat.com> |
109 | ||
110 | * configure: Regenerate. | |
111 | * po/opcodes.pot: Regenerate. | |
112 | ||
b115b9fd NC |
113 | 2020-07-04 Nick Clifton <nickc@redhat.com> |
114 | ||
115 | Binutils 2.35 branch created. | |
116 | ||
c2ecccb3 L |
117 | 2020-07-02 H.J. Lu <hongjiu.lu@intel.com> |
118 | ||
119 | * i386-gen.c (opcode_modifiers): Add VexSwapSources. | |
120 | * i386-opc.h (VexSwapSources): New. | |
121 | (i386_opcode_modifier): Add vexswapsources. | |
122 | * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions | |
123 | with two source operands swapped. | |
124 | * i386-tbl.h: Regenerated. | |
125 | ||
08ccfccf NC |
126 | 2020-06-30 Nelson Chu <nelson.chu@sifive.com> |
127 | ||
128 | * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the | |
129 | unprivileged CSR can also be initialized. | |
130 | ||
279edac5 AM |
131 | 2020-06-29 Alan Modra <amodra@gmail.com> |
132 | ||
133 | * arm-dis.c: Use C style comments. | |
134 | * cr16-opc.c: Likewise. | |
135 | * ft32-dis.c: Likewise. | |
136 | * moxie-opc.c: Likewise. | |
137 | * tic54x-dis.c: Likewise. | |
138 | * s12z-opc.c: Remove useless comment. | |
139 | * xgate-dis.c: Likewise. | |
140 | ||
e978ad62 L |
141 | 2020-06-26 H.J. Lu <hongjiu.lu@intel.com> |
142 | ||
143 | * i386-opc.tbl: Add a blank line. | |
144 | ||
63112cd6 L |
145 | 2020-06-26 H.J. Lu <hongjiu.lu@intel.com> |
146 | ||
147 | * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB. | |
148 | (VecSIB128): Renamed to ... | |
149 | (VECSIB128): This. | |
150 | (VecSIB256): Renamed to ... | |
151 | (VECSIB256): This. | |
152 | (VecSIB512): Renamed to ... | |
153 | (VECSIB512): This. | |
154 | (VecSIB): Renamed to ... | |
155 | (SIB): This. | |
156 | (i386_opcode_modifier): Replace vecsib with sib. | |
79b32e73 | 157 | * i386-opc.tbl (VecSIB128): New. |
63112cd6 L |
158 | (VecSIB256): Likewise. |
159 | (VecSIB512): Likewise. | |
79b32e73 | 160 | Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256 |
63112cd6 L |
161 | and VecSIB512, respectively. |
162 | ||
d1c36125 JB |
163 | 2020-06-26 Jan Beulich <jbeulich@suse.com> |
164 | ||
165 | * i386-dis.c: Adjust description of I macro. | |
166 | (x86_64_table): Drop use of I. | |
167 | (float_mem): Replace use of I. | |
168 | (putop): Remove handling of I. Adjust setting/clearing of "alt". | |
169 | ||
2a1bb84c JB |
170 | 2020-06-26 Jan Beulich <jbeulich@suse.com> |
171 | ||
172 | * i386-dis.c: (print_insn): Avoid straight assignment to | |
173 | priv.orig_sizeflag when processing -M sub-options. | |
174 | ||
8f570d62 JB |
175 | 2020-06-25 Jan Beulich <jbeulich@suse.com> |
176 | ||
177 | * i386-dis.c: Adjust description of J macro. | |
178 | (dis386, x86_64_table, mod_table): Replace J. | |
179 | (putop): Remove handling of J. | |
180 | ||
464dc4af JB |
181 | 2020-06-25 Jan Beulich <jbeulich@suse.com> |
182 | ||
183 | * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt. | |
184 | ||
589958d6 JB |
185 | 2020-06-25 Jan Beulich <jbeulich@suse.com> |
186 | ||
187 | * i386-dis.c: Adjust description of "LQ" macro. | |
188 | (dis386_twobyte): Use LQ for sysret. | |
189 | (putop): Adjust handling of LQ. | |
190 | ||
39ff0b81 NC |
191 | 2020-06-22 Nelson Chu <nelson.chu@sifive.com> |
192 | ||
193 | * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c. | |
194 | * riscv-dis.c: Include elfxx-riscv.h. | |
195 | ||
d27c357a JB |
196 | 2020-06-18 H.J. Lu <hongjiu.lu@intel.com> |
197 | ||
198 | * i386-dis.c (prefix_table): Revert the last vmgexit change. | |
199 | ||
6fde587f CL |
200 | 2020-06-17 Lili Cui <lili.cui@intel.com> |
201 | ||
202 | * i386-dis.c (prefix_table): Delete the incorrect vmgexit. | |
203 | ||
efe30057 L |
204 | 2020-06-14 H.J. Lu <hongjiu.lu@intel.com> |
205 | ||
206 | PR gas/26115 | |
207 | * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk. | |
208 | * i386-opc.tbl: Likewise. | |
209 | * i386-tbl.h: Regenerated. | |
210 | ||
d8af286f NC |
211 | 2020-06-12 Nelson Chu <nelson.chu@sifive.com> |
212 | ||
213 | * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9. | |
214 | ||
14962256 AC |
215 | 2020-06-11 Alex Coplan <alex.coplan@arm.com> |
216 | ||
217 | * aarch64-opc.c (SYSREG): New macro for describing system registers. | |
218 | (SR_CORE): Likewise. | |
219 | (SR_FEAT): Likewise. | |
220 | (SR_RNG): Likewise. | |
221 | (SR_V8_1): Likewise. | |
222 | (SR_V8_2): Likewise. | |
223 | (SR_V8_3): Likewise. | |
224 | (SR_V8_4): Likewise. | |
225 | (SR_PAN): Likewise. | |
226 | (SR_RAS): Likewise. | |
227 | (SR_SSBS): Likewise. | |
228 | (SR_SVE): Likewise. | |
229 | (SR_ID_PFR2): Likewise. | |
230 | (SR_PROFILE): Likewise. | |
231 | (SR_MEMTAG): Likewise. | |
232 | (SR_SCXTNUM): Likewise. | |
233 | (aarch64_sys_regs): Refactor to store feature information in the table. | |
234 | (aarch64_sys_reg_supported_p): Collapse logic for system registers | |
235 | that now describe their own features. | |
236 | (aarch64_pstatefield_supported_p): Likewise. | |
237 | ||
f9630fa6 L |
238 | 2020-06-09 H.J. Lu <hongjiu.lu@intel.com> |
239 | ||
240 | * i386-dis.c (prefix_table): Fix a typo in comments. | |
241 | ||
73239888 JB |
242 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
243 | ||
244 | * i386-dis.c (rex_ignored): Delete. | |
245 | (ckprefix): Drop rex_ignored initialization. | |
246 | (get_valid_dis386): Drop setting of rex_ignored. | |
247 | (print_insn): Drop checking of rex_ignored. Don't record data | |
248 | size prefix as used with VEX-and-alike encodings. | |
249 | ||
18897deb JB |
250 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
251 | ||
252 | * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2, | |
253 | MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators. | |
254 | (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete. | |
255 | (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define. | |
256 | (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16, | |
257 | VEX_0F12, and VEX_0F16. | |
258 | (vex_len_table): Use X for vmovlp* and vmovh*s. Drop | |
259 | VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries. | |
260 | (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE | |
261 | from movlps and movhlps. New MOD_0F12_PREFIX_2, | |
262 | MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and | |
263 | MOD_VEX_0F16_PREFIX_2 entries. | |
264 | ||
97e6786a JB |
265 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
266 | ||
267 | * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13, | |
268 | MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators. | |
269 | (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, | |
270 | PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, | |
271 | PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, | |
272 | PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6, | |
273 | EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0, | |
274 | EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2, | |
275 | EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, | |
276 | EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, | |
277 | EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, | |
278 | EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, | |
279 | EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, | |
280 | EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, | |
281 | EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, | |
282 | EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, | |
283 | EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, | |
284 | EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, | |
285 | EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, | |
286 | EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, | |
287 | EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, | |
288 | EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, | |
289 | EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, | |
290 | EVEX_W_0FC6_P_2): Delete. | |
291 | (print_insn): Add EVEX.W vs embedded prefix consistency check | |
292 | to prefix validation. | |
293 | * i386-dis-evex.h (evex_table): Don't further descend for | |
294 | vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX, | |
295 | and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17, | |
296 | and 0F2B. | |
297 | * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries. | |
298 | * i386-dis-evex-prefix.h: Don't further descend for vmovupX, | |
299 | vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX, | |
300 | vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases | |
301 | 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29. | |
302 | Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, | |
303 | PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B, | |
304 | PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56, | |
305 | PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries. | |
306 | * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, | |
307 | EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, | |
308 | EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, | |
309 | EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, | |
310 | EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, | |
311 | EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, | |
312 | EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, | |
313 | EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, | |
314 | EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, | |
315 | EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2, | |
316 | EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0, | |
317 | EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, | |
318 | EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0, | |
319 | EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2, | |
320 | EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0, | |
321 | EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2, | |
322 | EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0, | |
323 | EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries. | |
324 | ||
bf926894 JB |
325 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
326 | ||
327 | * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX, | |
328 | vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX. | |
329 | (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and | |
330 | vmovmskpX. | |
331 | (print_insn): Drop pointless check against bad_opcode. Split | |
332 | prefix validation into legacy and VEX-and-alike parts. | |
333 | (putop): Re-work 'X' macro handling. | |
334 | ||
a5aaedb9 JB |
335 | 2020-06-09 Jan Beulich <jbeulich@suse.com> |
336 | ||
337 | * i386-dis.c (MOD_0F51): Rename to ... | |
338 | (MOD_0F50): ... this. | |
339 | ||
26417f19 AC |
340 | 2020-06-08 Alex Coplan <alex.coplan@arm.com> |
341 | ||
342 | * arm-dis.c (arm_opcodes): Add dfb. | |
343 | (thumb32_opcodes): Add dfb. | |
344 | ||
8a6fb3f9 JB |
345 | 2020-06-08 Jan Beulich <jbeulich@suse.com> |
346 | ||
347 | * i386-opc.h (reg_entry): Const-qualify reg_name field. | |
348 | ||
1424c35d AM |
349 | 2020-06-06 Alan Modra <amodra@gmail.com> |
350 | ||
351 | * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10. | |
352 | ||
d3d1cc7b AM |
353 | 2020-06-05 Alan Modra <amodra@gmail.com> |
354 | ||
355 | * cgen-dis.c (hash_insn_array): Increase size of buf. Assert | |
356 | size is large enough. | |
357 | ||
d8740be1 JM |
358 | 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> |
359 | ||
360 | * disassemble.c (disassemble_init_for_target): Set endian_code for | |
361 | bpf targets. | |
362 | * bpf-desc.c: Regenerate. | |
363 | * bpf-opc.c: Likewise. | |
364 | * bpf-dis.c: Likewise. | |
365 | ||
e9bffec9 JM |
366 | 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com> |
367 | ||
368 | * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. | |
369 | (cgen_put_insn_value): Likewise. | |
370 | (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. | |
371 | * cgen-dis.in (print_insn): Likewise. | |
372 | * cgen-ibld.in (insert_1): Likewise. | |
373 | (insert_1): Likewise. | |
374 | (insert_insn_normal): Likewise. | |
375 | (extract_1): Likewise. | |
376 | * bpf-dis.c: Regenerate. | |
377 | * bpf-ibld.c: Likewise. | |
378 | * bpf-ibld.c: Likewise. | |
379 | * cgen-dis.in: Likewise. | |
380 | * cgen-ibld.in: Likewise. | |
381 | * cgen-opc.c: Likewise. | |
382 | * epiphany-dis.c: Likewise. | |
383 | * epiphany-ibld.c: Likewise. | |
384 | * fr30-dis.c: Likewise. | |
385 | * fr30-ibld.c: Likewise. | |
386 | * frv-dis.c: Likewise. | |
387 | * frv-ibld.c: Likewise. | |
388 | * ip2k-dis.c: Likewise. | |
389 | * ip2k-ibld.c: Likewise. | |
390 | * iq2000-dis.c: Likewise. | |
391 | * iq2000-ibld.c: Likewise. | |
392 | * lm32-dis.c: Likewise. | |
393 | * lm32-ibld.c: Likewise. | |
394 | * m32c-dis.c: Likewise. | |
395 | * m32c-ibld.c: Likewise. | |
396 | * m32r-dis.c: Likewise. | |
397 | * m32r-ibld.c: Likewise. | |
398 | * mep-dis.c: Likewise. | |
399 | * mep-ibld.c: Likewise. | |
400 | * mt-dis.c: Likewise. | |
401 | * mt-ibld.c: Likewise. | |
402 | * or1k-dis.c: Likewise. | |
403 | * or1k-ibld.c: Likewise. | |
404 | * xc16x-dis.c: Likewise. | |
405 | * xc16x-ibld.c: Likewise. | |
406 | * xstormy16-dis.c: Likewise. | |
407 | * xstormy16-ibld.c: Likewise. | |
408 | ||
b3db6d07 JM |
409 | 2020-06-04 Jose E. Marchesi <jemarch@gnu.org> |
410 | ||
411 | * cgen-dis.in (cpu_desc_list): New field `insn_endian'. | |
412 | (print_insn_): Handle instruction endian. | |
413 | * bpf-dis.c: Regenerate. | |
414 | * bpf-desc.c: Regenerate. | |
415 | * epiphany-dis.c: Likewise. | |
416 | * epiphany-desc.c: Likewise. | |
417 | * fr30-dis.c: Likewise. | |
418 | * fr30-desc.c: Likewise. | |
419 | * frv-dis.c: Likewise. | |
420 | * frv-desc.c: Likewise. | |
421 | * ip2k-dis.c: Likewise. | |
422 | * ip2k-desc.c: Likewise. | |
423 | * iq2000-dis.c: Likewise. | |
424 | * iq2000-desc.c: Likewise. | |
425 | * lm32-dis.c: Likewise. | |
426 | * lm32-desc.c: Likewise. | |
427 | * m32c-dis.c: Likewise. | |
428 | * m32c-desc.c: Likewise. | |
429 | * m32r-dis.c: Likewise. | |
430 | * m32r-desc.c: Likewise. | |
431 | * mep-dis.c: Likewise. | |
432 | * mep-desc.c: Likewise. | |
433 | * mt-dis.c: Likewise. | |
434 | * mt-desc.c: Likewise. | |
435 | * or1k-dis.c: Likewise. | |
436 | * or1k-desc.c: Likewise. | |
437 | * xc16x-dis.c: Likewise. | |
438 | * xc16x-desc.c: Likewise. | |
439 | * xstormy16-dis.c: Likewise. | |
440 | * xstormy16-desc.c: Likewise. | |
441 | ||
4ee4189f NC |
442 | 2020-06-03 Nick Clifton <nickc@redhat.com> |
443 | ||
444 | * po/sr.po: Updated Serbian translation. | |
445 | ||
44730156 NC |
446 | 2020-06-03 Nelson Chu <nelson.chu@sifive.com> |
447 | ||
448 | * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int. | |
449 | (riscv_get_priv_spec_class): Likewise. | |
450 | ||
3c3d0376 AM |
451 | 2020-06-01 Alan Modra <amodra@gmail.com> |
452 | ||
453 | * bpf-desc.c: Regenerate. | |
454 | ||
78c1c354 JM |
455 | 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com> |
456 | David Faust <david.faust@oracle.com> | |
457 | ||
458 | * bpf-desc.c: Regenerate. | |
459 | * bpf-opc.h: Likewise. | |
460 | * bpf-opc.c: Likewise. | |
461 | * bpf-dis.c: Likewise. | |
462 | ||
efcf5fb5 AM |
463 | 2020-05-28 Alan Modra <amodra@gmail.com> |
464 | ||
465 | * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative | |
466 | values. | |
467 | ||
ab382d64 AM |
468 | 2020-05-28 Alan Modra <amodra@gmail.com> |
469 | ||
470 | * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for | |
471 | immediates. | |
472 | (print_insn_ns32k): Revert last change. | |
473 | ||
151f5de4 NC |
474 | 2020-05-28 Nick Clifton <nickc@redhat.com> |
475 | ||
476 | * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to | |
477 | static. | |
478 | ||
25e1eca8 SL |
479 | 2020-05-26 Sandra Loosemore <sandra@codesourcery.com> |
480 | ||
481 | Fix extraction of signed constants in nios2 disassembler (again). | |
482 | ||
483 | * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to | |
484 | extractions of signed fields. | |
485 | ||
57b17940 SSF |
486 | 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> |
487 | ||
488 | * s390-opc.txt: Relocate vector load/store instructions with | |
489 | additional alignment parameter and change architecture level | |
490 | constraint from z14 to z13. | |
491 | ||
d96bf37b AM |
492 | 2020-05-21 Alan Modra <amodra@gmail.com> |
493 | ||
494 | * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout. | |
495 | * sparc-dis.c: Likewise. | |
496 | * tic4x-dis.c: Likewise. | |
497 | * xtensa-dis.c: Likewise. | |
498 | * bpf-desc.c: Regenerate. | |
499 | * epiphany-desc.c: Regenerate. | |
500 | * fr30-desc.c: Regenerate. | |
501 | * frv-desc.c: Regenerate. | |
502 | * ip2k-desc.c: Regenerate. | |
503 | * iq2000-desc.c: Regenerate. | |
504 | * lm32-desc.c: Regenerate. | |
505 | * m32c-desc.c: Regenerate. | |
506 | * m32r-desc.c: Regenerate. | |
507 | * mep-asm.c: Regenerate. | |
508 | * mep-desc.c: Regenerate. | |
509 | * mt-desc.c: Regenerate. | |
510 | * or1k-desc.c: Regenerate. | |
511 | * xc16x-desc.c: Regenerate. | |
512 | * xstormy16-desc.c: Regenerate. | |
513 | ||
8f595e9b NC |
514 | 2020-05-20 Nelson Chu <nelson.chu@sifive.com> |
515 | ||
516 | * riscv-opc.c (riscv_ext_version_table): The table used to store | |
517 | all information about the supported spec and the corresponding ISA | |
518 | versions. Currently, only Zicsr is supported to verify the | |
519 | correctness of Z sub extension settings. Others will be supported | |
520 | in the future patches. | |
521 | (struct isa_spec_t, isa_specs): List for all supported ISA spec | |
522 | classes and the corresponding strings. | |
523 | (riscv_get_isa_spec_class): New function. Get the corresponding ISA | |
524 | spec class by giving a ISA spec string. | |
525 | * riscv-opc.c (struct priv_spec_t): New structure. | |
526 | (struct priv_spec_t priv_specs): List for all supported privilege spec | |
527 | classes and the corresponding strings. | |
528 | (riscv_get_priv_spec_class): New function. Get the corresponding | |
529 | privilege spec class by giving a spec string. | |
530 | (riscv_get_priv_spec_name): New function. Get the corresponding | |
531 | privilege spec string by giving a CSR version class. | |
532 | * riscv-dis.c: Updated since DECLARE_CSR is changed. | |
533 | * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR | |
534 | according to the chosen version. Build a hash table riscv_csr_hash to | |
535 | store the valid CSR for the chosen pirv verison. Dump the direct | |
536 | CSR address rather than it's name if it is invalid. | |
537 | (parse_riscv_dis_option_without_args): New function. Parse the options | |
538 | without arguments. | |
539 | (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to | |
540 | parse the options without arguments first, and then handle the options | |
541 | with arguments. Add the new option -Mpriv-spec, which has argument. | |
542 | * riscv-dis.c (print_riscv_disassembler_options): Add description | |
543 | about the new OBJDUMP option. | |
544 | ||
3d205eb4 PB |
545 | 2020-05-19 Peter Bergner <bergner@linux.ibm.com> |
546 | ||
547 | * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new | |
548 | WC values on POWER10 sync, dcbf and wait instructions. | |
549 | (insert_pl, extract_pl): New functions. | |
550 | (L2OPT, LS, WC): Use insert_ls and extract_ls. | |
551 | (LS3): New , 3-bit L for sync. | |
552 | (LS3, L3OPT): New, 3-bit L for sync and dcbf. | |
553 | (SC2, PL): New, 2-bit SC and PL for sync and wait. | |
554 | (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks. | |
555 | (XOPL3, XWCPL, XSYNCLS): New opcode macros. | |
556 | (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync, | |
557 | plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics. | |
558 | <wait>: Enable PL operand on POWER10. | |
559 | <dcbf>: Enable L3OPT operand on POWER10. | |
560 | <sync>: Enable SC2 operand on POWER10. | |
561 | ||
a501eb44 SH |
562 | 2020-05-19 Stafford Horne <shorne@gmail.com> |
563 | ||
564 | PR 25184 | |
565 | * or1k-asm.c: Regenerate. | |
566 | * or1k-desc.c: Regenerate. | |
567 | * or1k-desc.h: Regenerate. | |
568 | * or1k-dis.c: Regenerate. | |
569 | * or1k-ibld.c: Regenerate. | |
570 | * or1k-opc.c: Regenerate. | |
571 | * or1k-opc.h: Regenerate. | |
572 | * or1k-opinst.c: Regenerate. | |
573 | ||
3b646889 AM |
574 | 2020-05-11 Alan Modra <amodra@gmail.com> |
575 | ||
576 | * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp, | |
577 | xsmaxcqp, xsmincqp. | |
578 | ||
9cc4ce88 AM |
579 | 2020-05-11 Alan Modra <amodra@gmail.com> |
580 | ||
581 | * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx, | |
582 | stxvrbx, stxvrhx, stxvrwx, stxvrdx. | |
583 | ||
5d57bc3f AM |
584 | 2020-05-11 Alan Modra <amodra@gmail.com> |
585 | ||
586 | * ppc-opc.c (powerpc_opcodes): Add xvtlsbb. | |
587 | ||
66ef5847 AM |
588 | 2020-05-11 Alan Modra <amodra@gmail.com> |
589 | ||
590 | * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr, | |
591 | vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr.. | |
592 | ||
4f3e9537 PB |
593 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
594 | ||
595 | * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New | |
596 | mnemonics. | |
597 | ||
ec40e91c AM |
598 | 2020-05-11 Alan Modra <amodra@gmail.com> |
599 | ||
600 | * ppc-opc.c (UIM8, P_U8XX4_MASK): Define. | |
601 | (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm, | |
602 | vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm. | |
603 | (prefix_opcodes): Add xxeval. | |
604 | ||
d7e97a76 AM |
605 | 2020-05-11 Alan Modra <amodra@gmail.com> |
606 | ||
607 | * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm, | |
608 | xxgenpcvwm, xxgenpcvdm. | |
609 | ||
fdefed7c AM |
610 | 2020-05-11 Alan Modra <amodra@gmail.com> |
611 | ||
612 | * ppc-opc.c (MP, VXVAM_MASK): Define. | |
613 | (VXVAPS_MASK): Use VXVA_MASK. | |
614 | (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm, | |
615 | vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm, | |
616 | vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm, | |
617 | vcntmbb, vcntmbh, vcntmbw, vcntmbd. | |
618 | ||
aa3c112f AM |
619 | 2020-05-11 Alan Modra <amodra@gmail.com> |
620 | Peter Bergner <bergner@linux.ibm.com> | |
621 | ||
622 | * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): | |
623 | New functions. | |
624 | (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK, | |
625 | YMSK2, XA6a, XA6ap, XB6a entries. | |
626 | (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define | |
627 | (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define. | |
628 | (PPCVSX4): Define. | |
629 | (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz, | |
630 | xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, | |
631 | xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, | |
632 | xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np, | |
633 | xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp, | |
634 | xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn, | |
635 | xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16. | |
636 | (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp, | |
637 | pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8, | |
638 | pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2, | |
639 | pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp, | |
640 | pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp, | |
641 | pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn, | |
642 | pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn. | |
643 | ||
6edbfd3b AM |
644 | 2020-05-11 Alan Modra <amodra@gmail.com> |
645 | ||
646 | * ppc-opc.c (insert_imm32, extract_imm32): New functions. | |
647 | (insert_xts, extract_xts): New functions. | |
648 | (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define. | |
649 | (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define. | |
650 | (VXRC_MASK, VXSH_MASK): Define. | |
651 | (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx, | |
652 | vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx, | |
653 | vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx, | |
654 | vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx, | |
655 | vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq. | |
656 | (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb, | |
657 | xxblendvh, xxblendvw, xxblendvd, xxpermx. | |
658 | ||
c7d7aea2 AM |
659 | 2020-05-11 Alan Modra <amodra@gmail.com> |
660 | ||
661 | * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi, | |
662 | vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd, | |
663 | vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd, | |
664 | vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz, | |
665 | xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq. | |
666 | ||
94ba9882 AM |
667 | 2020-05-11 Alan Modra <amodra@gmail.com> |
668 | ||
669 | * ppc-opc.c (insert_xtp, extract_xtp): New functions. | |
670 | (XTP, DQXP, DQXP_MASK): Define. | |
671 | (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx. | |
672 | (prefix_opcodes): Add plxvp and pstxvp. | |
673 | ||
f4791f1a AM |
674 | 2020-05-11 Alan Modra <amodra@gmail.com> |
675 | ||
676 | * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld, | |
677 | vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw, | |
678 | vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd. | |
679 | ||
3ff0a5ba PB |
680 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
681 | ||
682 | * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics. | |
683 | ||
afef4fe9 PB |
684 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
685 | ||
686 | * ppc-opc.c (insert_l1opt, extract_l1opt): New functions. | |
687 | (L1OPT): Define. | |
688 | (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10. | |
689 | ||
1224c05d PB |
690 | 2020-05-11 Peter Bergner <bergner@linux.ibm.com> |
691 | ||
692 | * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand. | |
693 | ||
6bbb0c05 AM |
694 | 2020-05-11 Alan Modra <amodra@gmail.com> |
695 | ||
696 | * ppc-dis.c (powerpc_init_dialect): Default to "power10". | |
697 | ||
7c1f4227 AM |
698 | 2020-05-11 Alan Modra <amodra@gmail.com> |
699 | ||
700 | * ppc-dis.c (ppc_opts): Add "power10" entry. | |
701 | (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming. | |
702 | * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses. | |
703 | ||
73199c2b NC |
704 | 2020-05-11 Nick Clifton <nickc@redhat.com> |
705 | ||
706 | * po/fr.po: Updated French translation. | |
707 | ||
09c1e68a AC |
708 | 2020-04-30 Alex Coplan <alex.coplan@arm.com> |
709 | ||
710 | * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2. | |
711 | * aarch64-opc.c (fields): Add entry for FLD_imm16_2. | |
712 | (operand_general_constraint_met_p): validate | |
713 | AARCH64_OPND_UNDEFINED. | |
714 | * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry | |
715 | for FLD_imm16_2. | |
716 | * aarch64-asm-2.c: Regenerated. | |
717 | * aarch64-dis-2.c: Regenerated. | |
718 | * aarch64-opc-2.c: Regenerated. | |
719 | ||
9654d51a NC |
720 | 2020-04-29 Nick Clifton <nickc@redhat.com> |
721 | ||
722 | PR 22699 | |
723 | * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC | |
724 | and SETRC insns. | |
725 | ||
c2e71e57 NC |
726 | 2020-04-29 Nick Clifton <nickc@redhat.com> |
727 | ||
728 | * po/sv.po: Updated Swedish translation. | |
729 | ||
5c936ef5 NC |
730 | 2020-04-29 Nick Clifton <nickc@redhat.com> |
731 | ||
732 | PR 22699 | |
733 | * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use | |
734 | IMM0_8S for arithmetic insns and IMM0_8U for logical insns. | |
735 | * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add | |
736 | IMM0_8U case. | |
737 | ||
bb2a1453 AS |
738 | 2020-04-21 Andreas Schwab <schwab@linux-m68k.org> |
739 | ||
740 | PR 25848 | |
741 | * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of | |
742 | cmpi only on m68020up and cpu32. | |
743 | ||
c2e5c986 SD |
744 | 2020-04-20 Sudakshina Das <sudi.das@arm.com> |
745 | ||
746 | * aarch64-asm.c (aarch64_ins_none): New. | |
747 | * aarch64-asm.h (ins_none): New declaration. | |
748 | * aarch64-dis.c (aarch64_ext_none): New. | |
749 | * aarch64-dis.h (ext_none): New declaration. | |
750 | * aarch64-opc.c (aarch64_print_operand): Update case for | |
751 | AARCH64_OPND_BARRIER_PSB. | |
752 | * aarch64-tbl.h (aarch64_opcode_table): Add tsb. | |
753 | (AARCH64_OPERANDS): Update inserter/extracter for | |
754 | AARCH64_OPND_BARRIER_PSB to use new dummy functions. | |
755 | * aarch64-asm-2.c: Regenerated. | |
756 | * aarch64-dis-2.c: Regenerated. | |
757 | * aarch64-opc-2.c: Regenerated. | |
758 | ||
8a6e1d1d SD |
759 | 2020-04-20 Sudakshina Das <sudi.das@arm.com> |
760 | ||
761 | * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove. | |
762 | (aarch64_feature_ras, RAS): Likewise. | |
763 | (aarch64_feature_stat_profile, STAT_PROFILE): Likewise. | |
764 | (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716, | |
765 | autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp, | |
766 | autiaz, autiasp, autibz, autibsp to be CORE_INSN. | |
767 | * aarch64-asm-2.c: Regenerated. | |
768 | * aarch64-dis-2.c: Regenerated. | |
769 | * aarch64-opc-2.c: Regenerated. | |
770 | ||
e409955d FS |
771 | 2020-04-17 Fredrik Strupe <fredrik@strupe.net> |
772 | ||
773 | * arm-dis.c (neon_opcodes): Fix VDUP instruction masks. | |
774 | (print_insn_neon): Support disassembly of conditional | |
775 | instructions. | |
776 | ||
c54a9b56 DF |
777 | 2020-02-16 David Faust <david.faust@oracle.com> |
778 | ||
779 | * bpf-desc.c: Regenerate. | |
780 | * bpf-desc.h: Likewise. | |
781 | * bpf-opc.c: Regenerate. | |
782 | * bpf-opc.h: Likewise. | |
783 | ||
bb651e8b CL |
784 | 2020-04-07 Lili Cui <lili.cui@intel.com> |
785 | ||
786 | * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1, | |
787 | (prefix_table): New instructions (see prefixes above). | |
788 | (rm_table): Likewise | |
789 | * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS, | |
790 | CPU_ANY_TSXLDTRK_FLAGS. | |
791 | (cpu_flags): Add CpuTSXLDTRK. | |
792 | * i386-opc.h (enum): Add CpuTSXLDTRK. | |
793 | (i386_cpu_flags): Add cputsxldtrk. | |
794 | * i386-opc.tbl: Add XSUSPLDTRK insns. | |
795 | * i386-init.h: Regenerate. | |
796 | * i386-tbl.h: Likewise. | |
797 | ||
4b27d27c L |
798 | 2020-04-02 Lili Cui <lili.cui@intel.com> |
799 | ||
800 | * i386-dis.c (prefix_table): New instructions serialize. | |
801 | * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS, | |
802 | CPU_ANY_SERIALIZE_FLAGS. | |
803 | (cpu_flags): Add CpuSERIALIZE. | |
804 | * i386-opc.h (enum): Add CpuSERIALIZE. | |
805 | (i386_cpu_flags): Add cpuserialize. | |
806 | * i386-opc.tbl: Add SERIALIZE insns. | |
807 | * i386-init.h: Regenerate. | |
808 | * i386-tbl.h: Likewise. | |
809 | ||
832a5807 AM |
810 | 2020-03-26 Alan Modra <amodra@gmail.com> |
811 | ||
812 | * disassemble.h (opcodes_assert): Declare. | |
813 | (OPCODES_ASSERT): Define. | |
814 | * disassemble.c: Don't include assert.h. Include opintl.h. | |
815 | (opcodes_assert): New function. | |
816 | * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT. | |
817 | (bfd_h8_disassemble): Reduce size of data array. Correctly | |
818 | calculate maxlen. Omit insn decoding when insn length exceeds | |
819 | maxlen. Exit from nibble loop when looking for E, before | |
820 | accessing next data byte. Move processing of E outside loop. | |
821 | Replace tests of maxlen in loop with assertions. | |
822 | ||
4c4addbe AM |
823 | 2020-03-26 Alan Modra <amodra@gmail.com> |
824 | ||
825 | * arc-dis.c (find_format): Init needs_limm. Simplify use of limm. | |
826 | ||
a18cd0ca AM |
827 | 2020-03-25 Alan Modra <amodra@gmail.com> |
828 | ||
829 | * z80-dis.c (suffix): Init mybuf. | |
830 | ||
57cb32b3 AM |
831 | 2020-03-22 Alan Modra <amodra@gmail.com> |
832 | ||
833 | * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that | |
834 | successflly read from section. | |
835 | ||
beea5cc1 AM |
836 | 2020-03-22 Alan Modra <amodra@gmail.com> |
837 | ||
838 | * arc-dis.c (find_format): Use ISO C string concatenation rather | |
839 | than line continuation within a string. Don't access needs_limm | |
840 | before testing opcode != NULL. | |
841 | ||
03704c77 AM |
842 | 2020-03-22 Alan Modra <amodra@gmail.com> |
843 | ||
844 | * ns32k-dis.c (print_insn_arg): Update comment. | |
845 | (print_insn_ns32k): Reduce size of index_offset array, and | |
846 | initialize, passing -1 to print_insn_arg for args that are not | |
847 | an index. Don't exit arg loop early. Abort on bad arg number. | |
848 | ||
d1023b5d AM |
849 | 2020-03-22 Alan Modra <amodra@gmail.com> |
850 | ||
851 | * s12z-dis.c (abstract_read_memory): Don't print error on EOI. | |
852 | * s12z-opc.c: Formatting. | |
853 | (operands_f): Return an int. | |
854 | (opr_n_bytes_p1): Return -1 on reaching buffer memory limit. | |
855 | (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes), | |
856 | (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes), | |
857 | (exg_sex_discrim): Likewise. | |
858 | (create_immediate_operand, create_bitfield_operand), | |
859 | (create_register_operand_with_size, create_register_all_operand), | |
860 | (create_register_all16_operand, create_simple_memory_operand), | |
861 | (create_memory_operand, create_memory_auto_operand): Don't | |
862 | segfault on malloc failure. | |
863 | (z_ext24_decode): Return an int status, negative on fail, zero | |
864 | on success. | |
865 | (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2), | |
866 | (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base), | |
867 | (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7), | |
868 | (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x), | |
869 | (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode), | |
870 | (mov_imm_opr, ld_18bit_decode, exg_sex_decode), | |
871 | (loop_primitive_decode, shift_decode, psh_pul_decode), | |
872 | (bit_field_decode): Similarly. | |
873 | (z_decode_signed_value, decode_signed_value): Similarly. Add arg | |
874 | to return value, update callers. | |
875 | (x_opr_decode_with_size): Check all reads, returning NULL on fail. | |
876 | Don't segfault on NULL operand. | |
877 | (decode_operation): Return OP_INVALID on first fail. | |
878 | (decode_s12z): Check all reads, returning -1 on fail. | |
879 | ||
340f3ac8 AM |
880 | 2020-03-20 Alan Modra <amodra@gmail.com> |
881 | ||
882 | * metag-dis.c (print_insn_metag): Don't ignore status from | |
883 | read_memory_func. | |
884 | ||
fe90ae8a AM |
885 | 2020-03-20 Alan Modra <amodra@gmail.com> |
886 | ||
887 | * nds32-dis.c (print_insn_nds32): Remove unnecessary casts. | |
888 | Initialize parts of buffer not written when handling a possible | |
889 | 2-byte insn at end of section. Don't attempt decoding of such | |
890 | an insn by the 4-byte machinery. | |
891 | ||
833d919c AM |
892 | 2020-03-20 Alan Modra <amodra@gmail.com> |
893 | ||
894 | * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of | |
895 | partially filled buffer. Prevent lookup of 4-byte insns when | |
896 | only VLE 2-byte insns are possible due to section size. Print | |
897 | ".word" rather than ".long" for 2-byte leftovers. | |
898 | ||
327ef784 NC |
899 | 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com> |
900 | ||
901 | PR 25641 | |
902 | * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes. | |
903 | ||
1673df32 JB |
904 | 2020-03-13 Jan Beulich <jbeulich@suse.com> |
905 | ||
906 | * i386-dis.c (X86_64_0D): Rename to ... | |
907 | (X86_64_0E): ... this. | |
908 | ||
384f3689 L |
909 | 2020-03-09 H.J. Lu <hongjiu.lu@intel.com> |
910 | ||
911 | * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP). | |
912 | * Makefile.in: Regenerated. | |
913 | ||
865e2027 JB |
914 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
915 | ||
916 | * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp* | |
917 | 3-operand pseudos. | |
918 | * i386-tbl.h: Re-generate. | |
919 | ||
2f13234b JB |
920 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
921 | ||
922 | * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*, | |
923 | vprot*, vpsha*, and vpshl*. | |
924 | * i386-tbl.h: Re-generate. | |
925 | ||
3fabc179 JB |
926 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
927 | ||
928 | * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps, | |
929 | vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops. | |
930 | * i386-tbl.h: Re-generate. | |
931 | ||
3677e4c1 JB |
932 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
933 | ||
934 | * i386-gen.c (set_bitfield): Ignore zero-length field names. | |
935 | * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps, | |
936 | cmpss, cmppd, and cmpsd 2-operand pseudo-ops. | |
937 | * i386-tbl.h: Re-generate. | |
938 | ||
4c4898e8 JB |
939 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
940 | ||
941 | * i386-gen.c (struct template_arg, struct template_instance, | |
942 | struct template_param, struct template, templates, | |
943 | parse_template, expand_templates): New. | |
944 | (process_i386_opcodes): Various local variables moved to | |
945 | expand_templates. Call parse_template and expand_templates. | |
946 | * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc. | |
947 | * i386-tbl.h: Re-generate. | |
948 | ||
bc49bfd8 JB |
949 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
950 | ||
951 | * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph, | |
952 | vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate | |
953 | register and memory source templates. Replace VexW= by VexW* | |
954 | where applicable. | |
955 | * i386-tbl.h: Re-generate. | |
956 | ||
4873e243 JB |
957 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
958 | ||
959 | * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace | |
960 | VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable. | |
961 | * i386-tbl.h: Re-generate. | |
962 | ||
672a349b JB |
963 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
964 | ||
965 | * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax. | |
966 | * i386-tbl.h: Re-generate. | |
967 | ||
4ed21b58 JB |
968 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
969 | ||
970 | * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants. | |
971 | (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps, | |
972 | pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use | |
973 | VexW0 on SSE2AVX variants. | |
974 | (vmovq): Drop NoRex64 from XMM/XMM variants. | |
975 | (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb, | |
976 | vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where | |
977 | applicable use VexW0. | |
978 | * i386-tbl.h: Re-generate. | |
979 | ||
643bb870 JB |
980 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
981 | ||
982 | * i386-gen.c (opcode_modifiers): Remove Rex64 field. | |
983 | * i386-opc.h (Rex64): Delete. | |
984 | (struct i386_opcode_modifier): Remove rex64 field. | |
985 | * i386-opc.tbl (crc32): Drop Rex64. | |
986 | Replace Rex64 with Size64 everywhere else. | |
987 | * i386-tbl.h: Re-generate. | |
988 | ||
a23b33b3 JB |
989 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
990 | ||
991 | * i386-dis.c (OP_E_memory): Exclude recording of used address | |
992 | prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit | |
993 | addressed memory operands for MPX insns. | |
994 | ||
a0497384 JB |
995 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
996 | ||
997 | * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept, | |
998 | invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx, | |
999 | adox, mwaitx, rdpid, movdiri): Add IgnoreSize. | |
1000 | (ptwrite): Split into non-64-bit and 64-bit forms. | |
1001 | * i386-tbl.h: Re-generate. | |
1002 | ||
b630c145 JB |
1003 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
1004 | ||
1005 | * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand | |
1006 | template. | |
1007 | * i386-tbl.h: Re-generate. | |
1008 | ||
a847e322 JB |
1009 | 2020-03-04 Jan Beulich <jbeulich@suse.com> |
1010 | ||
1011 | * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New. | |
1012 | (prefix_table): Move vmmcall here. Add vmgexit. | |
1013 | (rm_table): Replace vmmcall entry by prefix_table[] escape. | |
1014 | * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry. | |
1015 | (cpu_flags): Add CpuSEV_ES entry. | |
1016 | * i386-opc.h (CpuSEV_ES): New. | |
1017 | (union i386_cpu_flags): Add cpusev_es field. | |
1018 | * i386-opc.tbl (vmgexit): New. | |
1019 | * i386-init.h, i386-tbl.h: Re-generate. | |
1020 | ||
3cd7f3e3 L |
1021 | 2020-03-03 H.J. Lu <hongjiu.lu@intel.com> |
1022 | ||
1023 | * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize | |
1024 | with MnemonicSize. | |
1025 | * i386-opc.h (IGNORESIZE): New. | |
1026 | (DEFAULTSIZE): Likewise. | |
1027 | (IgnoreSize): Removed. | |
1028 | (DefaultSize): Likewise. | |
1029 | (MnemonicSize): New. | |
1030 | (i386_opcode_modifier): Replace ignoresize/defaultsize with | |
1031 | mnemonicsize. | |
1032 | * i386-opc.tbl (IgnoreSize): New. | |
1033 | (DefaultSize): Likewise. | |
1034 | * i386-tbl.h: Regenerated. | |
1035 | ||
b8ba1385 SB |
1036 | 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com> |
1037 | ||
1038 | PR 25627 | |
1039 | * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX | |
1040 | instructions. | |
1041 | ||
10d97a0f L |
1042 | 2020-03-03 H.J. Lu <hongjiu.lu@intel.com> |
1043 | ||
1044 | PR gas/25622 | |
1045 | * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd, | |
1046 | vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax. | |
1047 | * i386-tbl.h: Regenerated. | |
1048 | ||
dc1e8a47 AM |
1049 | 2020-02-26 Alan Modra <amodra@gmail.com> |
1050 | ||
1051 | * aarch64-asm.c: Indent labels correctly. | |
1052 | * aarch64-dis.c: Likewise. | |
1053 | * aarch64-gen.c: Likewise. | |
1054 | * aarch64-opc.c: Likewise. | |
1055 | * alpha-dis.c: Likewise. | |
1056 | * i386-dis.c: Likewise. | |
1057 | * nds32-asm.c: Likewise. | |
1058 | * nfp-dis.c: Likewise. | |
1059 | * visium-dis.c: Likewise. | |
1060 | ||
265b4673 CZ |
1061 | 2020-02-25 Claudiu Zissulescu <claziss@gmail.com> |
1062 | ||
1063 | * arc-regs.h (int_vector_base): Make it available for all ARC | |
1064 | CPUs. | |
1065 | ||
bd0cf5a6 NC |
1066 | 2020-02-20 Nelson Chu <nelson.chu@sifive.com> |
1067 | ||
1068 | * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is | |
1069 | changed. | |
1070 | ||
fa164239 JW |
1071 | 2020-02-19 Nelson Chu <nelson.chu@sifive.com> |
1072 | ||
1073 | * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed | |
1074 | c.mv/c.li if rs1 is zero. | |
1075 | ||
272a84b1 L |
1076 | 2020-02-17 H.J. Lu <hongjiu.lu@intel.com> |
1077 | ||
1078 | * i386-gen.c (cpu_flag_init): Replace CpuABM with | |
1079 | CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add | |
1080 | CPU_POPCNT_FLAGS. | |
1081 | (cpu_flags): Remove CpuABM. Add CpuPOPCNT. | |
1082 | * i386-opc.h (CpuABM): Removed. | |
1083 | (CpuPOPCNT): New. | |
1084 | (i386_cpu_flags): Remove cpuabm. Add cpupopcnt. | |
1085 | * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on | |
1086 | popcnt. Remove CpuABM from lzcnt. | |
1087 | * i386-init.h: Regenerated. | |
1088 | * i386-tbl.h: Likewise. | |
1089 | ||
1f730c46 JB |
1090 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
1091 | ||
1092 | * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss): | |
1093 | Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/ | |
1094 | VexW1 instead of open-coding them. | |
1095 | * i386-tbl.h: Re-generate. | |
1096 | ||
c8f8eebc JB |
1097 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
1098 | ||
1099 | * i386-opc.tbl (AddrPrefixOpReg): Define. | |
1100 | (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx, | |
1101 | umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64 | |
1102 | templates. Drop NoRex64. | |
1103 | * i386-tbl.h: Re-generate. | |
1104 | ||
b9915cbc JB |
1105 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
1106 | ||
1107 | PR gas/6518 | |
1108 | * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq, | |
1109 | vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms | |
1110 | into Intel syntax instance (with Unpsecified) and AT&T one | |
1111 | (without). | |
1112 | (vcvtneps2bf16): Likewise, along with folding the two so far | |
1113 | separate ones. | |
1114 | * i386-tbl.h: Re-generate. | |
1115 | ||
ce504911 L |
1116 | 2020-02-16 H.J. Lu <hongjiu.lu@intel.com> |
1117 | ||
1118 | * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from | |
1119 | CPU_ANY_SSE4A_FLAGS. | |
1120 | ||
dabec65d AM |
1121 | 2020-02-17 Alan Modra <amodra@gmail.com> |
1122 | ||
1123 | * i386-gen.c (cpu_flag_init): Correct last change. | |
1124 | ||
af5c13b0 L |
1125 | 2020-02-16 H.J. Lu <hongjiu.lu@intel.com> |
1126 | ||
1127 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove | |
1128 | CPU_ANY_SSE4_FLAGS. | |
1129 | ||
6867aac0 L |
1130 | 2020-02-14 H.J. Lu <hongjiu.lu@intel.com> |
1131 | ||
1132 | * i386-opc.tbl (movsx): Remove Intel syntax comments. | |
1133 | (movzx): Likewise. | |
1134 | ||
65fca059 JB |
1135 | 2020-02-14 Jan Beulich <jbeulich@suse.com> |
1136 | ||
1137 | PR gas/25438 | |
1138 | * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as | |
1139 | destination for Cpu64-only variant. | |
1140 | (movzx): Fold patterns. | |
1141 | * i386-tbl.h: Re-generate. | |
1142 | ||
7deea9aa JB |
1143 | 2020-02-13 Jan Beulich <jbeulich@suse.com> |
1144 | ||
1145 | * i386-gen.c (cpu_flag_init): Move CpuSSE4a from | |
1146 | CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add | |
1147 | CPU_ANY_SSE4_FLAGS entry. | |
1148 | * i386-init.h: Re-generate. | |
1149 | ||
6c0946d0 JB |
1150 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
1151 | ||
1152 | * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form | |
1153 | with Unspecified, making the present one AT&T syntax only. | |
1154 | * i386-tbl.h: Re-generate. | |
1155 | ||
ddb56fe6 JB |
1156 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
1157 | ||
1158 | * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants. | |
1159 | * i386-tbl.h: Re-generate. | |
1160 | ||
5990e377 JB |
1161 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
1162 | ||
1163 | PR gas/24546 | |
1164 | * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. | |
1165 | * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into | |
1166 | Amd64 and Intel64 templates. | |
1167 | (call, jmp): Likewise for far indirect variants. Dro | |
1168 | Unspecified. | |
1169 | * i386-tbl.h: Re-generate. | |
1170 | ||
50128d0c JB |
1171 | 2020-02-11 Jan Beulich <jbeulich@suse.com> |
1172 | ||
1173 | * i386-gen.c (opcode_modifiers): Remove ShortForm entry. | |
1174 | * i386-opc.h (ShortForm): Delete. | |
1175 | (struct i386_opcode_modifier): Remove shortform field. | |
1176 | * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld, | |
1177 | fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub, | |
1178 | fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp, | |
1179 | ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq): | |
1180 | Drop ShortForm. | |
1181 | * i386-tbl.h: Re-generate. | |
1182 | ||
1e05b5c4 JB |
1183 | 2020-02-11 Jan Beulich <jbeulich@suse.com> |
1184 | ||
1185 | * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip, | |
1186 | fucompi): Drop ShortForm from operand-less templates. | |
1187 | * i386-tbl.h: Re-generate. | |
1188 | ||
2f5dd314 AM |
1189 | 2020-02-11 Alan Modra <amodra@gmail.com> |
1190 | ||
1191 | * cgen-ibld.in (extract_normal): Set *valuep on all return paths. | |
1192 | * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, | |
1193 | * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, | |
1194 | * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, | |
1195 | * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate. | |
1196 | ||
5aae9ae9 MM |
1197 | 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> |
1198 | ||
1199 | * arm-dis.c (print_insn_cde): Define 'V' parse character. | |
1200 | (cde_opcodes): Add VCX* instructions. | |
1201 | ||
4934a27c MM |
1202 | 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> |
1203 | Matthew Malcomson <matthew.malcomson@arm.com> | |
1204 | ||
1205 | * arm-dis.c (struct cdeopcode32): New. | |
1206 | (CDE_OPCODE): New macro. | |
1207 | (cde_opcodes): New disassembly table. | |
1208 | (regnames): New option to table. | |
1209 | (cde_coprocs): New global variable. | |
1210 | (print_insn_cde): New | |
1211 | (print_insn_thumb32): Use print_insn_cde. | |
1212 | (parse_arm_disassembler_options): Parse coprocN args. | |
1213 | ||
4b5aaf5f L |
1214 | 2020-02-10 H.J. Lu <hongjiu.lu@intel.com> |
1215 | ||
1216 | PR gas/25516 | |
1217 | * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 | |
1218 | with ISA64. | |
1219 | * i386-opc.h (AMD64): Removed. | |
1220 | (Intel64): Likewose. | |
1221 | (AMD64): New. | |
1222 | (INTEL64): Likewise. | |
1223 | (INTEL64ONLY): Likewise. | |
1224 | (i386_opcode_modifier): Replace amd64 and intel64 with isa64. | |
1225 | * i386-opc.tbl (Amd64): New. | |
1226 | (Intel64): Likewise. | |
1227 | (Intel64Only): Likewise. | |
1228 | Replace AMD64 with Amd64. Update sysenter/sysenter with | |
1229 | Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. | |
1230 | * i386-tbl.h: Regenerated. | |
1231 | ||
9fc0b501 SB |
1232 | 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com> |
1233 | ||
1234 | PR 25469 | |
1235 | * z80-dis.c: Add support for GBZ80 opcodes. | |
1236 | ||
c5d7be0c AM |
1237 | 2020-02-04 Alan Modra <amodra@gmail.com> |
1238 | ||
1239 | * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned. | |
1240 | ||
44e4546f AM |
1241 | 2020-02-03 Alan Modra <amodra@gmail.com> |
1242 | ||
1243 | * m32c-ibld.c: Regenerate. | |
1244 | ||
b2b1453a AM |
1245 | 2020-02-01 Alan Modra <amodra@gmail.com> |
1246 | ||
1247 | * frv-ibld.c: Regenerate. | |
1248 | ||
4102be5c JB |
1249 | 2020-01-31 Jan Beulich <jbeulich@suse.com> |
1250 | ||
1251 | * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete. | |
1252 | (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label. | |
1253 | (OP_E_memory): Replace xmm_mdq_mode case label by | |
1254 | vex_scalar_w_dq_mode one. | |
1255 | * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar. | |
1256 | ||
825bd36c JB |
1257 | 2020-01-31 Jan Beulich <jbeulich@suse.com> |
1258 | ||
1259 | * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete. | |
1260 | (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode, | |
1261 | vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments. | |
1262 | (intel_operand_size): Drop vex_w_dq_mode case label. | |
1263 | ||
c3036ed0 RS |
1264 | 2020-01-31 Richard Sandiford <richard.sandiford@arm.com> |
1265 | ||
1266 | * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt. | |
1267 | Remove C_SCAN_MOVPRFX for SVE bfcvtnt. | |
1268 | ||
0c115f84 AM |
1269 | 2020-01-30 Alan Modra <amodra@gmail.com> |
1270 | ||
1271 | * m32c-ibld.c: Regenerate. | |
1272 | ||
bd434cc4 JM |
1273 | 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> |
1274 | ||
1275 | * bpf-opc.c: Regenerate. | |
1276 | ||
aeab2b26 JB |
1277 | 2020-01-30 Jan Beulich <jbeulich@suse.com> |
1278 | ||
1279 | * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators. | |
1280 | (dis386): Use them to replace C2/C3 table entries. | |
1281 | (x86_64_table): Add X86_64_C2 and X86_64_C3 entries. | |
1282 | * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64 | |
1283 | ones. Use Size64 instead of DefaultSize on Intel64 ones. | |
1284 | * i386-tbl.h: Re-generate. | |
1285 | ||
62b3f548 JB |
1286 | 2020-01-30 Jan Beulich <jbeulich@suse.com> |
1287 | ||
1288 | * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword | |
1289 | forms. | |
1290 | (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop | |
1291 | DefaultSize. | |
1292 | * i386-tbl.h: Re-generate. | |
1293 | ||
1bd8ae10 AM |
1294 | 2020-01-30 Alan Modra <amodra@gmail.com> |
1295 | ||
1296 | * tic4x-dis.c (tic4x_dp): Make unsigned. | |
1297 | ||
bc31405e L |
1298 | 2020-01-27 H.J. Lu <hongjiu.lu@intel.com> |
1299 | Jan Beulich <jbeulich@suse.com> | |
1300 | ||
1301 | PR binutils/25445 | |
1302 | * i386-dis.c (MOVSXD_Fixup): New function. | |
1303 | (movsxd_mode): New enum. | |
1304 | (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd. | |
1305 | (intel_operand_size): Handle movsxd_mode. | |
1306 | (OP_E_register): Likewise. | |
1307 | (OP_G): Likewise. | |
1308 | * i386-opc.tbl: Remove Rex64 and allow 32-bit destination | |
1309 | register on movsxd. Add movsxd with 16-bit destination register | |
1310 | for AMD64 and Intel64 ISAs. | |
1311 | * i386-tbl.h: Regenerated. | |
1312 | ||
7568c93b TC |
1313 | 2020-01-27 Tamar Christina <tamar.christina@arm.com> |
1314 | ||
1315 | PR 25403 | |
1316 | * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. | |
1317 | * aarch64-asm-2.c: Regenerate | |
1318 | * aarch64-dis-2.c: Likewise. | |
1319 | * aarch64-opc-2.c: Likewise. | |
1320 | ||
c006a730 JB |
1321 | 2020-01-21 Jan Beulich <jbeulich@suse.com> |
1322 | ||
1323 | * i386-opc.tbl (sysret): Drop DefaultSize. | |
1324 | * i386-tbl.h: Re-generate. | |
1325 | ||
c906a69a JB |
1326 | 2020-01-21 Jan Beulich <jbeulich@suse.com> |
1327 | ||
1328 | * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and | |
1329 | Dword. | |
1330 | (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword. | |
1331 | * i386-tbl.h: Re-generate. | |
1332 | ||
26916852 NC |
1333 | 2020-01-20 Nick Clifton <nickc@redhat.com> |
1334 | ||
1335 | * po/de.po: Updated German translation. | |
1336 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
1337 | * po/uk.po: Updated Ukranian translation. | |
1338 | ||
4d6cbb64 AM |
1339 | 2020-01-20 Alan Modra <amodra@gmail.com> |
1340 | ||
1341 | * hppa-dis.c (fput_const): Remove useless cast. | |
1342 | ||
2bddb71a AM |
1343 | 2020-01-20 Alan Modra <amodra@gmail.com> |
1344 | ||
1345 | * arm-dis.c (print_insn_arm): Wrap 'T' value. | |
1346 | ||
1b1bb2c6 NC |
1347 | 2020-01-18 Nick Clifton <nickc@redhat.com> |
1348 | ||
1349 | * configure: Regenerate. | |
1350 | * po/opcodes.pot: Regenerate. | |
1351 | ||
ae774686 NC |
1352 | 2020-01-18 Nick Clifton <nickc@redhat.com> |
1353 | ||
1354 | Binutils 2.34 branch created. | |
1355 | ||
07f1f3aa CB |
1356 | 2020-01-17 Christian Biesinger <cbiesinger@google.com> |
1357 | ||
1358 | * opintl.h: Fix spelling error (seperate). | |
1359 | ||
42e04b36 L |
1360 | 2020-01-17 H.J. Lu <hongjiu.lu@intel.com> |
1361 | ||
1362 | * i386-opc.tbl: Add {vex} pseudo prefix. | |
1363 | * i386-tbl.h: Regenerated. | |
1364 | ||
2da2eaf4 AV |
1365 | 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
1366 | ||
1367 | PR 25376 | |
1368 | * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. | |
1369 | (neon_opcodes): Likewise. | |
1370 | (select_arm_features): Make sure we enable MVE bits when selecting | |
1371 | armv8.1-m.main. Make sure we do not enable MVE bits when not selecting | |
1372 | any architecture. | |
1373 | ||
d0849eed JB |
1374 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
1375 | ||
1376 | * i386-opc.tbl: Drop stale comment from XOP section. | |
1377 | ||
9cf70a44 JB |
1378 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
1379 | ||
1380 | * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms. | |
1381 | (extractps): Add VexWIG to SSE2AVX forms. | |
1382 | * i386-tbl.h: Re-generate. | |
1383 | ||
4814632e JB |
1384 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
1385 | ||
1386 | * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop | |
1387 | Size64 from and use VexW1 on SSE2AVX forms. | |
1388 | (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from | |
1389 | VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1. | |
1390 | * i386-tbl.h: Re-generate. | |
1391 | ||
aad09917 AM |
1392 | 2020-01-15 Alan Modra <amodra@gmail.com> |
1393 | ||
1394 | * tic4x-dis.c (tic4x_version): Make unsigned long. | |
1395 | (optab, optab_special, registernames): New file scope vars. | |
1396 | (tic4x_print_register): Set up registernames rather than | |
1397 | malloc'd registertable. | |
1398 | (tic4x_disassemble): Delete optable and optable_special. Use | |
1399 | optab and optab_special instead. Throw away old optab, | |
1400 | optab_special and registernames when info->mach changes. | |
1401 | ||
7a6bf3be SB |
1402 | 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com> |
1403 | ||
1404 | PR 25377 | |
1405 | * z80-dis.c (suffix): Use .db instruction to generate double | |
1406 | prefix. | |
1407 | ||
ca1eaac0 AM |
1408 | 2020-01-14 Alan Modra <amodra@gmail.com> |
1409 | ||
1410 | * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short | |
1411 | values to unsigned before shifting. | |
1412 | ||
1d67fe3b TT |
1413 | 2020-01-13 Thomas Troeger <tstroege@gmx.de> |
1414 | ||
1415 | * arm-dis.c (print_insn_arm): Fill in insn info fields for control | |
1416 | flow instructions. | |
1417 | (print_insn_thumb16, print_insn_thumb32): Likewise. | |
1418 | (print_insn): Initialize the insn info. | |
1419 | * i386-dis.c (print_insn): Initialize the insn info fields, and | |
1420 | detect jumps. | |
1421 | ||
5e4f7e05 CZ |
1422 | 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> |
1423 | ||
1424 | * arc-opc.c (C_NE): Make it required. | |
1425 | ||
b9fe6b8a CZ |
1426 | 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> |
1427 | ||
1428 | * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo | |
1429 | reserved register name. | |
1430 | ||
90dee485 AM |
1431 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1432 | ||
1433 | * ns32k-dis.c (Is_gen): Use strchr, add 'f'. | |
1434 | (print_insn_ns32k): Adjust ioffset for 'f' index_offset. | |
1435 | ||
febda64f AM |
1436 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1437 | ||
1438 | * wasm32-dis.c (print_insn_wasm32): Localise variables. Store | |
1439 | result of wasm_read_leb128 in a uint64_t and check that bits | |
1440 | are not lost when copying to other locals. Use uint32_t for | |
1441 | most locals. Use PRId64 when printing int64_t. | |
1442 | ||
df08b588 AM |
1443 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1444 | ||
1445 | * score-dis.c: Formatting. | |
1446 | * score7-dis.c: Formatting. | |
1447 | ||
b2c759ce AM |
1448 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1449 | ||
1450 | * score-dis.c (print_insn_score48): Use unsigned variables for | |
1451 | unsigned values. Don't left shift negative values. | |
1452 | (print_insn_score32): Likewise. | |
1453 | * score7-dis.c (print_insn_score32, print_insn_score16): Likewise. | |
1454 | ||
5496abe1 AM |
1455 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1456 | ||
1457 | * tic4x-dis.c (tic4x_print_register): Remove dead code. | |
1458 | ||
202e762b AM |
1459 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1460 | ||
1461 | * fr30-ibld.c: Regenerate. | |
1462 | ||
7ef412cf AM |
1463 | 2020-01-13 Alan Modra <amodra@gmail.com> |
1464 | ||
1465 | * xgate-dis.c (print_insn): Don't left shift signed value. | |
1466 | (ripBits): Formatting, use 1u. | |
1467 | ||
7f578b95 AM |
1468 | 2020-01-10 Alan Modra <amodra@gmail.com> |
1469 | ||
1470 | * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned. | |
1471 | * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval. | |
1472 | ||
441af85b AM |
1473 | 2020-01-10 Alan Modra <amodra@gmail.com> |
1474 | ||
1475 | * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG, | |
1476 | and XRREG value earlier to avoid a shift with negative exponent. | |
1477 | * m10200-dis.c (disassemble): Similarly. | |
1478 | ||
bce58db4 NC |
1479 | 2020-01-09 Nick Clifton <nickc@redhat.com> |
1480 | ||
1481 | PR 25224 | |
1482 | * z80-dis.c (ld_ii_ii): Use correct cast. | |
1483 | ||
40c75bc8 SB |
1484 | 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com> |
1485 | ||
1486 | PR 25224 | |
1487 | * z80-dis.c (ld_ii_ii): Use character constant when checking | |
1488 | opcode byte value. | |
1489 | ||
d835a58b JB |
1490 | 2020-01-09 Jan Beulich <jbeulich@suse.com> |
1491 | ||
1492 | * i386-dis.c (SEP_Fixup): New. | |
1493 | (SEP): Define. | |
1494 | (dis386_twobyte): Use it for sysenter/sysexit. | |
1495 | (enum x86_64_isa): Change amd64 enumerator to value 1. | |
1496 | (OP_J): Compare isa64 against intel64 instead of amd64. | |
1497 | * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64 | |
1498 | forms. | |
1499 | * i386-tbl.h: Re-generate. | |
1500 | ||
030a2e78 AM |
1501 | 2020-01-08 Alan Modra <amodra@gmail.com> |
1502 | ||
1503 | * z8k-dis.c: Include libiberty.h | |
1504 | (instr_data_s): Make max_fetched unsigned. | |
1505 | (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. | |
1506 | Don't exceed byte_info bounds. | |
1507 | (output_instr): Make num_bytes unsigned. | |
1508 | (unpack_instr): Likewise for nibl_count and loop. | |
1509 | * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and | |
1510 | idx unsigned. | |
1511 | * z8k-opc.h: Regenerate. | |
1512 | ||
bb82aefe SV |
1513 | 2020-01-07 Shahab Vahedi <shahab@synopsys.com> |
1514 | ||
1515 | * arc-tbl.h (llock): Use 'LLOCK' as class. | |
1516 | (llockd): Likewise. | |
1517 | (scond): Use 'SCOND' as class. | |
1518 | (scondd): Likewise. | |
1519 | (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit. | |
1520 | (scondd): Likewise. | |
1521 | ||
cc6aa1a6 AM |
1522 | 2020-01-06 Alan Modra <amodra@gmail.com> |
1523 | ||
1524 | * m32c-ibld.c: Regenerate. | |
1525 | ||
660e62b1 AM |
1526 | 2020-01-06 Alan Modra <amodra@gmail.com> |
1527 | ||
1528 | PR 25344 | |
1529 | * z80-dis.c (suffix): Don't use a local struct buffer copy. | |
1530 | Peek at next byte to prevent recursion on repeated prefix bytes. | |
1531 | Ensure uninitialised "mybuf" is not accessed. | |
1532 | (print_insn_z80): Don't zero n_fetch and n_used here,.. | |
1533 | (print_insn_z80_buf): ..do it here instead. | |
1534 | ||
c9ae58fe AM |
1535 | 2020-01-04 Alan Modra <amodra@gmail.com> |
1536 | ||
1537 | * m32r-ibld.c: Regenerate. | |
1538 | ||
5f57d4ec AM |
1539 | 2020-01-04 Alan Modra <amodra@gmail.com> |
1540 | ||
1541 | * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value. | |
1542 | ||
2c5c1196 AM |
1543 | 2020-01-04 Alan Modra <amodra@gmail.com> |
1544 | ||
1545 | * crx-dis.c (match_opcode): Avoid shift left of signed value. | |
1546 | ||
2e98c6c5 AM |
1547 | 2020-01-04 Alan Modra <amodra@gmail.com> |
1548 | ||
1549 | * d30v-dis.c (print_insn): Avoid signed overflow in left shift. | |
1550 | ||
567dfba2 JB |
1551 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
1552 | ||
5437a02a JB |
1553 | * aarch64-tbl.h (aarch64_opcode_table): Use |
1554 | SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}. | |
1555 | ||
1556 | 2020-01-03 Jan Beulich <jbeulich@suse.com> | |
1557 | ||
1558 | * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD | |
567dfba2 JB |
1559 | forms of SUDOT and USDOT. |
1560 | ||
8c45011a JB |
1561 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
1562 | ||
5437a02a | 1563 | * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from |
8c45011a JB |
1564 | uzip{1,2}. |
1565 | * opcodes/aarch64-dis-2.c: Re-generate. | |
1566 | ||
f4950f76 JB |
1567 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
1568 | ||
5437a02a | 1569 | * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit |
f4950f76 JB |
1570 | FMMLA encoding. |
1571 | * opcodes/aarch64-dis-2.c: Re-generate. | |
1572 | ||
6655dba2 SB |
1573 | 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com> |
1574 | ||
1575 | * z80-dis.c: Add support for eZ80 and Z80 instructions. | |
1576 | ||
b14ce8bf AM |
1577 | 2020-01-01 Alan Modra <amodra@gmail.com> |
1578 | ||
1579 | Update year range in copyright notice of all files. | |
1580 | ||
0b114740 | 1581 | For older changes see ChangeLog-2019 |
3499769a | 1582 | \f |
0b114740 | 1583 | Copyright (C) 2020 Free Software Foundation, Inc. |
3499769a AM |
1584 | |
1585 | Copying and distribution of this file, with or without modification, | |
1586 | are permitted in any medium without royalty provided the copyright | |
1587 | notice and this notice are preserved. | |
1588 | ||
1589 | Local Variables: | |
1590 | mode: change-log | |
1591 | left-margin: 8 | |
1592 | fill-column: 74 | |
1593 | version-control: never | |
1594 | End: |