PR 360
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
979273e3
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12004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
2
3 * configure.in: Autoupdate to autoconf 2.59.
4 * aclocal.m4: Rebuild with aclocal 1.4p6.
5 * configure: Rebuild with autoconf 2.59.
6 * Makefile.in: Rebuild with automake 1.4p6 (picking up
7 bfd changes for autoconf 2.59 on the way).
8 * config.in: Rebuild with autoheader 2.59.
9
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102004-08-27 Richard Sandiford <rsandifo@redhat.com>
11
12 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
13
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142004-07-30 Michal Ludvig <mludvig@suse.cz>
15
16 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
17 (GRPPADLCK2): New define.
18 (twobyte_has_modrm): True for 0xA6.
19 (grps): GRPPADLCK2 for opcode 0xA6.
20
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AO
212004-07-29 Alexandre Oliva <aoliva@redhat.com>
22
23 Introduce SH2a support.
24 * sh-opc.h (arch_sh2a_base): Renumber.
25 (arch_sh2a_nofpu_base): Remove.
26 (arch_sh_base_mask): Adjust.
27 (arch_opann_mask): New.
28 (arch_sh2a, arch_sh2a_nofpu): Adjust.
29 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
30 (sh_table): Adjust whitespace.
31 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
32 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
33 instruction list throughout.
34 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
35 of arch_sh2a in instruction list throughout.
36 (arch_sh2e_up): Accomodate above changes.
37 (arch_sh2_up): Ditto.
38 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
39 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
40 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
41 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
42 * sh-opc.h (arch_sh2a_nofpu): New.
43 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
44 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
45 instruction.
46 2004-01-20 DJ Delorie <dj@redhat.com>
47 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
48 2003-12-29 DJ Delorie <dj@redhat.com>
49 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
50 sh_opcode_info, sh_table): Add sh2a support.
51 (arch_op32): New, to tag 32-bit opcodes.
52 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
53 2003-12-02 Michael Snyder <msnyder@redhat.com>
54 * sh-opc.h (arch_sh2a): Add.
55 * sh-dis.c (arch_sh2a): Handle.
56 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
57
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582004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
59
60 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
61
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622004-07-22 Nick Clifton <nickc@redhat.com>
63
64 PR/280
65 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
66 insns - this is done by objdump itself.
67 * h8500-dis.c (print_insn_h8500): Likewise.
68
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692004-07-21 Jan Beulich <jbeulich@novell.com>
70
71 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
72 regardless of address size prefix in effect.
73 (ptr_reg): Size or address registers does not depend on rex64, but
74 on the presence of an address size override.
75 (OP_MMX): Use rex.x only for xmm registers.
76 (OP_EM): Use rex.z only for xmm registers.
77
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782004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
79
80 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
81 move/branch operations to the bottom so that VR5400 multimedia
82 instructions take precedence in disassembly.
83
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842004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
85
86 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
87 ISA-specific "break" encoding.
88
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892004-07-13 Elvis Chiang <elvisfb@gmail.com>
90
91 * arm-opc.h: Fix typo in comment.
92
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932004-07-11 Andreas Schwab <schwab@suse.de>
94
95 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
96
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972004-07-09 Andreas Schwab <schwab@suse.de>
98
99 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
100
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1012004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
102
103 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
104 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
105 (crx-dis.lo): New target.
106 (crx-opc.lo): Likewise.
107 * Makefile.in: Regenerate.
108 * configure.in: Handle bfd_crx_arch.
109 * configure: Regenerate.
110 * crx-dis.c: New file.
111 * crx-opc.c: New file.
112 * disassemble.c (ARCH_crx): Define.
113 (disassembler): Handle ARCH_crx.
114
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1152004-06-29 James E Wilson <wilson@specifixinc.com>
116
117 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
118 * ia64-asmtab.c: Regnerate.
119
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1202004-06-28 Alan Modra <amodra@bigpond.net.au>
121
122 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
123 (extract_fxm): Don't test dialect.
124 (XFXFXM_MASK): Include the power4 bit.
125 (XFXM): Add p4 param.
126 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
127
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1282004-06-27 Alexandre Oliva <aoliva@redhat.com>
129
130 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
131 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
132
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1332004-06-26 Alan Modra <amodra@bigpond.net.au>
134
135 * ppc-opc.c (BH, XLBH_MASK): Define.
136 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
137
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1382004-06-24 Alan Modra <amodra@bigpond.net.au>
139
140 * i386-dis.c (x_mode): Comment.
141 (two_source_ops): File scope.
142 (float_mem): Correct fisttpll and fistpll.
143 (float_mem_mode): New table.
144 (dofloat): Use it.
145 (OP_E): Correct intel mode PTR output.
146 (ptr_reg): Use open_char and close_char.
147 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
148 operands. Set two_source_ops.
149
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1502004-06-15 Alan Modra <amodra@bigpond.net.au>
151
152 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
153 instead of _raw_size.
154
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JJ
1552004-06-08 Jakub Jelinek <jakub@redhat.com>
156
157 * ia64-gen.c (in_iclass): Handle more postinc st
158 and ld variants.
159 * ia64-asmtab.c: Rebuilt.
160
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1612004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
162
163 * s390-opc.txt: Correct architecture mask for some opcodes.
164 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
165 in the esa mode as well.
166
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1672004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
168
169 * sh-dis.c (target_arch): Make unsigned.
170 (print_insn_sh): Replace (most of) switch with a call to
171 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
172 * sh-opc.h: Redefine architecture flags values.
173 Add sh3-nommu architecture.
174 Reorganise <arch>_up macros so they make more visual sense.
175 (SH_MERGE_ARCH_SET): Define new macro.
176 (SH_VALID_BASE_ARCH_SET): Likewise.
177 (SH_VALID_MMU_ARCH_SET): Likewise.
178 (SH_VALID_CO_ARCH_SET): Likewise.
179 (SH_VALID_ARCH_SET): Likewise.
180 (SH_MERGE_ARCH_SET_VALID): Likewise.
181 (SH_ARCH_SET_HAS_FPU): Likewise.
182 (SH_ARCH_SET_HAS_DSP): Likewise.
183 (SH_ARCH_UNKNOWN_ARCH): Likewise.
184 (sh_get_arch_from_bfd_mach): Add prototype.
185 (sh_get_arch_up_from_bfd_mach): Likewise.
186 (sh_get_bfd_mach_from_arch_set): Likewise.
187 (sh_merge_bfd_arc): Likewise.
188
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1892004-05-24 Peter Barada <peter@the-baradas.com>
190
191 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
192 into new match_insn_m68k function. Loop over canidate
193 matches and select first that completely matches.
194 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
195 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
196 to verify addressing for MAC/EMAC.
197 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
198 reigster halves since 'fpu' and 'spl' look misleading.
199 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
200 * m68k-opc.c: Rearragne mac/emac cases to use longest for
201 first, tighten up match masks.
202 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
203 'size' from special case code in print_insn_m68k to
204 determine decode size of insns.
205
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AM
2062004-05-19 Alan Modra <amodra@bigpond.net.au>
207
208 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
209 well as when -mpower4.
210
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2112004-05-13 Nick Clifton <nickc@redhat.com>
212
213 * po/fr.po: Updated French translation.
214
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2152004-05-05 Peter Barada <peter@the-baradas.com>
216
217 * m68k-dis.c(print_insn_m68k): Add new chips, use core
218 variants in arch_mask. Only set m68881/68851 for 68k chips.
219 * m68k-op.c: Switch from ColdFire chips to core variants.
220
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2212004-05-05 Alan Modra <amodra@bigpond.net.au>
222
a30e9cc4 223 PR 147.
a404d431
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224 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
225
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2262004-04-29 Ben Elliston <bje@au.ibm.com>
227
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228 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
229 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 230
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2312004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
232
233 * sh-dis.c (print_insn_sh): Print the value in constant pool
234 as a symbol if it looks like a symbol.
235
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2362004-04-22 Peter Barada <peter@the-baradas.com>
237
238 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
239 appropriate ColdFire architectures.
240 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
241 mask addressing.
242 Add EMAC instructions, fix MAC instructions. Remove
243 macmw/macml/msacmw/msacml instructions since mask addressing now
244 supported.
245
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2462004-04-20 Jakub Jelinek <jakub@redhat.com>
247
248 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
249 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
250 suffix. Use fmov*x macros, create all 3 fpsize variants in one
251 macro. Adjust all users.
252
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2532004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
254
255 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
256 separately.
257
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2582004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
259
260 * m32r-asm.c: Regenerate.
261
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2622004-03-29 Stan Shebs <shebs@apple.com>
263
264 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
265 used.
266
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AM
2672004-03-19 Alan Modra <amodra@bigpond.net.au>
268
269 * aclocal.m4: Regenerate.
270 * config.in: Regenerate.
271 * configure: Regenerate.
272 * po/POTFILES.in: Regenerate.
273 * po/opcodes.pot: Regenerate.
274
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AM
2752004-03-16 Alan Modra <amodra@bigpond.net.au>
276
277 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
278 PPC_OPERANDS_GPR_0.
279 * ppc-opc.c (RA0): Define.
280 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
281 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 282 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 283
2dc111b3 2842004-03-15 Aldy Hernandez <aldyh@redhat.com>
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285
286 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 287
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2882004-03-15 Alan Modra <amodra@bigpond.net.au>
289
290 * sparc-dis.c (print_insn_sparc): Update getword prototype.
291
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2922004-03-12 Michal Ludvig <mludvig@suse.cz>
293
294 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 295 (grps): Delete GRPPLOCK entry.
7ffdda93 296
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2972004-03-12 Alan Modra <amodra@bigpond.net.au>
298
299 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
300 (M, Mp): Use OP_M.
301 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
302 (GRPPADLCK): Define.
303 (dis386): Use NOP_Fixup on "nop".
304 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
305 (twobyte_has_modrm): Set for 0xa7.
306 (padlock_table): Delete. Move to..
307 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
308 and clflush.
309 (print_insn): Revert PADLOCK_SPECIAL code.
310 (OP_E): Delete sfence, lfence, mfence checks.
311
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JJ
3122004-03-12 Jakub Jelinek <jakub@redhat.com>
313
314 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
315 (INVLPG_Fixup): New function.
316 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
317
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ML
3182004-03-12 Michal Ludvig <mludvig@suse.cz>
319
320 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
321 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
322 (padlock_table): New struct with PadLock instructions.
323 (print_insn): Handle PADLOCK_SPECIAL.
324
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3252004-03-12 Alan Modra <amodra@bigpond.net.au>
326
327 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
328 (OP_E): Twiddle clflush to sfence here.
329
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3302004-03-08 Nick Clifton <nickc@redhat.com>
331
332 * po/de.po: Updated German translation.
333
ae51a426
JR
3342003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
335
336 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
337 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
338 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
339 accordingly.
340
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3412004-03-01 Richard Sandiford <rsandifo@redhat.com>
342
343 * frv-asm.c: Regenerate.
344 * frv-desc.c: Regenerate.
345 * frv-desc.h: Regenerate.
346 * frv-dis.c: Regenerate.
347 * frv-ibld.c: Regenerate.
348 * frv-opc.c: Regenerate.
349 * frv-opc.h: Regenerate.
350
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3512004-03-01 Richard Sandiford <rsandifo@redhat.com>
352
353 * frv-desc.c, frv-opc.c: Regenerate.
354
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3552004-03-01 Richard Sandiford <rsandifo@redhat.com>
356
357 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
358
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JR
3592004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
360
361 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
362 Also correct mistake in the comment.
363
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JR
3642004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
365
366 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
367 ensure that double registers have even numbers.
368 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
369 that reserved instruction 0xfffd does not decode the same
370 as 0xfdfd (ftrv).
371 * sh-opc.h: Add REG_N_D nibble type and use it whereever
372 REG_N refers to a double register.
373 Add REG_N_B01 nibble type and use it instead of REG_NM
374 in ftrv.
375 Adjust the bit patterns in a few comments.
376
e5d2b64f 3772004-02-25 Aldy Hernandez <aldyh@redhat.com>
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378
379 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 380
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3812004-02-20 Aldy Hernandez <aldyh@redhat.com>
382
383 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
384
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AH
3852004-02-20 Aldy Hernandez <aldyh@redhat.com>
386
387 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
388
f0b26da6 3892004-02-20 Aldy Hernandez <aldyh@redhat.com>
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390
391 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
392 mtivor32, mtivor33, mtivor34.
f0b26da6 393
23d59c56 3942004-02-19 Aldy Hernandez <aldyh@redhat.com>
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395
396 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 397
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3982004-02-10 Petko Manolov <petkan@nucleusys.com>
399
400 * arm-opc.h Maverick accumulator register opcode fixes.
401
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4022004-02-13 Ben Elliston <bje@wasabisystems.com>
403
404 * m32r-dis.c: Regenerate.
405
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4062004-01-27 Michael Snyder <msnyder@redhat.com>
407
408 * sh-opc.h (sh_table): "fsrra", not "fssra".
409
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4102004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
411
412 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
413 contraints.
414
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4152004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
416
417 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
418
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4192004-01-19 Alan Modra <amodra@bigpond.net.au>
420
421 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
422 1. Don't print scale factor on AT&T mode when index missing.
423
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AO
4242004-01-16 Alexandre Oliva <aoliva@redhat.com>
425
426 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
427 when loaded into XR registers.
428
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RS
4292004-01-14 Richard Sandiford <rsandifo@redhat.com>
430
431 * frv-desc.h: Regenerate.
432 * frv-desc.c: Regenerate.
433 * frv-opc.c: Regenerate.
434
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4352004-01-13 Michael Snyder <msnyder@redhat.com>
436
437 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
438
e45d0630
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4392004-01-09 Paul Brook <paul@codesourcery.com>
440
441 * arm-opc.h (arm_opcodes): Move generic mcrr after known
442 specific opcodes.
443
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DJ
4442004-01-07 Daniel Jacobowitz <drow@mvista.com>
445
446 * Makefile.am (libopcodes_la_DEPENDENCIES)
447 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
448 comment about the problem.
449 * Makefile.in: Regenerate.
450
ba2d3f07
AO
4512004-01-06 Alexandre Oliva <aoliva@redhat.com>
452
453 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
454 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
455 cut&paste errors in shifting/truncating numerical operands.
456 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
457 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
458 (parse_uslo16): Likewise.
459 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
460 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
461 (parse_s12): Likewise.
462 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
463 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
464 (parse_uslo16): Likewise.
465 (parse_uhi16): Parse gothi and gotfuncdeschi.
466 (parse_d12): Parse got12 and gotfuncdesc12.
467 (parse_s12): Likewise.
468
3ab48931
NC
4692004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
470
471 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
472 instruction which looks similar to an 'rla' instruction.
a0bd404e 473
c9e214e5 474For older changes see ChangeLog-0203
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475\f
476Local Variables:
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477mode: change-log
478left-margin: 8
479fill-column: 74
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480version-control: never
481End:
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