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* lib/mi-support.exp (mi_gdb_test): Expect different formats
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
b83a9376
CM		 12013-11-11 Catherine Moore <clm@codesourcery.com>
2
3 * mips-dis.c (print_insn_mips): Use
4 INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
5 (print_insn_micromips): Likewise.
6 * mips-opc.c (LDD): Remove.
7 (CLD): Include INSN_LOAD_MEMORY.
8 (LM): New.
9 (mips_builtin_opcodes): Use LM instead of LDD.
10 Add LM to load instructions.
11
d56da83e
L		 122013-11-08 H.J. Lu <hongjiu.lu@intel.com>
13
14 PR gas/16140
15 * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
16 * i386-init.h: Regenerated.
17
49eec193
YZ		 182013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
19
20 * aarch64-opc.c (F_DEPRECATED): New macro.
21 (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
22 F_DEPRECATED.
23 (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
24 AARCH64_OPND_SYSREG.
25
68a64283
YZ		 262013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
27
28 * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
29 (convert_from_csel): Likewise.
30 * aarch64-opc.c (operand_general_constraint_met_p): Handle
31 AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
32 (aarch64_print_operand): Handle AARCH64_OPND_COND1.
33 * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
34 COND for cinc, cset, cinv, csetm and cneg.
35 (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
36 * aarch64-asm-2.c: Re-generated.
37 * aarch64-dis-2.c: Ditto.
38 * aarch64-opc-2.c: Ditto.
39
4e50d5f8
YZ		 402013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
41
42 * aarch64-opc.c (set_syntax_error): New function.
43 (operand_general_constraint_met_p): Replace set_other_error
44 with set_syntax_error.
45
7d4a7d10
AA		 462013-10-30 Andreas Arnez <arnez@linux.vnet.ibm.com>
47
48 * s390-dis.c (init_disasm): Default to full 'zarch' opcode
49 availability even for 31-bit programs.
50
85181173
RR		 512013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
52
53 * arm-dis.c (neon_opcodes): Adjust print string for vshll.
54
4edbb8e3
CF		 552013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
56
57 * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
58 +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
59 +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
60 (MSA): New define.
61 (MSA64): New define.
62 (micromips_opcodes): Add MSA instructions.
63 * mips-dis.c (msa_control_names): New array.
64 (mips_abi_choice): Add ASE_MSA to mips32r2.
65 Remove ASE_MDMX from mips64r2.
66 Add ASE_MSA and ASE_MSA64 to mips64r2.
67 (parse_mips_dis_option): Handle -Mmsa.
68 (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
69 (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
70 (print_mips_disassembler_options): Print -Mmsa.
71 * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
72 +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
73 (MSA): New define.
74 (MSA64): New define.
75 (mips_builtin_op): Add MSA instructions.
76
ae335a4e
SL		 772013-10-13 Sandra Loosemore <sandra@codesourcery.com>
78
79 * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
80 as the primary name of r30.
81
6c75cc62
L		 822013-10-12 Jan Beulich <jbeulich@suse.com>
83
84 * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
85 default case.
86 (OP_E_register): Move v_bnd_mode alongside m_mode.
87 * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
88 Drop Reg16 and Disp16. Add NoRex64.
89 (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
90 * i386-tbl.h: Re-generate.
91
0e1c2434
SK		 922013-10-10 Sean Keys <skeys@ipdatasys.com>
93
94 * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
95 table.
96 * xgate-dis.c (print_insn): Refactor to work with table change.
97
7903e530
RM		 982013-10-10 Roland McGrath <mcgrathr@google.com>
99
9ce09ba2
RM		 100 * i386-dis.c (oappend_maybe_intel): New function.
101 (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
102 (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
103 (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
104
2b4e983c
RM		 105 * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
106 possible compiler warnings when the union's initializer is
107 actually meant for the 'preg' enum typed member.
108 * crx-opc.c (REG): Likewise.
109
7903e530
RM		 110 * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
111 Remove duplicate const qualifier.
112
79e0e31d
JB		 1132013-10-08 Jan Beulich <jbeulich@suse.com>
114
115 * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
116 (clflush): Use Anysize instead of Byte|Unspecified.
117 (prefetch*): Likewise.
118 * i386-tbl.h: Re-generate.
119
45099dfa
CF		 1202013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
121
122 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
123
916fae91
L		 1242013-09-30 H.J. Lu <hongjiu.lu@intel.com>
125
126 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
127 * i386-init.h: Regenerated.
128
c7b0bd56
SE		 1292013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
130
131 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
132 * i386-init.h: Regenerated.
133
cc9afea3
AM		 1342013-09-20 Alan Modra <amodra@gmail.com>
135
136 * configure: Regenerate.
137
e3f9e852
RS		 1382013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
139
140 * s390-opc.txt (clih): Make the immediate unsigned.
141
74db7efb
NC		 1422013-09-04 Roland McGrath <mcgrathr@google.com>
143
144 PR gas/15914
145 * arm-dis.c (arm_opcodes): Add udf.
146 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
147 (thumb32_opcodes): Add udf.w.
148 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
149
c8094e01
AK		 1502013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
151
152 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
153 For the load fp integer instructions only the suppression flag was
154 new with z196 version.
155
7e105031
NC		 1562013-08-28 Nick Clifton <nickc@redhat.com>
157
158 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
159 immediate is not suitable for the 32-bit ABI.
160
fb6f3895
MR		 1612013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
162
163 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
164 replacing NODS.
165
9aff4b7a
NC		 1662013-08-23 Yuri Chornoivan <yurchor@ukr.net>
167
168 PR binutils/15834
169 * aarch64-asm.c: Fix typos.
170 * aarch64-dis.c: Likewise.
171 * msp430-dis.c: Likewise.
172
5e0dc5ba
RS		 1732013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
174
175 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
176 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
177 Use +H rather than +C for the real "dext".
178 * mips-opc.c (mips_builtin_opcodes): Likewise.
179
0f35dbc4
RS		 1802013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
181
182 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
183 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
184 and OPTIONAL_MAPPED_REG.
185 * mips-opc.c (decode_mips_operand): Likewise.
186 * mips16-opc.c (decode_mips16_operand): Likewise.
187 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
188
79ceb7cb
L		 1892013-08-19 H.J. Lu <hongjiu.lu@intel.com>
190
191 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
192 (PREFIX_EVEX_0F3A3F): Likewise.
193 * i386-dis-evex.h (evex_table): Updated.
194
ee5734f0
RS		 1952013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
196
197 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
198 VCLIPW.
199
d6787ef9
EB		 2002013-08-05 Eric Botcazou <ebotcazou@adacore.com>
201 Konrad Eisele <konrad@gaisler.com>
202
203 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
204 bfd_mach_sparc.
205 * sparc-opc.c (MASK_LEON): Define.
206 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
207 (letandleon): New macro.
208 (v9andleon): Likewise.
209 (sparc_opc): Add leon.
210 (umac): Enable for letandleon.
211 (smac): Likewise.
212 (casa): Enable for v9andleon.
213 (cas): Likewise.
214 (casl): Likewise.
215
14daeee3
RS		 2162013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
217 Richard Sandiford <rdsandiford@googlemail.com>
218
219 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
220 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
221 (print_vu0_channel): New function.
222 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
223 (print_insn_args): Handle '#'.
224 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
225 * mips-opc.c (mips_vu0_channel_mask): New constant.
226 (decode_mips_operand): Handle new VU0 operand types.
227 (VU0, VU0CH): New macros.
228 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
229 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
230 Use "+6" rather than "G" for QMFC2 and QMTC2.
231
3ccad066
RS		 2322013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
233
234 * mips-formats.h (PCREL): Reorder parameters and update the definition
235 to match new mips_pcrel_operand layout.
236 (JUMP, JALX, BRANCH): Update accordingly.
237 * mips16-opc.c (decode_mips16_operand): Likewise.
238
df34fbcc
RS		 2392013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
240
241 * micromips-opc.c (WR_s): Delete.
242
fc76e730
RS		 2432013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
244
245 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
246 New macros.
247 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
248 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
249 (mips_builtin_opcodes): Use the new position-based read-write flags
250 instead of field-based ones. Use UDI for "udi..." instructions.
251 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
252 New macros.
253 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
254 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
255 (WR_SP, RD_16): New macros.
256 (RD_SP): Redefine as an INSN2_* flag.
257 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
258 (mips16_opcodes): Use the new position-based read-write flags
259 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
260 pinfo2 field.
261 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
262 New macros.
263 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
264 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
265 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
266 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
267 (micromips_opcodes): Use the new position-based read-write flags
268 instead of field-based ones.
269 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
270 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
271 of field-based flags.
272
26545944
RS		 2732013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
274
275 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
276 (WR_SP): Replace with...
277 (MOD_SP): ...this.
278 (mips16_opcodes): Update accordingly.
279 * mips-dis.c (print_insn_mips16): Likewise.
280
a8d92fc6
RS		 2812013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
282
283 * mips16-opc.c (mips16_opcodes): Reformat.
284
6a819047
RS		 2852013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
286
287 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
288 for operands that are hard-coded to $0.
289 * micromips-opc.c (micromips_opcodes): Likewise.
290
344c74a6
RS		 2912013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
292
293 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
294 for the single-operand forms of JALR and JALR.HB.
295 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
296 and JALRS.HB.
297
41989114
RS		 2982013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
299
300 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
301 instructions. Fix them to use WR_MACC instead of WR_CC and
302 add missing RD_MACCs.
303
6d075bce
RS		 3042013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
305
306 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
307
4f6ffcd3
PB		 3082013-07-29 Peter Bergner <bergner@vnet.ibm.com>
309
310 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
311
43234a1e
L		 3122013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
313 Alexander Ivchenko <alexander.ivchenko@intel.com>
314 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
315 Sergey Lega <sergey.s.lega@intel.com>
316 Anna Tikhonova <anna.tikhonova@intel.com>
317 Ilya Tocar <ilya.tocar@intel.com>
318 Andrey Turetskiy <andrey.turetskiy@intel.com>
319 Ilya Verbin <ilya.verbin@intel.com>
320 Kirill Yukhin <kirill.yukhin@intel.com>
321 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
322
323 * i386-dis-evex.h: New.
324 * i386-dis.c (OP_Rounding): New.
325 (VPCMP_Fixup): New.
326 (OP_Mask): New.
327 (Rdq): New.
328 (XMxmmq): New.
329 (EXdScalarS): New.
330 (EXymm): New.
331 (EXEvexHalfBcstXmmq): New.
332 (EXxmm_mdq): New.
333 (EXEvexXGscat): New.
334 (EXEvexXNoBcst): New.
335 (VPCMP): New.
336 (EXxEVexR): New.
337 (EXxEVexS): New.
338 (XMask): New.
339 (MaskG): New.
340 (MaskE): New.
341 (MaskR): New.
342 (MaskVex): New.
343 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
344 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
345 evex_rounding_mode, evex_sae_mode, mask_mode.
346 (USE_EVEX_TABLE): New.
347 (EVEX_TABLE): New.
348 (EVEX enum): New.
349 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
350 REG_EVEX_0F38C7.
351 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
352 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
353 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
354 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
355 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
356 MOD_EVEX_0F38C7_REG_6.
357 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
358 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
359 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
360 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
361 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
362 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
363 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
364 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
365 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
366 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
367 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
368 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
369 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
370 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
371 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
372 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
373 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
374 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
375 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
376 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
377 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
378 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
379 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
380 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
381 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
382 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
383 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
384 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
385 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
386 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
387 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
388 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
389 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
390 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
391 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
392 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
393 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
394 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
395 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
396 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
397 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
398 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
399 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
400 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
401 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
402 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
403 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
404 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
405 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
406 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
407 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
408 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
409 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
410 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
411 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
412 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
413 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
414 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
415 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
416 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
417 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
418 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
419 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
420 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
421 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
422 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
423 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
424 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
425 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
426 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
427 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
428 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
429 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
430 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
431 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
432 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
433 PREFIX_EVEX_0F3A55.
434 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
435 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
436 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
437 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
438 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
439 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
440 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
441 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
442 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
443 VEX_W_0F3A32_P_2_LEN_0.
444 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
445 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
446 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
447 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
448 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
449 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
450 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
451 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
452 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
453 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
454 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
455 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
456 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
457 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
458 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
459 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
460 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
461 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
462 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
463 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
464 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
465 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
466 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
467 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
468 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
469 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
470 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
471 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
472 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
473 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
474 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
475 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
476 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
477 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
478 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
479 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
480 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
481 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
482 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
483 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
484 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
485 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
486 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
487 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
488 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
489 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
490 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
491 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
492 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
493 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
494 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
495 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
496 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
497 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
498 (struct vex): Add fields evex, r, v, mask_register_specifier,
499 zeroing, ll, b.
500 (intel_names_xmm): Add upper 16 registers.
501 (att_names_xmm): Ditto.
502 (intel_names_ymm): Ditto.
503 (att_names_ymm): Ditto.
504 (names_zmm): New.
505 (intel_names_zmm): Ditto.
506 (att_names_zmm): Ditto.
507 (names_mask): Ditto.
508 (intel_names_mask): Ditto.
509 (att_names_mask): Ditto.
510 (names_rounding): Ditto.
511 (names_broadcast): Ditto.
512 (x86_64_table): Add escape to evex-table.
513 (reg_table): Include reg_table evex-entries from
514 i386-dis-evex.h. Fix prefetchwt1 instruction.
515 (prefix_table): Add entries for new instructions.
516 (vex_table): Ditto.
517 (vex_len_table): Ditto.
518 (vex_w_table): Ditto.
519 (mod_table): Ditto.
520 (get_valid_dis386): Properly handle new instructions.
521 (print_insn): Handle zmm and mask registers, print mask operand.
522 (intel_operand_size): Support EVEX, new modes and sizes.
523 (OP_E_register): Handle new modes.
524 (OP_E_memory): Ditto.
525 (OP_G): Ditto.
526 (OP_XMM): Ditto.
527 (OP_EX): Ditto.
528 (OP_VEX): Ditto.
529 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
530 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
531 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
532 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
533 CpuAVX512PF and CpuVREX.
534 (operand_type_init): Add OPERAND_TYPE_REGZMM,
535 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
536 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
537 StaticRounding, SAE, Disp8MemShift, NoDefMask.
538 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
539 * i386-init.h: Regenerate.
540 * i386-opc.h (CpuAVX512F): New.
541 (CpuAVX512CD): New.
542 (CpuAVX512ER): New.
543 (CpuAVX512PF): New.
544 (CpuVREX): New.
545 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
546 cpuavx512pf and cpuvrex fields.
547 (VecSIB): Add VecSIB512.
548 (EVex): New.
549 (Masking): New.
550 (VecESize): New.
551 (Broadcast): New.
552 (StaticRounding): New.
553 (SAE): New.
554 (Disp8MemShift): New.
555 (NoDefMask): New.
556 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
557 staticrounding, sae, disp8memshift and nodefmask.
558 (RegZMM): New.
559 (Zmmword): Ditto.
560 (Vec_Disp8): Ditto.
561 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
562 fields.
563 (RegVRex): New.
564 * i386-opc.tbl: Add AVX512 instructions.
565 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
566 registers, mask registers.
567 * i386-tbl.h: Regenerate.
568
1d2db237
RS		 5692013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
570
571 PR gas/15220
572 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
573 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
574
a0046408
L		 5752013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
576
577 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
578 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
579 PREFIX_0F3ACC.
580 (prefix_table): Updated.
581 (three_byte_table): Likewise.
582 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
583 (cpu_flags): Add CpuSHA.
584 (i386_cpu_flags): Add cpusha.
585 * i386-init.h: Regenerate.
586 * i386-opc.h (CpuSHA): New.
587 (CpuUnused): Restored.
588 (i386_cpu_flags): Add cpusha.
589 * i386-opc.tbl: Add SHA instructions.
590 * i386-tbl.h: Regenerate.
591
7e8b059b
L		 5922013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
593 Kirill Yukhin <kirill.yukhin@intel.com>
594 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
595
596 * i386-dis.c (BND_Fixup): New.
597 (Ebnd): New.
598 (Ev_bnd): New.
599 (Gbnd): New.
600 (BND): New.
601 (v_bnd_mode): New.
602 (bnd_mode): New.
c623f86c
L		 603 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
604 MOD_0F1B_PREFIX_1.
605 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 606 (dis tables): Replace XX with BND for near branch and call
607 instructions.
608 (prefix_table): Add new entries.
609 (mod_table): Likewise.
610 (names_bnd): New.
611 (intel_names_bnd): New.
612 (att_names_bnd): New.
613 (BND_PREFIX): New.
614 (prefix_name): Handle BND_PREFIX.
615 (print_insn): Initialize names_bnd.
616 (intel_operand_size): Handle new modes.
617 (OP_E_register): Likewise.
618 (OP_E_memory): Likewise.
619 (OP_G): Likewise.
620 * i386-gen.c (cpu_flag_init): Add CpuMPX.
621 (cpu_flags): Add CpuMPX.
622 (operand_type_init): Add RegBND.
623 (opcode_modifiers): Add BNDPrefixOk.
624 (operand_types): Add RegBND.
625 * i386-init.h: Regenerate.
626 * i386-opc.h (CpuMPX): New.
627 (CpuUnused): Comment out.
628 (i386_cpu_flags): Add cpumpx.
629 (BNDPrefixOk): New.
630 (i386_opcode_modifier): Add bndprefixok.
631 (RegBND): New.
632 (i386_operand_type): Add regbnd.
633 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
634 Add MPX instructions and bnd prefix.
635 * i386-reg.tbl: Add bnd0-bnd3 registers.
636 * i386-tbl.h: Regenerate.
637
b56e23fb
RS		 6382013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
639
640 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
641 ATTRIBUTE_UNUSED.
642
e7ae278d
RS		 6432013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
644
645 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
646 special rules.
647 * Makefile.in: Regenerate.
648 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
649 all fields. Reformat.
650
c3c07478
RS		 6512013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
652
653 * mips16-opc.c: Include mips-formats.h.
654 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
655 static arrays.
656 (decode_mips16_operand): New function.
657 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
658 (print_insn_arg): Handle OP_ENTRY_EXIT list.
659 Abort for OP_SAVE_RESTORE_LIST.
660 (print_mips16_insn_arg): Change interface. Use mips_operand
661 structures. Delete GET_OP_S. Move GET_OP definition to...
662 (print_insn_mips16): ...here. Call init_print_arg_state.
663 Update the call to print_mips16_insn_arg.
664
ab902481
RS		 6652013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
666
667 * mips-formats.h: New file.
668 * mips-opc.c: Include mips-formats.h.
669 (reg_0_map): New static array.
670 (decode_mips_operand): New function.
671 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
672 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
673 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
674 (int_c_map): New static arrays.
675 (decode_micromips_operand): New function.
676 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
677 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
678 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
679 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
680 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
681 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
682 (micromips_imm_b_map, micromips_imm_c_map): Delete.
683 (print_reg): New function.
684 (mips_print_arg_state): New structure.
685 (init_print_arg_state, print_insn_arg): New functions.
686 (print_insn_args): Change interface and use mips_operand structures.
687 Delete GET_OP_S. Move GET_OP definition to...
688 (print_insn_mips): ...here. Update the call to print_insn_args.
689 (print_insn_micromips): Use print_insn_args.
690
cc537e56
RS		 6912013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
692
693 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
694 in macros.
695
7a5f87ce
RS		 6962013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
697
698 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
699 ADDA.S, MULA.S and SUBA.S.
700
41741fa4
L		 7012013-07-08 H.J. Lu <hongjiu.lu@intel.com>
702
703 PR gas/13572
704 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
705 * i386-tbl.h: Regenerated.
706
f2ae14a1
RS		 7072013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
708
709 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
710 and SD A(B) macros up.
711 * micromips-opc.c (micromips_opcodes): Likewise.
712
04c9d415
RS		 7132013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
714
715 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
716 instructions.
717
5c324c16
RS		 7182013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
719
720 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
721 MDMX-like instructions.
722 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
723 printing "Q" operands for INSN_5400 instructions.
724
23e69e47
RS		 7252013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
726
727 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
728 "+S" for "cins".
729 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
730 Combine cases.
731
27c5c572
RS		 7322013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
733
734 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
735 "jalx".
736 * mips16-opc.c (mips16_opcodes): Likewise.
737 * micromips-opc.c (micromips_opcodes): Likewise.
738 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
739 (print_insn_mips16): Handle "+i".
740 (print_insn_micromips): Likewise. Conditionally preserve the
741 ISA bit for "a" but not for "+i".
742
e76ff5ab
RS		 7432013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
744
745 * micromips-opc.c (WR_mhi): Rename to..
746 (WR_mh): ...this.
747 (micromips_opcodes): Update "movep" entry accordingly. Replace
748 "mh,mi" with "mh".
749 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
750 (micromips_to_32_reg_h_map1): ...this.
751 (micromips_to_32_reg_i_map): Rename to...
752 (micromips_to_32_reg_h_map2): ...this.
753 (print_micromips_insn): Remove "mi" case. Print both registers
754 in the pair for "mh".
755
fa7616a4
RS		 7562013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
757
758 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
759 * micromips-opc.c (micromips_opcodes): Likewise.
760 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
761 and "+T" handling. Check for a "0" suffix when deciding whether to
762 use coprocessor 0 names. In that case, also check for ",H" selectors.
763
fb798c50
AK		 7642013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
765
766 * s390-opc.c (J12_12, J24_24): New macros.
767 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
768 (MASK_MII_UPI): Rename to MASK_MII_UPP.
769 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
770
58ae08f2
AM		 7712013-07-04 Alan Modra <amodra@gmail.com>
772
773 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
774
b5e04c2b
NC		 7752013-06-26 Nick Clifton <nickc@redhat.com>
776
777 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
778 field when checking for type 2 nop.
779 * rx-decode.c: Regenerate.
780
833794fc
MR		 7812013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
782
783 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
784 and "movep" macros.
785
1bbce132
MR		 7862013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
787
788 * mips-dis.c (is_mips16_plt_tail): New function.
789 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
790 word.
791 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
792
34c911a4
NC		 7932013-06-21 DJ Delorie <dj@redhat.com>
794
795 * msp430-decode.opc: New.
796 * msp430-decode.c: New/generated.
797 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
798 (MAINTAINER_CLEANFILES): Likewise.
799 Add rule to build msp430-decode.c frommsp430decode.opc
800 using the opc2c program.
801 * Makefile.in: Regenerate.
802 * configure.in: Add msp430-decode.lo to msp430 architecture files.
803 * configure: Regenerate.
804
b9eead84
YZ		 8052013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
806
807 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
808 (SYMTAB_AVAILABLE): Removed.
809 (#include "elf/aarch64.h): Ditto.
810
7f3c4072
CM		 8112013-06-17 Catherine Moore <clm@codesourcery.com>
812 Maciej W. Rozycki <macro@codesourcery.com>
813 Chao-Ying Fu <fu@mips.com>
814
815 * micromips-opc.c (EVA): Define.
816 (TLBINV): Define.
817 (micromips_opcodes): Add EVA opcodes.
818 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
819 (print_insn_args): Handle EVA offsets.
820 (print_insn_micromips): Likewise.
821 * mips-opc.c (EVA): Define.
822 (TLBINV): Define.
823 (mips_builtin_opcodes): Add EVA opcodes.
824
de40ceb6
AM		 8252013-06-17 Alan Modra <amodra@gmail.com>
826
827 * Makefile.am (mips-opc.lo): Add rules to create automatic
828 dependency files. Pass archdefs.
829 (micromips-opc.lo, mips16-opc.lo): Likewise.
830 * Makefile.in: Regenerate.
831
3531d549
DD		 8322013-06-14 DJ Delorie <dj@redhat.com>
833
834 * rx-decode.opc (rx_decode_opcode): Bit operations on
835 registers are 32-bit operations, not 8-bit operations.
836 * rx-decode.c: Regenerate.
837
ba92f7fb
CF		 8382013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
839
840 * micromips-opc.c (IVIRT): New define.
841 (IVIRT64): New define.
842 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
843 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
844
845 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
846 dmtgc0 to print cp0 names.
847
9daf7bab
SL		 8482013-06-09 Sandra Loosemore <sandra@codesourcery.com>
849
850 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
851 argument.
852
d301a56b
RS		 8532013-06-08 Catherine Moore <clm@codesourcery.com>
854 Richard Sandiford <rdsandiford@googlemail.com>
855
856 * micromips-opc.c (D32, D33, MC): Update definitions.
857 (micromips_opcodes): Initialize ase field.
858 * mips-dis.c (mips_arch_choice): Add ase field.
859 (mips_arch_choices): Initialize ase field.
860 (set_default_mips_dis_options): Declare and setup mips_ase.
861 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
862 MT32, MC): Update definitions.
863 (mips_builtin_opcodes): Initialize ase field.
864
a3dcb6c5
RS		 8652013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
866
867 * s390-opc.txt (flogr): Require a register pair destination.
868
6cf1d90c
AK		 8692013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
870
871 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
872 instruction format.
873
c77c0862
RS		 8742013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
875
876 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
877
c0637f3a
PB		 8782013-05-20 Peter Bergner <bergner@vnet.ibm.com>
879
880 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
881 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
882 XLS_MASK, PPCVSX2): New defines.
883 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
884 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
885 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
886 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
887 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
888 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
889 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
890 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
891 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
892 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
893 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
894 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
895 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
896 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
897 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
898 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
899 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
900 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
901 <lxvx, stxvx>: New extended mnemonics.
902
4934fdaf
AM		 9032013-05-17 Alan Modra <amodra@gmail.com>
904
905 * ia64-raw.tbl: Replace non-ASCII char.
906 * ia64-waw.tbl: Likewise.
907 * ia64-asmtab.c: Regenerate.
908
6091d651
SE		 9092013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
910
911 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
912 * i386-init.h: Regenerated.
913
d2865ed3
YZ		 9142013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
915
916 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
917 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
918 check from [0, 255] to [-128, 255].
919
b015e599
AP		 9202013-05-09 Andrew Pinski <apinski@cavium.com>
921
922 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
923 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
924 (parse_mips_dis_option): Handle the virt option.
925 (print_insn_args): Handle "+J".
926 (print_mips_disassembler_options): Print out message about virt64.
927 * mips-opc.c (IVIRT): New define.
928 (IVIRT64): New define.
929 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
930 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
931 Move rfe to the bottom as it conflicts with tlbgp.
932
9f0682fe
AM		 9332013-05-09 Alan Modra <amodra@gmail.com>
934
935 * ppc-opc.c (extract_vlesi): Properly sign extend.
936 (extract_vlensi): Likewise. Comment reason for setting invalid.
937
13761a11
NC		 9382013-05-02 Nick Clifton <nickc@redhat.com>
939
940 * msp430-dis.c: Add support for MSP430X instructions.
941
e3031850
SL		 9422013-04-24 Sandra Loosemore <sandra@codesourcery.com>
943
944 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
945 to "eccinj".
946
17310e56
NC		 9472013-04-17 Wei-chen Wang <cole945@gmail.com>
948
949 PR binutils/15369
950 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
951 of CGEN_CPU_ENDIAN.
952 (hash_insns_list): Likewise.
953
731df338
JK		 9542013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
955
956 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
957 warning workaround.
958
5f77db52
JB		 9592013-04-08 Jan Beulich <jbeulich@suse.com>
960
961 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
962 * i386-tbl.h: Re-generate.
963
0afd1215
DM		 9642013-04-06 David S. Miller <davem@davemloft.net>
965
966 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
967 of an opcode, prefer the one with F_PREFERRED set.
968 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
969 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
970 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
971 mark existing mnenomics as aliases. Add "cc" suffix to edge
972 instructions generating condition codes, mark existing mnenomics
973 as aliases. Add "fp" prefix to VIS compare instructions, mark
974 existing mnenomics as aliases.
975
41702d50
NC		 9762013-04-03 Nick Clifton <nickc@redhat.com>
977
978 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
979 destination address by subtracting the operand from the current
980 address.
981 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
982 a positive value in the insn.
983 (extract_u16_loop): Do not negate the returned value.
984 (D16_LOOP): Add V850_INVERSE_PCREL flag.
985
986 (ceilf.sw): Remove duplicate entry.
987 (cvtf.hs): New entry.
988 (cvtf.sh): Likewise.
989 (fmaf.s): Likewise.
990 (fmsf.s): Likewise.
991 (fnmaf.s): Likewise.
992 (fnmsf.s): Likewise.
993 (maddf.s): Restrict to E3V5 architectures.
994 (msubf.s): Likewise.
995 (nmaddf.s): Likewise.
996 (nmsubf.s): Likewise.
997
55cf16e1
L		 9982013-03-27 H.J. Lu <hongjiu.lu@intel.com>
999
1000 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
1001 check address mode.
1002 (print_insn): Pass sizeflag to get_sib.
1003
51dcdd4d
NC		 10042013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
1005
1006 PR binutils/15068
1007 * tic6x-dis.c: Add support for displaying 16-bit insns.
1008
795b8e6b
NC		 10092013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
1010
1011 PR gas/15095
1012 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1013 individual msb and lsb halves in src1 & src2 fields. Discard the
1014 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1015 follow what Ti SDK does in that case as any value in the src1
1016 field yields the same output with SDK disassembler.
1017
314d60dd
ME		 10182013-03-12 Michael Eager <eager@eagercon.com>
1019
795b8e6b 1020 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 1021
dad60f8e
SL		 10222013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1023
1024 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1025
f5cb796a
SL		 10262013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1027
1028 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1029
21fde85c
SL		 10302013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1031
1032 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1033
dd5181d5
KT		 10342013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1035
1036 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1037 (thumb32_opcodes): Likewise.
1038 (print_insn_thumb32): Handle 'S' control char.
1039
87a8d6cb
NC		 10402013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
1041
1042 * lm32-desc.c: Regenerate.
1043
99dce992
L		 10442013-03-01 H.J. Lu <hongjiu.lu@intel.com>
1045
1046 * i386-reg.tbl (riz): Add RegRex64.
1047 * i386-tbl.h: Regenerated.
1048
e60bb1dd
YZ		 10492013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1050
1051 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1052 (aarch64_feature_crc): New static.
1053 (CRC): New macro.
1054 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1055 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1056 * aarch64-asm-2.c: Re-generate.
1057 * aarch64-dis-2.c: Ditto.
1058 * aarch64-opc-2.c: Ditto.
1059
c7570fcd
AM		 10602013-02-27 Alan Modra <amodra@gmail.com>
1061
1062 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1063 * rl78-decode.c: Regenerate.
1064
151fa98f
NC		 10652013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1066
1067 * rl78-decode.opc: Fix encoding of DIVWU insn.
1068 * rl78-decode.c: Regenerate.
1069
5c111e37
L		 10702013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1071
1072 PR gas/15159
1073 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1074
1075 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1076 (cpu_flags): Add CpuSMAP.
1077
1078 * i386-opc.h (CpuSMAP): New.
1079 (i386_cpu_flags): Add cpusmap.
1080
1081 * i386-opc.tbl: Add clac and stac.
1082
1083 * i386-init.h: Regenerated.
1084 * i386-tbl.h: Likewise.
1085
9d1df426
NC		 10862013-02-15 Markos Chandras <markos.chandras@imgtec.com>
1087
1088 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1089 which also makes the disassembler output be in little
1090 endian like it should be.
1091
a1ccaec9
YZ		 10922013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1093
1094 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1095 fields to NULL.
1096 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1097
ef068ef4 10982013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 1099
1100 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1101 section disassembled.
1102
6fe6ded9
RE		 11032013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1104
1105 * arm-dis.c: Update strht pattern.
1106
0aa27725
RS		 11072013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1108
1109 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1110 single-float. Disable ll, lld, sc and scd for EE. Disable the
1111 trunc.w.s macro for EE.
1112
36591ba1
SL		 11132013-02-06 Sandra Loosemore <sandra@codesourcery.com>
1114 Andrew Jenner <andrew@codesourcery.com>
1115
1116 Based on patches from Altera Corporation.
1117
1118 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1119 nios2-opc.c.
1120 * Makefile.in: Regenerated.
1121 * configure.in: Add case for bfd_nios2_arch.
1122 * configure: Regenerated.
1123 * disassemble.c (ARCH_nios2): Define.
1124 (disassembler): Add case for bfd_arch_nios2.
1125 * nios2-dis.c: New file.
1126 * nios2-opc.c: New file.
1127
545093a4
AM		 11282013-02-04 Alan Modra <amodra@gmail.com>
1129
1130 * po/POTFILES.in: Regenerate.
1131 * rl78-decode.c: Regenerate.
1132 * rx-decode.c: Regenerate.
1133
e30181a5
YZ		 11342013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1135
1136 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1137 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1138 * aarch64-asm.c (convert_xtl_to_shll): New function.
1139 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1140 calling convert_xtl_to_shll.
1141 * aarch64-dis.c (convert_shll_to_xtl): New function.
1142 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1143 calling convert_shll_to_xtl.
1144 * aarch64-gen.c: Update copyright year.
1145 * aarch64-asm-2.c: Re-generate.
1146 * aarch64-dis-2.c: Re-generate.
1147 * aarch64-opc-2.c: Re-generate.
1148
78c8d46c
NC		 11492013-01-24 Nick Clifton <nickc@redhat.com>
1150
1151 * v850-dis.c: Add support for e3v5 architecture.
1152 * v850-opc.c: Likewise.
1153
f5555712
YZ		 11542013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1155
1156 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1157 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1158 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 1159 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 1160 alignment check; change to call set_sft_amount_out_of_range_error
1161 instead of set_imm_out_of_range_error.
1162 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1163 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1164 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1165 SIMD_IMM_SFT.
1166
2f81ff92
L		 11672013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1168
1169 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1170
1171 * i386-init.h: Regenerated.
1172 * i386-tbl.h: Likewise.
1173
dd42f060
NC		 11742013-01-15 Nick Clifton <nickc@redhat.com>
1175
1176 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1177 values.
1178 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1179
a4533ed8
NC		 11802013-01-14 Will Newton <will.newton@imgtec.com>
1181
1182 * metag-dis.c (REG_WIDTH): Increase to 64.
1183
5817ffd1
PB		 11842013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1185
1186 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1187 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1188 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1189 (SH6): Update.
1190 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1191 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1192 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1193 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1194
a3c62988
NC		 11952013-01-10 Will Newton <will.newton@imgtec.com>
1196
1197 * Makefile.am: Add Meta.
1198 * configure.in: Add Meta.
1199 * disassemble.c: Add Meta support.
1200 * metag-dis.c: New file.
1201 * Makefile.in: Regenerate.
1202 * configure: Regenerate.
1203
73335eae
NC		 12042013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1205
1206 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1207 (match_opcode): Rename to cr16_match_opcode.
1208
e407c74b
NC		 12092013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1210
1211 * mips-dis.c: Add names for CP0 registers of r5900.
1212 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1213 instructions sq and lq.
1214 Add support for MIPS r5900 CPU.
1215 Add support for 128 bit MMI (Multimedia Instructions).
1216 Add support for EE instructions (Emotion Engine).
1217 Disable unsupported floating point instructions (64 bit and
1218 undefined compare operations).
1219 Enable instructions of MIPS ISA IV which are supported by r5900.
1220 Disable 64 bit co processor instructions.
1221 Disable 64 bit multiplication and division instructions.
1222 Disable instructions for co-processor 2 and 3, because these are
1223 not supported (preparation for later VU0 support (Vector Unit)).
1224 Disable cvt.w.s because this behaves like trunc.w.s and the
1225 correct execution can't be ensured on r5900.
1226 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1227 will confuse less developers and compilers.
1228
a32c3ff8
NC		 12292013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1230
fb098a1e
YZ		 1231 * aarch64-opc.c (aarch64_print_operand): Change to print
1232 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1233 in comment.
1234 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1235 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1236 OP_MOV_IMM_WIDE.
1237
12382013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1239
1240 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1241 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1242
62658407
L		 12432013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1244
1245 * i386-gen.c (process_copyright): Update copyright year to 2013.
1246
bab4becb 12472013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1248
bab4becb
NC		 1249 * cr16-dis.c (match_opcode,make_instruction): Remove static
1250 declaration.
1251 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1252 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1253
bab4becb 1254For older changes see ChangeLog-2012
252b5132 1255\f
bab4becb 1256Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1257
1258Copying and distribution of this file, with or without modification,
1259are permitted in any medium without royalty provided the copyright
1260notice and this notice are preserved.
1261
252b5132 1262Local Variables:
2f6d2f85
NC		 1263mode: change-log
1264left-margin: 8
1265fill-column: 74
252b5132
RH		 1266version-control: never
1267End:
GDB Binutils - Deliverables
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