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GDB kills itself instead of interrupting inferior
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
1d2db237
RS		 12013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
2
3 PR gas/15220
4 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
5 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
6
a0046408
L		 72013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
8
9 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
10 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
11 PREFIX_0F3ACC.
12 (prefix_table): Updated.
13 (three_byte_table): Likewise.
14 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
15 (cpu_flags): Add CpuSHA.
16 (i386_cpu_flags): Add cpusha.
17 * i386-init.h: Regenerate.
18 * i386-opc.h (CpuSHA): New.
19 (CpuUnused): Restored.
20 (i386_cpu_flags): Add cpusha.
21 * i386-opc.tbl: Add SHA instructions.
22 * i386-tbl.h: Regenerate.
23
7e8b059b
L		 242013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
25 Kirill Yukhin <kirill.yukhin@intel.com>
26 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
27
28 * i386-dis.c (BND_Fixup): New.
29 (Ebnd): New.
30 (Ev_bnd): New.
31 (Gbnd): New.
32 (BND): New.
33 (v_bnd_mode): New.
34 (bnd_mode): New.
c623f86c
L		 35 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
36 MOD_0F1B_PREFIX_1.
37 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 38 (dis tables): Replace XX with BND for near branch and call
39 instructions.
40 (prefix_table): Add new entries.
41 (mod_table): Likewise.
42 (names_bnd): New.
43 (intel_names_bnd): New.
44 (att_names_bnd): New.
45 (BND_PREFIX): New.
46 (prefix_name): Handle BND_PREFIX.
47 (print_insn): Initialize names_bnd.
48 (intel_operand_size): Handle new modes.
49 (OP_E_register): Likewise.
50 (OP_E_memory): Likewise.
51 (OP_G): Likewise.
52 * i386-gen.c (cpu_flag_init): Add CpuMPX.
53 (cpu_flags): Add CpuMPX.
54 (operand_type_init): Add RegBND.
55 (opcode_modifiers): Add BNDPrefixOk.
56 (operand_types): Add RegBND.
57 * i386-init.h: Regenerate.
58 * i386-opc.h (CpuMPX): New.
59 (CpuUnused): Comment out.
60 (i386_cpu_flags): Add cpumpx.
61 (BNDPrefixOk): New.
62 (i386_opcode_modifier): Add bndprefixok.
63 (RegBND): New.
64 (i386_operand_type): Add regbnd.
65 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
66 Add MPX instructions and bnd prefix.
67 * i386-reg.tbl: Add bnd0-bnd3 registers.
68 * i386-tbl.h: Regenerate.
69
b56e23fb
RS		 702013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
71
72 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
73 ATTRIBUTE_UNUSED.
74
e7ae278d
RS		 752013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
76
77 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
78 special rules.
79 * Makefile.in: Regenerate.
80 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
81 all fields. Reformat.
82
c3c07478
RS		 832013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
84
85 * mips16-opc.c: Include mips-formats.h.
86 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
87 static arrays.
88 (decode_mips16_operand): New function.
89 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
90 (print_insn_arg): Handle OP_ENTRY_EXIT list.
91 Abort for OP_SAVE_RESTORE_LIST.
92 (print_mips16_insn_arg): Change interface. Use mips_operand
93 structures. Delete GET_OP_S. Move GET_OP definition to...
94 (print_insn_mips16): ...here. Call init_print_arg_state.
95 Update the call to print_mips16_insn_arg.
96
ab902481
RS		 972013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
98
99 * mips-formats.h: New file.
100 * mips-opc.c: Include mips-formats.h.
101 (reg_0_map): New static array.
102 (decode_mips_operand): New function.
103 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
104 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
105 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
106 (int_c_map): New static arrays.
107 (decode_micromips_operand): New function.
108 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
109 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
110 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
111 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
112 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
113 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
114 (micromips_imm_b_map, micromips_imm_c_map): Delete.
115 (print_reg): New function.
116 (mips_print_arg_state): New structure.
117 (init_print_arg_state, print_insn_arg): New functions.
118 (print_insn_args): Change interface and use mips_operand structures.
119 Delete GET_OP_S. Move GET_OP definition to...
120 (print_insn_mips): ...here. Update the call to print_insn_args.
121 (print_insn_micromips): Use print_insn_args.
122
cc537e56
RS		 1232013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
124
125 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
126 in macros.
127
7a5f87ce
RS		 1282013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
129
130 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
131 ADDA.S, MULA.S and SUBA.S.
132
41741fa4
L		 1332013-07-08 H.J. Lu <hongjiu.lu@intel.com>
134
135 PR gas/13572
136 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
137 * i386-tbl.h: Regenerated.
138
f2ae14a1
RS		 1392013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
140
141 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
142 and SD A(B) macros up.
143 * micromips-opc.c (micromips_opcodes): Likewise.
144
04c9d415
RS		 1452013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
146
147 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
148 instructions.
149
5c324c16
RS		 1502013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
151
152 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
153 MDMX-like instructions.
154 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
155 printing "Q" operands for INSN_5400 instructions.
156
23e69e47
RS		 1572013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
158
159 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
160 "+S" for "cins".
161 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
162 Combine cases.
163
27c5c572
RS		 1642013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
165
166 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
167 "jalx".
168 * mips16-opc.c (mips16_opcodes): Likewise.
169 * micromips-opc.c (micromips_opcodes): Likewise.
170 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
171 (print_insn_mips16): Handle "+i".
172 (print_insn_micromips): Likewise. Conditionally preserve the
173 ISA bit for "a" but not for "+i".
174
e76ff5ab
RS		 1752013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
176
177 * micromips-opc.c (WR_mhi): Rename to..
178 (WR_mh): ...this.
179 (micromips_opcodes): Update "movep" entry accordingly. Replace
180 "mh,mi" with "mh".
181 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
182 (micromips_to_32_reg_h_map1): ...this.
183 (micromips_to_32_reg_i_map): Rename to...
184 (micromips_to_32_reg_h_map2): ...this.
185 (print_micromips_insn): Remove "mi" case. Print both registers
186 in the pair for "mh".
187
fa7616a4
RS		 1882013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
189
190 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
191 * micromips-opc.c (micromips_opcodes): Likewise.
192 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
193 and "+T" handling. Check for a "0" suffix when deciding whether to
194 use coprocessor 0 names. In that case, also check for ",H" selectors.
195
fb798c50
AK		 1962013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
197
198 * s390-opc.c (J12_12, J24_24): New macros.
199 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
200 (MASK_MII_UPI): Rename to MASK_MII_UPP.
201 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
202
58ae08f2
AM		 2032013-07-04 Alan Modra <amodra@gmail.com>
204
205 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
206
b5e04c2b
NC		 2072013-06-26 Nick Clifton <nickc@redhat.com>
208
209 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
210 field when checking for type 2 nop.
211 * rx-decode.c: Regenerate.
212
833794fc
MR		 2132013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
214
215 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
216 and "movep" macros.
217
1bbce132
MR		 2182013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
219
220 * mips-dis.c (is_mips16_plt_tail): New function.
221 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
222 word.
223 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
224
34c911a4
NC		 2252013-06-21 DJ Delorie <dj@redhat.com>
226
227 * msp430-decode.opc: New.
228 * msp430-decode.c: New/generated.
229 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
230 (MAINTAINER_CLEANFILES): Likewise.
231 Add rule to build msp430-decode.c frommsp430decode.opc
232 using the opc2c program.
233 * Makefile.in: Regenerate.
234 * configure.in: Add msp430-decode.lo to msp430 architecture files.
235 * configure: Regenerate.
236
b9eead84
YZ		 2372013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
238
239 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
240 (SYMTAB_AVAILABLE): Removed.
241 (#include "elf/aarch64.h): Ditto.
242
7f3c4072
CM		 2432013-06-17 Catherine Moore <clm@codesourcery.com>
244 Maciej W. Rozycki <macro@codesourcery.com>
245 Chao-Ying Fu <fu@mips.com>
246
247 * micromips-opc.c (EVA): Define.
248 (TLBINV): Define.
249 (micromips_opcodes): Add EVA opcodes.
250 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
251 (print_insn_args): Handle EVA offsets.
252 (print_insn_micromips): Likewise.
253 * mips-opc.c (EVA): Define.
254 (TLBINV): Define.
255 (mips_builtin_opcodes): Add EVA opcodes.
256
de40ceb6
AM		 2572013-06-17 Alan Modra <amodra@gmail.com>
258
259 * Makefile.am (mips-opc.lo): Add rules to create automatic
260 dependency files. Pass archdefs.
261 (micromips-opc.lo, mips16-opc.lo): Likewise.
262 * Makefile.in: Regenerate.
263
3531d549
DD		 2642013-06-14 DJ Delorie <dj@redhat.com>
265
266 * rx-decode.opc (rx_decode_opcode): Bit operations on
267 registers are 32-bit operations, not 8-bit operations.
268 * rx-decode.c: Regenerate.
269
ba92f7fb
CF		 2702013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
271
272 * micromips-opc.c (IVIRT): New define.
273 (IVIRT64): New define.
274 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
275 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
276
277 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
278 dmtgc0 to print cp0 names.
279
9daf7bab
SL		 2802013-06-09 Sandra Loosemore <sandra@codesourcery.com>
281
282 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
283 argument.
284
d301a56b
RS		 2852013-06-08 Catherine Moore <clm@codesourcery.com>
286 Richard Sandiford <rdsandiford@googlemail.com>
287
288 * micromips-opc.c (D32, D33, MC): Update definitions.
289 (micromips_opcodes): Initialize ase field.
290 * mips-dis.c (mips_arch_choice): Add ase field.
291 (mips_arch_choices): Initialize ase field.
292 (set_default_mips_dis_options): Declare and setup mips_ase.
293 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
294 MT32, MC): Update definitions.
295 (mips_builtin_opcodes): Initialize ase field.
296
a3dcb6c5
RS		 2972013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
298
299 * s390-opc.txt (flogr): Require a register pair destination.
300
6cf1d90c
AK		 3012013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
302
303 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
304 instruction format.
305
c77c0862
RS		 3062013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
307
308 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
309
c0637f3a
PB		 3102013-05-20 Peter Bergner <bergner@vnet.ibm.com>
311
312 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
313 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
314 XLS_MASK, PPCVSX2): New defines.
315 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
316 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
317 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
318 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
319 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
320 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
321 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
322 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
323 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
324 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
325 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
326 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
327 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
328 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
329 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
330 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
331 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
332 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
333 <lxvx, stxvx>: New extended mnemonics.
334
4934fdaf
AM		 3352013-05-17 Alan Modra <amodra@gmail.com>
336
337 * ia64-raw.tbl: Replace non-ASCII char.
338 * ia64-waw.tbl: Likewise.
339 * ia64-asmtab.c: Regenerate.
340
6091d651
SE		 3412013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
342
343 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
344 * i386-init.h: Regenerated.
345
d2865ed3
YZ		 3462013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
347
348 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
349 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
350 check from [0, 255] to [-128, 255].
351
b015e599
AP		 3522013-05-09 Andrew Pinski <apinski@cavium.com>
353
354 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
355 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
356 (parse_mips_dis_option): Handle the virt option.
357 (print_insn_args): Handle "+J".
358 (print_mips_disassembler_options): Print out message about virt64.
359 * mips-opc.c (IVIRT): New define.
360 (IVIRT64): New define.
361 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
362 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
363 Move rfe to the bottom as it conflicts with tlbgp.
364
9f0682fe
AM		 3652013-05-09 Alan Modra <amodra@gmail.com>
366
367 * ppc-opc.c (extract_vlesi): Properly sign extend.
368 (extract_vlensi): Likewise. Comment reason for setting invalid.
369
13761a11
NC		 3702013-05-02 Nick Clifton <nickc@redhat.com>
371
372 * msp430-dis.c: Add support for MSP430X instructions.
373
e3031850
SL		 3742013-04-24 Sandra Loosemore <sandra@codesourcery.com>
375
376 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
377 to "eccinj".
378
17310e56
NC		 3792013-04-17 Wei-chen Wang <cole945@gmail.com>
380
381 PR binutils/15369
382 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
383 of CGEN_CPU_ENDIAN.
384 (hash_insns_list): Likewise.
385
731df338
JK		 3862013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
387
388 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
389 warning workaround.
390
5f77db52
JB		 3912013-04-08 Jan Beulich <jbeulich@suse.com>
392
393 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
394 * i386-tbl.h: Re-generate.
395
0afd1215
DM		 3962013-04-06 David S. Miller <davem@davemloft.net>
397
398 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
399 of an opcode, prefer the one with F_PREFERRED set.
400 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
401 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
402 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
403 mark existing mnenomics as aliases. Add "cc" suffix to edge
404 instructions generating condition codes, mark existing mnenomics
405 as aliases. Add "fp" prefix to VIS compare instructions, mark
406 existing mnenomics as aliases.
407
41702d50
NC		 4082013-04-03 Nick Clifton <nickc@redhat.com>
409
410 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
411 destination address by subtracting the operand from the current
412 address.
413 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
414 a positive value in the insn.
415 (extract_u16_loop): Do not negate the returned value.
416 (D16_LOOP): Add V850_INVERSE_PCREL flag.
417
418 (ceilf.sw): Remove duplicate entry.
419 (cvtf.hs): New entry.
420 (cvtf.sh): Likewise.
421 (fmaf.s): Likewise.
422 (fmsf.s): Likewise.
423 (fnmaf.s): Likewise.
424 (fnmsf.s): Likewise.
425 (maddf.s): Restrict to E3V5 architectures.
426 (msubf.s): Likewise.
427 (nmaddf.s): Likewise.
428 (nmsubf.s): Likewise.
429
55cf16e1
L		 4302013-03-27 H.J. Lu <hongjiu.lu@intel.com>
431
432 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
433 check address mode.
434 (print_insn): Pass sizeflag to get_sib.
435
51dcdd4d
NC		 4362013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
437
438 PR binutils/15068
439 * tic6x-dis.c: Add support for displaying 16-bit insns.
440
795b8e6b
NC		 4412013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
442
443 PR gas/15095
444 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
445 individual msb and lsb halves in src1 & src2 fields. Discard the
446 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
447 follow what Ti SDK does in that case as any value in the src1
448 field yields the same output with SDK disassembler.
449
314d60dd
ME		 4502013-03-12 Michael Eager <eager@eagercon.com>
451
795b8e6b 452 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 453
dad60f8e
SL		 4542013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
455
456 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
457
f5cb796a
SL		 4582013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
459
460 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
461
21fde85c
SL		 4622013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
463
464 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
465
dd5181d5
KT		 4662013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
467
468 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
469 (thumb32_opcodes): Likewise.
470 (print_insn_thumb32): Handle 'S' control char.
471
87a8d6cb
NC		 4722013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
473
474 * lm32-desc.c: Regenerate.
475
99dce992
L		 4762013-03-01 H.J. Lu <hongjiu.lu@intel.com>
477
478 * i386-reg.tbl (riz): Add RegRex64.
479 * i386-tbl.h: Regenerated.
480
e60bb1dd
YZ		 4812013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
482
483 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
484 (aarch64_feature_crc): New static.
485 (CRC): New macro.
486 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
487 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
488 * aarch64-asm-2.c: Re-generate.
489 * aarch64-dis-2.c: Ditto.
490 * aarch64-opc-2.c: Ditto.
491
c7570fcd
AM		 4922013-02-27 Alan Modra <amodra@gmail.com>
493
494 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
495 * rl78-decode.c: Regenerate.
496
151fa98f
NC		 4972013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
498
499 * rl78-decode.opc: Fix encoding of DIVWU insn.
500 * rl78-decode.c: Regenerate.
501
5c111e37
L		 5022013-02-19 H.J. Lu <hongjiu.lu@intel.com>
503
504 PR gas/15159
505 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
506
507 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
508 (cpu_flags): Add CpuSMAP.
509
510 * i386-opc.h (CpuSMAP): New.
511 (i386_cpu_flags): Add cpusmap.
512
513 * i386-opc.tbl: Add clac and stac.
514
515 * i386-init.h: Regenerated.
516 * i386-tbl.h: Likewise.
517
9d1df426
NC		 5182013-02-15 Markos Chandras <markos.chandras@imgtec.com>
519
520 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
521 which also makes the disassembler output be in little
522 endian like it should be.
523
a1ccaec9
YZ		 5242013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
525
526 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
527 fields to NULL.
528 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
529
ef068ef4 5302013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 531
532 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
533 section disassembled.
534
6fe6ded9
RE		 5352013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
536
537 * arm-dis.c: Update strht pattern.
538
0aa27725
RS		 5392013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
540
541 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
542 single-float. Disable ll, lld, sc and scd for EE. Disable the
543 trunc.w.s macro for EE.
544
36591ba1
SL		 5452013-02-06 Sandra Loosemore <sandra@codesourcery.com>
546 Andrew Jenner <andrew@codesourcery.com>
547
548 Based on patches from Altera Corporation.
549
550 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
551 nios2-opc.c.
552 * Makefile.in: Regenerated.
553 * configure.in: Add case for bfd_nios2_arch.
554 * configure: Regenerated.
555 * disassemble.c (ARCH_nios2): Define.
556 (disassembler): Add case for bfd_arch_nios2.
557 * nios2-dis.c: New file.
558 * nios2-opc.c: New file.
559
545093a4
AM		 5602013-02-04 Alan Modra <amodra@gmail.com>
561
562 * po/POTFILES.in: Regenerate.
563 * rl78-decode.c: Regenerate.
564 * rx-decode.c: Regenerate.
565
e30181a5
YZ		 5662013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
567
568 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
569 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
570 * aarch64-asm.c (convert_xtl_to_shll): New function.
571 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
572 calling convert_xtl_to_shll.
573 * aarch64-dis.c (convert_shll_to_xtl): New function.
574 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
575 calling convert_shll_to_xtl.
576 * aarch64-gen.c: Update copyright year.
577 * aarch64-asm-2.c: Re-generate.
578 * aarch64-dis-2.c: Re-generate.
579 * aarch64-opc-2.c: Re-generate.
580
78c8d46c
NC		 5812013-01-24 Nick Clifton <nickc@redhat.com>
582
583 * v850-dis.c: Add support for e3v5 architecture.
584 * v850-opc.c: Likewise.
585
f5555712
YZ		 5862013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
587
588 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
589 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
590 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 591 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 592 alignment check; change to call set_sft_amount_out_of_range_error
593 instead of set_imm_out_of_range_error.
594 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
595 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
596 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
597 SIMD_IMM_SFT.
598
2f81ff92
L		 5992013-01-16 H.J. Lu <hongjiu.lu@intel.com>
600
601 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
602
603 * i386-init.h: Regenerated.
604 * i386-tbl.h: Likewise.
605
dd42f060
NC		 6062013-01-15 Nick Clifton <nickc@redhat.com>
607
608 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
609 values.
610 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
611
a4533ed8
NC		 6122013-01-14 Will Newton <will.newton@imgtec.com>
613
614 * metag-dis.c (REG_WIDTH): Increase to 64.
615
5817ffd1
PB		 6162013-01-10 Peter Bergner <bergner@vnet.ibm.com>
617
618 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
619 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
620 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
621 (SH6): Update.
622 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
623 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
624 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
625 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
626
a3c62988
NC		 6272013-01-10 Will Newton <will.newton@imgtec.com>
628
629 * Makefile.am: Add Meta.
630 * configure.in: Add Meta.
631 * disassemble.c: Add Meta support.
632 * metag-dis.c: New file.
633 * Makefile.in: Regenerate.
634 * configure: Regenerate.
635
73335eae
NC		 6362013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
637
638 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
639 (match_opcode): Rename to cr16_match_opcode.
640
e407c74b
NC		 6412013-01-04 Juergen Urban <JuergenUrban@gmx.de>
642
643 * mips-dis.c: Add names for CP0 registers of r5900.
644 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
645 instructions sq and lq.
646 Add support for MIPS r5900 CPU.
647 Add support for 128 bit MMI (Multimedia Instructions).
648 Add support for EE instructions (Emotion Engine).
649 Disable unsupported floating point instructions (64 bit and
650 undefined compare operations).
651 Enable instructions of MIPS ISA IV which are supported by r5900.
652 Disable 64 bit co processor instructions.
653 Disable 64 bit multiplication and division instructions.
654 Disable instructions for co-processor 2 and 3, because these are
655 not supported (preparation for later VU0 support (Vector Unit)).
656 Disable cvt.w.s because this behaves like trunc.w.s and the
657 correct execution can't be ensured on r5900.
658 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
659 will confuse less developers and compilers.
660
a32c3ff8
NC		 6612013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
662
fb098a1e
YZ		 663 * aarch64-opc.c (aarch64_print_operand): Change to print
664 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
665 in comment.
666 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
667 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
668 OP_MOV_IMM_WIDE.
669
6702013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
671
672 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
673 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 674
62658407
L		 6752013-01-02 H.J. Lu <hongjiu.lu@intel.com>
676
677 * i386-gen.c (process_copyright): Update copyright year to 2013.
678
bab4becb 6792013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 680
bab4becb
NC		 681 * cr16-dis.c (match_opcode,make_instruction): Remove static
682 declaration.
683 (dwordU,wordU): Moved typedefs to opcode/cr16.h
684 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 685
bab4becb 686For older changes see ChangeLog-2012
252b5132 687\f
bab4becb 688Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 689
690Copying and distribution of this file, with or without modification,
691are permitted in any medium without royalty provided the copyright
692notice and this notice are preserved.
693
252b5132 694Local Variables:
2f6d2f85
NC		 695mode: change-log
696left-margin: 8
697fill-column: 74
252b5132
RH		 698version-control: never
699End:
GDB Binutils - Deliverables
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