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2012-11-09 Nick Clifton <nickc@redhat.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5bb3703f
L		 12012-11-09 H.J. Lu <hongjiu.lu@intel.com>
2
3 * aarch64-opc.h (gen_mask): Remove trailing redundant `;'.
4 * ia64-gen.c (fetch_insn_class): Likewise.
5
6febeb74
AM		 62012-11-08 Alan Modra <amodra@gmail.com>
7
8 * po/POTFILES.in: Regenerate.
9
d17dce55
AM		 102012-11-05 Alan Modra <amodra@gmail.com>
11
12 * configure.in: Apply 2012-09-10 change to config.in here.
13
aac129d7
AK		 142012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
15
16 * s390-mkopc.c: Accept empty lines in s390-opc.txt.
d17dce55
AM		 17 * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2
18 and RRF_RMRR.
aac129d7
AK		 19 * s390-opc.txt: Add new instructions. New instruction type for lptea.
20
747a4ac1
CG		 212012-10-26 Christian Groessler <chris@groessler.org>
22
23 * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb,
24 trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove
25 non-existing opcode trtrb.
26 * z8k-opc.h: Regenerate.
27
62082a42
AM		 282012-10-26 Alan Modra <amodra@gmail.com>
29
30 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
31
6c067bbb
RM		 322012-10-24 Roland McGrath <mcgrathr@google.com>
33
34 * i386-dis.c (ckprefix): When bailing out for fwait with prefixes,
35 set rex_used to rex.
36
ab4437c3
PB		 372012-10-22 Peter Bergner <bergner@vnet.ibm.com>
38
39 * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
40
9a176a4a
TT		 412012-10-18 Tom Tromey <tromey@redhat.com>
42
43 * tic54x-dis.c (print_instruction): Don't use K&R style.
44 (print_parallel_instruction, sprint_dual_address)
45 (sprint_indirect_address, sprint_direct_address, sprint_mmr)
46 (sprint_cc2, sprint_condition): Likewise.
47
4ad3b7ef
KT		 482012-10-18 Kai Tietz <ktietz@redhat.com>
49
50 * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
51 value with a default.
52 (do_special_encoding): Likewise.
53 (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
54 variables with default.
55 * arc-dis.c (write_comments_): Don't use strncat due
56 size of state->commentBuffer pointer isn't predictable.
57
b7a54b55
YZ		 582012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
59
60 * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
61 rmr_el3; remove daifset and daifclr.
62
9b61754a
YZ		 632012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
64
65 * aarch64-opc.c (operand_general_constraint_met_p): Change to check
66 the alignment of addr.offset.imm instead of that of shifter.amount for
67 operand type AARCH64_OPND_ADDR_UIMM12.
68
f8ece37f
RE		 692012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
70
71 * arm-dis.c: Use preferred form of vrint instruction variants
72 for disassembly.
73
5e5c50d3
NE		 742012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
75
76 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
77 * i386-init.h: Regenerated.
78
c7a5aa9c
PB		 792012-10-05 Peter Bergner <bergner@vnet.ibm.com>
80
81 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
82 * ppc-opc.c (VBA): New define.
83 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
84 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
85
04ee5257
NC		 862012-10-04 Nick Clifton <nickc@redhat.com>
87
88 * v850-dis.c (disassemble): Place square parentheses around second
89 register operand of clr1, not1, set1 and tst1 instructions.
90
cfc72779
AK		 912012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
92
93 * s390-mkopc.c: Support new option zEC12.
94 * s390-opc.c: Add new instruction formats.
95 * s390-opc.txt: Add new instructions for zEC12.
96
1415a2a7
AG		 972012-09-27 Anthony Green <green@moxielogic.com>
98
99 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
100 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
101
160a30bb
L		 1022012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
103
04ee5257
NC		 104 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
105 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
160a30bb
L		 106 and CPU_BTVER2_FLAGS.
107 * i386-init.h: Regenerated.
108
60aa667e
L		 1092012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
110
111 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
112 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
113 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
114 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
115 (cpu_flags): Add CpuCX16.
116 * i386-opc.h (CpuCX16): New.
117 (i386_cpu_flags): Add cpucx16.
118 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
119 * i386-tbl.h: Regenerate.
120 * i386-init.h: Likewise.
121
4b8c8c02
RE		 1222012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
123
60aa667e 124 * arm-dis.c: Changed ldra and strl-form mnemonics
4b8c8c02
RE		 125 to lda and stl-form.
126
83ea18d0
MR		 1272012-09-18 Chao-ying Fu <fu@mips.com>
128
129 * micromips-opc.c (micromips_opcodes): Correct the encoding of
130 the "swxc1" instruction.
131
062f38fa
RE		 1322012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
133
134 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
135 the parameter 'inst'.
136 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
137 (convert_mov_to_movewide): Change to assert (0) when
138 aarch64_wide_constant_p returns FALSE.
139
b132a67d
DE		 1402012-09-14 David Edelsohn <dje.gcc@gmail.com>
141
142 * configure: Regenerate.
143
1f9b75dd
AG		 1442012-09-14 Anthony Green <green@moxielogic.com>
145
146 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
147 the address after the branch instruction.
148
e202fa84
AG		 1492012-09-13 Anthony Green <green@moxielogic.com>
150
151 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
152
00716ab1
AM		 1532012-09-10 Matthias Klose <doko@ubuntu.com>
154
155 * config.in: Disable sanity check for kfreebsd.
156
6d2920c8
L		 1572012-09-10 H.J. Lu <hongjiu.lu@intel.com>
158
159 * configure: Regenerated.
160
b3e14eda
L		 1612012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
162
163 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
164 * ia64-gen.c: Promote completer index type to longlong.
165 (irf_operand): Add new register recognition.
166 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
167 (lookup_specifier): Add new resource recognition.
168 (insert_bit_table_ent): Relax abort condition according to the
169 changed completer index type.
170 (print_dis_table): Fix printf format for completer index.
171 * ia64-ic.tbl: Add a new instruction class.
172 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
173 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
174 * ia64-opc.h: Define short names for new operand types.
175 * ia64-raw.tbl: Add new RAW resource for DAHR register.
176 * ia64-waw.tbl: Add new WAW resource for DAHR register.
177 * ia64-asmtab.c: Regenerate.
178
382c72e9
PB		 1792012-08-29 Peter Bergner <bergner@vnet.ibm.com>
180
181 * ppc-opc.c (VXASHB_MASK): New define.
182 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
183
fb048c26
PB		 1842012-08-28 Peter Bergner <bergner@vnet.ibm.com>
185
186 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
187 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
188 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
189 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
190 vupklsh>: Use VXVA_MASK.
191 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
192 <mfvscr>: Use VXVAVB_MASK.
193 <mtvscr>: Use VXVDVA_MASK.
194 <vspltb>: Use VXUIMM4_MASK.
195 <vsplth>: Use VXUIMM3_MASK.
196 <vspltw>: Use VXUIMM2_MASK.
197
3c9017d2
MGD		 1982012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
199
200 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
201
48adcd8e
MGD		 2022012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
203
204 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
205
4f51b4bd
MGD		 2062012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
207
208 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
209
91ff7894
MGD		 2102012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
211
212 * arm-dis.c (neon_opcodes): Add support for AES instructions.
213
c70a8987
MGD		 2142012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
215
216 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
217 conversions.
218
30bdf752
MGD		 2192012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
220
221 * arm-dis.c (coprocessor_opcodes): Add VRINT.
222 (neon_opcodes): Likewise.
223
7e8e6784
MGD		 2242012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
225
226 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
227 variants.
228 (neon_opcodes): Likewise.
229
73924fbc
MGD		 2302012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
231
232 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
233 (neon_opcodes): Likewise.
234
33399f07
MGD		 2352012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
236
237 * arm-dis.c (coprocessor_opcodes): Add VSEL.
238 (print_insn_coprocessor): Add new %<>c bitfield format
239 specifier.
240
9eb6c0f1
MGD		 2412012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
242
243 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
244 (thumb32_opcodes): Likewise.
245 (print_arm_insn): Add support for %<>T formatter.
246
8884b720
MGD		 2472012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
248
249 * arm-dis.c (arm_opcodes): Add HLT.
250 (thumb_opcodes): Likewise.
251
b79f7053
MGD		 2522012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
253
254 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
255
53c4b28b
MGD		 2562012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
257
258 * arm-dis.c (arm_opcodes): Add SEVL.
259 (thumb_opcodes): Likewise.
260 (thumb32_opcodes): Likewise.
261
e797f7e0
MGD		 2622012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
263
264 * arm-dis.c (data_barrier_option): New function.
265 (print_insn_arm): Use data_barrier_option.
266 (print_insn_thumb32): Use data_barrier_option.
267
e2efe87d
MGD		 2682012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
269
270 * arm-dis.c (COND_UNCOND): New constant.
271 (print_insn_coprocessor): Add support for %u format specifier.
272 (print_insn_neon): Likewise.
273
2c63854f
DM		 2742012-08-21 David S. Miller <davem@davemloft.net>
275
276 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
277 F3F4 macro.
278
e67ed0e8
AM		 2792012-08-20 Edmar Wienskoski <edmar@freescale.com>
280
281 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
282 vabsduh, vabsduw, mviwsplt.
283
7b458c12
L		 2842012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
285
286 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
287 CPU_BTVER2_FLAGS.
288
e67ed0e8 289 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 290
291 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
292 * i386-init.h: Regenerated.
293 * i386-tbl.h: Likewise.
294
eb80cb87
NC		 2952012-08-17 Nick Clifton <nickc@redhat.com>
296
297 * po/uk.po: New Ukranian translation.
298 * configure.in (ALL_LINGUAS): Add uk.
299 * configure: Regenerate.
300
8baf7b78
PB		 3012012-08-16 Peter Bergner <bergner@vnet.ibm.com>
302
303 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
304 RBX for the third operand.
305 <"lswi">: Use RAX for second and NBI for the third operand.
306
3d557b4c
DD		 3072012-08-15 DJ Delorie <dj@redhat.com>
308
309 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
310 operands, so that data addresses can be corrected when not
311 ES-overridden.
312 * rl78-decode.c: Regenerate.
313 * rl78-dis.c (print_insn_rl78): Make order of modifiers
314 irrelevent. When the 'e' specifier is used on an operand and no
315 ES prefix is provided, adjust address to make it absolute.
316
588925d0
PB		 3172012-08-15 Peter Bergner <bergner@vnet.ibm.com>
318
319 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
320
9f6a6cc0
PB		 3212012-08-15 Peter Bergner <bergner@vnet.ibm.com>
322
323 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
324
fc8c4fd1
MR		 3252012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
326
327 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
328 macros, use local variables for info struct member accesses,
329 update the type of the variable used to hold the instruction
330 word.
331 (print_insn_mips, print_mips16_insn_arg): Likewise.
332 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
333 local variables for info struct member accesses.
334 (print_insn_micromips): Add GET_OP_S local macro.
335 (_print_insn_mips): Update the type of the variable used to hold
336 the instruction word.
337
a06ea964 3382012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 339 Laurent Desnogues <laurent.desnogues@arm.com>
340 Jim MacArthur <jim.macarthur@arm.com>
341 Marcus Shawcroft <marcus.shawcroft@arm.com>
342 Nigel Stephens <nigel.stephens@arm.com>
343 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
344 Richard Earnshaw <rearnsha@arm.com>
345 Sofiane Naci <sofiane.naci@arm.com>
346 Tejas Belagod <tejas.belagod@arm.com>
347 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 348
349 * Makefile.am: Add AArch64.
350 * Makefile.in: Regenerate.
351 * aarch64-asm.c: New file.
352 * aarch64-asm.h: New file.
353 * aarch64-dis.c: New file.
354 * aarch64-dis.h: New file.
355 * aarch64-gen.c: New file.
356 * aarch64-opc.c: New file.
357 * aarch64-opc.h: New file.
358 * aarch64-tbl.h: New file.
359 * configure.in: Add AArch64.
360 * configure: Regenerate.
361 * disassemble.c: Add AArch64.
362 * aarch64-asm-2.c: New file (automatically generated).
363 * aarch64-dis-2.c: New file (automatically generated).
364 * aarch64-opc-2.c: New file (automatically generated).
365 * po/POTFILES.in: Regenerate.
366
35d0a169
MR		 3672012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
368
369 * micromips-opc.c (micromips_opcodes): Update comment.
370 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
371 instructions for IOCT as appropriate.
372 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
373 opcode_is_member.
374 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
375 the result of a check for the -Wno-missing-field-initializers
376 GCC option.
377 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
378 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
379 compilation.
380 (mips16-opc.lo): Likewise.
381 (micromips-opc.lo): Likewise.
382 * aclocal.m4: Regenerate.
383 * configure: Regenerate.
384 * Makefile.in: Regenerate.
385
5c5acbbd
L		 3862012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
387
388 PR gas/14423
389 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
390 * i386-init.h: Regenerated.
391
3c892704
NC		 3922012-08-09 Nick Clifton <nickc@redhat.com>
393
394 * po/vi.po: Updated Vietnamese translation.
395
d7189fa5
RM		 3962012-08-07 Roland McGrath <mcgrathr@google.com>
397
398 * i386-dis.c (reg_table): Fill out REG_0F0D table with
399 AMD-reserved cases as "prefetch".
400 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
401 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
402 (reg_table): Use those under REG_0F18.
403 (mod_table): Add those cases as "nop/reserved".
404
4c692bc7
JB		 4052012-08-07 Jan Beulich <jbeulich@suse.com>
406
407 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
408
de882298
RM		 4092012-08-06 Roland McGrath <mcgrathr@google.com>
410
411 * i386-dis.c (print_insn): Print spaces between multiple excess
412 prefixes. Return actual number of excess prefixes consumed,
413 not always one.
414
415 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
416
7bb15c6f
RM		 4172012-08-06 Roland McGrath <mcgrathr@google.com>
418 Victor Khimenko <khim@google.com>
419 H.J. Lu <hongjiu.lu@intel.com>
420
421 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
422 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
423 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
424 (OP_E_register): Likewise.
425 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
426
3843081d
JBG		 4272012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
428
429 * configure.in: Formatting.
430 * configure: Regenerate.
431
48891606
AM		 4322012-08-01 Alan Modra <amodra@gmail.com>
433
434 * h8300-dis.c: Fix printf arg warnings.
435 * i960-dis.c: Likewise.
436 * mips-dis.c: Likewise.
437 * pdp11-dis.c: Likewise.
438 * sh-dis.c: Likewise.
439 * v850-dis.c: Likewise.
440 * configure.in: Formatting.
441 * configure: Regenerate.
442 * rl78-decode.c: Regenerate.
443 * po/POTFILES.in: Regenerate.
444
03f66e8a 4452012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 446 Catherine Moore <clm@codesourcery.com>
447 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 448
449 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
450 (DSP_VOLA): Likewise.
451 (D32, D33): Likewise.
452 (micromips_opcodes): Add DSP ASE instructions.
48891606 453 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 454 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
455
94948e64
JB		 4562012-07-31 Jan Beulich <jbeulich@suse.com>
457
458 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
459 instruction group. Mark as requiring AVX2.
460 * i386-tbl.h: Re-generate.
461
a6dc81d2
NC		 4622012-07-30 Nick Clifton <nickc@redhat.com>
463
464 * po/opcodes.pot: Updated template.
465 * po/es.po: Updated Spanish translation.
466 * po/fi.po: Updated Finnish translation.
467
c4dd807e
MF		 4682012-07-27 Mike Frysinger <vapier@gentoo.org>
469
470 * configure.in (BFD_VERSION): Run bfd/configure --version and
471 parse the output of that.
472 * configure: Regenerate.
473
03edbe3b
JL		 4742012-07-25 James Lemke <jwlemke@codesourcery.com>
475
476 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
477
63d08c68
NC		 4782012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
479 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 480
481 PR binutils/13135
482 * arm-dis.c: Add necessary casts for printing integer values.
483 Use %s when printing string values.
484 * hppa-dis.c: Likewise.
485 * m68k-dis.c: Likewise.
486 * microblaze-dis.c: Likewise.
487 * mips-dis.c: Likewise.
488 * sparc-dis.c: Likewise.
489
ff688e1f
L		 4902012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
491
492 PR binutils/14355
493 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
494 (VEX_LEN_0FXOP_08_CD): Likewise.
495 (VEX_LEN_0FXOP_08_CE): Likewise.
496 (VEX_LEN_0FXOP_08_CF): Likewise.
497 (VEX_LEN_0FXOP_08_EC): Likewise.
498 (VEX_LEN_0FXOP_08_ED): Likewise.
499 (VEX_LEN_0FXOP_08_EE): Likewise.
500 (VEX_LEN_0FXOP_08_EF): Likewise.
501 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
502 vpcomub, vpcomuw, vpcomud, vpcomuq.
503 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
504 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
505 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
506 VEX_LEN_0FXOP_08_EF.
507
e2e1fcde
L		 5082012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
509
510 * i386-dis.c (PREFIX_0F38F6): New.
511 (prefix_table): Add adcx, adox instructions.
512 (three_byte_table): Use PREFIX_0F38F6.
513 (mod_table): Add rdseed instruction.
514 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
515 (cpu_flags): Likewise.
516 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
517 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
518 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
519 prefetchw.
520 * i386-tbl.h: Regenerate.
521 * i386-init.h: Likewise.
522
8b99bf0b
TS		 5232012-07-05 Thomas Schwinge <thomas@codesourcery.com>
524
f4263ca2 525 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 526
416cf80a
SK		 5272012-07-05 Sean Keys <skeys@ipdatasys.com>
528
529 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 530 always be false due to overlapping operand masks.
531 * xgate-opc.c: Corrected 'com' opcode entry and
532 fixed spacing.
416cf80a 533
9fa0f14a
RM		 5342012-07-02 Roland McGrath <mcgrathr@google.com>
535
536 * i386-opc.tbl: Add RepPrefixOk to nop.
537 * i386-tbl.h: Regenerate.
538
4c6a93d3
NC		 5392012-06-28 Nick Clifton <nickc@redhat.com>
540
541 * po/vi.po: Updated Vietnamese translation.
542
29c048b6
RM		 5432012-06-22 Roland McGrath <mcgrathr@google.com>
544
fe13e45b
RM		 545 * i386-opc.tbl: Add RepPrefixOk to ret.
546 * i386-tbl.h: Regenerate.
547
29c048b6
RM		 548 * i386-opc.h (RepPrefixOk): New enum constant.
549 (i386_opcode_modifier): New bitfield 'repprefixok'.
550 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
551 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
552 instructions that have IsString.
553 * i386-tbl.h: Regenerate.
554
c7a8dbf9
AS		 5552012-06-11 Andreas Schwab <schwab@linux-m68k.org>
556
557 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
558 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
559 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
560 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
561 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
562 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
563 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
564 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
565 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
566
94caa966
AM		 5672012-05-19 Alan Modra <amodra@gmail.com>
568
569 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
570 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
571
5eb3690e
AM		 5722012-05-18 Alan Modra <amodra@gmail.com>
573
71fe7bab
AM		 574 * ia64-opc.c: Remove #include "ansidecl.h".
575 * z8kgen.c: Include sysdep.h first.
576
5eb3690e
AM		 577 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
578 * bfin-dis.c: Likewise.
579 * i860-dis.c: Likewise.
580 * ia64-dis.c: Likewise.
581 * ia64-gen.c: Likewise.
582 * m68hc11-dis.c: Likewise.
583 * mmix-dis.c: Likewise.
584 * msp430-dis.c: Likewise.
585 * or32-dis.c: Likewise.
586 * rl78-dis.c: Likewise.
587 * rx-dis.c: Likewise.
588 * tic4x-dis.c: Likewise.
589 * tilegx-opc.c: Likewise.
590 * tilepro-opc.c: Likewise.
591 * rx-decode.c: Regenerate.
592
a4ebc835
AM		 5932012-05-17 James Lemke <jwlemke@codesourcery.com>
594
595 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
596
98c76446
AM		 5972012-05-17 James Lemke <jwlemke@codesourcery.com>
598
599 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
600
df7b86aa
NC		 6012012-05-17 Daniel Richard G. <skunk@iskunk.org>
602 Nick Clifton <nickc@redhat.com>
603
604 PR 14072
605 * configure.in: Add check that sysdep.h has been included before
606 any system header files.
607 * configure: Regenerate.
608 * config.in: Regenerate.
609 * sysdep.h: Generate an error if included before config.h.
610 * alpha-opc.c: Include sysdep.h before any other header file.
611 * alpha-dis.c: Likewise.
612 * avr-dis.c: Likewise.
613 * cgen-opc.c: Likewise.
614 * cr16-dis.c: Likewise.
615 * cris-dis.c: Likewise.
616 * crx-dis.c: Likewise.
617 * d10v-dis.c: Likewise.
618 * d10v-opc.c: Likewise.
619 * d30v-dis.c: Likewise.
620 * d30v-opc.c: Likewise.
621 * h8500-dis.c: Likewise.
622 * i370-dis.c: Likewise.
623 * i370-opc.c: Likewise.
624 * m10200-dis.c: Likewise.
625 * m10300-dis.c: Likewise.
626 * micromips-opc.c: Likewise.
627 * mips-opc.c: Likewise.
628 * mips61-opc.c: Likewise.
629 * moxie-dis.c: Likewise.
630 * or32-opc.c: Likewise.
631 * pj-dis.c: Likewise.
632 * ppc-dis.c: Likewise.
633 * ppc-opc.c: Likewise.
634 * s390-dis.c: Likewise.
635 * sh-dis.c: Likewise.
636 * sh64-dis.c: Likewise.
637 * sparc-dis.c: Likewise.
638 * sparc-opc.c: Likewise.
639 * spu-dis.c: Likewise.
640 * tic30-dis.c: Likewise.
641 * tic54x-dis.c: Likewise.
642 * tic80-dis.c: Likewise.
643 * tic80-opc.c: Likewise.
644 * tilegx-dis.c: Likewise.
645 * tilepro-dis.c: Likewise.
646 * v850-dis.c: Likewise.
647 * v850-opc.c: Likewise.
648 * vax-dis.c: Likewise.
649 * w65-dis.c: Likewise.
650 * xgate-dis.c: Likewise.
651 * xtensa-dis.c: Likewise.
652 * rl78-decode.opc: Likewise.
653 * rl78-decode.c: Regenerate.
654 * rx-decode.opc: Likewise.
655 * rx-decode.c: Regenerate.
656
e1dad58d
AM		 6572012-05-17 Alan Modra <amodra@gmail.com>
658
659 * ppc_dis.c: Don't include elf/ppc.h.
660
101af531
NC		 6612012-05-16 Meador Inge <meadori@codesourcery.com>
662
663 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
664 to PUSH/POP {reg}.
665
6927f982
NC		 6662012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
667 Stephane Carrez <stcarrez@nerim.fr>
668
669 * configure.in: Add S12X and XGATE co-processor support to m68hc11
670 target.
671 * disassemble.c: Likewise.
672 * configure: Regenerate.
673 * m68hc11-dis.c: Make objdump output more consistent, use hex
674 instead of decimal and use 0x prefix for hex.
675 * m68hc11-opc.c: Add S12X and XGATE opcodes.
676
b9c361e0
JL		 6772012-05-14 James Lemke <jwlemke@codesourcery.com>
678
679 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
680 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
681 (vle_opcd_indices): New array.
682 (lookup_vle): New function.
683 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
684 (print_insn_powerpc): Likewise.
685 * ppc-opc.c: Likewise.
686
6872012-05-14 Catherine Moore <clm@codesourcery.com>
688 Maciej W. Rozycki <macro@codesourcery.com>
689 Rhonda Wittels <rhonda@codesourcery.com>
690 Nathan Froyd <froydnj@codesourcery.com>
691
692 * ppc-opc.c (insert_arx, extract_arx): New functions.
693 (insert_ary, extract_ary): New functions.
694 (insert_li20, extract_li20): New functions.
695 (insert_rx, extract_rx): New functions.
696 (insert_ry, extract_ry): New functions.
697 (insert_sci8, extract_sci8): New functions.
698 (insert_sci8n, extract_sci8n): New functions.
699 (insert_sd4h, extract_sd4h): New functions.
700 (insert_sd4w, extract_sd4w): New functions.
701 (insert_vlesi, extract_vlesi): New functions.
702 (insert_vlensi, extract_vlensi): New functions.
703 (insert_vleui, extract_vleui): New functions.
704 (insert_vleil, extract_vleil): New functions.
705 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
706 (BI16, BI32, BO32, B8): New.
707 (B15, B24, CRD32, CRS): New.
708 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
709 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
710 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
711 (SH6_MASK): Use PPC_OPSHIFT_INV.
712 (SI8, UI5, OIMM5, UI7, BO16): New.
713 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
714 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
715 (ALLOW8_SPRG): New.
716 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
717 (OPVUP, OPVUP_MASK OPVUP): New
718 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
719 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
720 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
721 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
722 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
723 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
724 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
725 (SE_IM5, SE_IM5_MASK): New.
726 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
727 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
728 (BO32DNZ, BO32DZ): New.
729 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
730 (PPCVLE): New.
731 (powerpc_opcodes): Add new VLE instructions. Update existing
732 instruction to include PPCVLE if supported.
733 * ppc-dis.c (ppc_opts): Add vle entry.
734 (get_powerpc_dialect): New function.
735 (powerpc_init_dialect): VLE support.
736 (print_insn_big_powerpc): Call get_powerpc_dialect.
737 (print_insn_little_powerpc): Likewise.
738 (operand_value_powerpc): Handle negative shift counts.
739 (print_insn_powerpc): Handle 2-byte instruction lengths.
740
208a4923
NC		 7412012-05-11 Daniel Richard G. <skunk@iskunk.org>
742
743 PR binutils/14028
744 * configure.in: Invoke ACX_HEADER_STRING.
745 * configure: Regenerate.
746 * config.in: Regenerate.
747 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
748 string.h and strings.h.
749
6750a3a7
NC		 7502012-05-11 Nick Clifton <nickc@redhat.com>
751
752 PR binutils/14006
753 * arm-dis.c (print_insn): Fix detection of instruction mode in
754 files containing multiple executable sections.
755
f6c1a2d5
NC		 7562012-05-03 Sean Keys <skeys@ipdatasys.com>
757
758 * Makefile.in, configure: regenerate
759 * disassemble.c (disassembler): Recognize ARCH_XGATE.
760 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
761 New functions.
762 * configure.in: Recognize xgate.
763 * xgate-dis.c, xgate-opc.c: New files for support of xgate
764 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
765 and opcode generation for xgate.
766
78e98aab
DD		 7672012-04-30 DJ Delorie <dj@redhat.com>
768
769 * rx-decode.opc (MOV): Do not sign-extend immediates which are
770 already the maximum bit size.
771 * rx-decode.c: Regenerate.
772
ec668d69
DM		 7732012-04-27 David S. Miller <davem@davemloft.net>
774
2e52845b
DM		 775 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
776 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
777
58004e23
DM		 778 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
779 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
780
698544e1
DM		 781 * sparc-opc.c (CBCOND): New define.
782 (CBCOND_XCC): Likewise.
783 (cbcond): New helper macro.
784 (sparc_opcodes): Add compare-and-branch instructions.
785
6cda1326
DM		 786 * sparc-dis.c (print_insn_sparc): Handle ')'.
787 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
788
ec668d69
DM		 789 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
790 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
791
2615994e
DM		 7922012-04-12 David S. Miller <davem@davemloft.net>
793
794 * sparc-dis.c (X_DISP10): Define.
795 (print_insn_sparc): Handle '='.
796
5de10af0
MF		 7972012-04-01 Mike Frysinger <vapier@gentoo.org>
798
799 * bfin-dis.c (fmtconst): Replace decimal handling with a single
800 sprintf call and the '*' field width.
801
55a36193
MK		 8022012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
803
804 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
805
d6688282
AM		 8062012-03-16 Alan Modra <amodra@gmail.com>
807
808 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
809 (powerpc_opcd_indices): Bump array size.
810 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
811 corresponding to unused opcodes to following entry.
812 (lookup_powerpc): New function, extracted and optimised from..
813 (print_insn_powerpc): ..here.
814
b240011a
AM		 8152012-03-15 Alan Modra <amodra@gmail.com>
816 James Lemke <jwlemke@codesourcery.com>
817
818 * disassemble.c (disassemble_init_for_target): Handle ppc init.
819 * ppc-dis.c (private): New var.
820 (powerpc_init_dialect): Don't return calloc failure, instead use
821 private.
822 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
823 (powerpc_opcd_indices): New array.
824 (disassemble_init_powerpc): New function.
825 (print_insn_big_powerpc): Don't init dialect here.
826 (print_insn_little_powerpc): Likewise.
827 (print_insn_powerpc): Start search using powerpc_opcd_indices.
828
aea77599
AM		 8292012-03-10 Edmar Wienskoski <edmar@freescale.com>
830
831 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
832 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
833 (PPCVEC2, PPCTMR, E6500): New short names.
834 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
835 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
836 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
837 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
838 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
839 optional operands on sync instruction for E6500 target.
840
5333187a
AK		 8412012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
842
843 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
844
a597d2d3
AM		 8452012-02-27 Alan Modra <amodra@gmail.com>
846
847 * mt-dis.c: Regenerate.
848
3f26eb3a
AM		 8492012-02-27 Alan Modra <amodra@gmail.com>
850
851 * v850-opc.c (extract_v8): Rearrange to make it obvious this
852 is the inverse of corresponding insert function.
853 (extract_d22, extract_u9, extract_r4): Likewise.
854 (extract_d9): Correct sign extension.
855 (extract_d16_15): Don't assume "long" is 32 bits, and don't
856 rely on implementation defined behaviour for shift right of
857 signed types.
858 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
859 (extract_d23): Likewise, and correct mask.
860
1f42f8b3
AM		 8612012-02-27 Alan Modra <amodra@gmail.com>
862
863 * crx-dis.c (print_arg): Mask constant to 32 bits.
864 * crx-opc.c (cst4_map): Use int array.
865
cdb06235
AM		 8662012-02-27 Alan Modra <amodra@gmail.com>
867
868 * arc-dis.c (BITS): Don't use shifts to mask off bits.
869 (FIELDD): Sign extend with xor,sub.
870
6f7be959
WL		 8712012-02-25 Walter Lee <walt@tilera.com>
872
873 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
874 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
875 TILEPRO_OPC_LW_TLS_SN.
876
82c2def5
L		 8772012-02-21 H.J. Lu <hongjiu.lu@intel.com>
878
879 * i386-opc.h (HLEPrefixNone): New.
880 (HLEPrefixLock): Likewise.
881 (HLEPrefixAny): Likewise.
882 (HLEPrefixRelease): Likewise.
883
42164a71
L		 8842012-02-08 H.J. Lu <hongjiu.lu@intel.com>
885
886 * i386-dis.c (HLE_Fixup1): New.
887 (HLE_Fixup2): Likewise.
888 (HLE_Fixup3): Likewise.
889 (Ebh1): Likewise.
890 (Evh1): Likewise.
891 (Ebh2): Likewise.
892 (Evh2): Likewise.
893 (Ebh3): Likewise.
894 (Evh3): Likewise.
895 (MOD_C6_REG_7): Likewise.
896 (MOD_C7_REG_7): Likewise.
897 (RM_C6_REG_7): Likewise.
898 (RM_C7_REG_7): Likewise.
899 (XACQUIRE_PREFIX): Likewise.
900 (XRELEASE_PREFIX): Likewise.
901 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
902 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
903 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
904 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
905 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
906 MOD_C6_REG_7 and MOD_C7_REG_7.
907 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
908 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
909 xtest.
910 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
911 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
912
913 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
914 CPU_RTM_FLAGS.
915 (cpu_flags): Add CpuHLE and CpuRTM.
916 (opcode_modifiers): Add HLEPrefixOk.
917
918 * i386-opc.h (CpuHLE): New.
919 (CpuRTM): Likewise.
920 (HLEPrefixOk): Likewise.
921 (i386_cpu_flags): Add cpuhle and cpurtm.
922 (i386_opcode_modifier): Add hleprefixok.
923
924 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
925 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
926 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
927 operand. Add xacquire, xrelease, xabort, xbegin, xend and
928 xtest.
929 * i386-init.h: Regenerated.
930 * i386-tbl.h: Likewise.
931
21abe33a
DD		 9322012-01-24 DJ Delorie <dj@redhat.com>
933
934 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
935 * rl78-decode.c: Regenerate.
936
e20cc039
AM		 9372012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
938
939 PR binutils/10173
940 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
941
e143d25c
AS		 9422012-01-17 Andreas Schwab <schwab@linux-m68k.org>
943
944 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
945 register and move them after pmove with PSR/PCSR register.
946
8729a6f6
L		 9472012-01-13 H.J. Lu <hongjiu.lu@intel.com>
948
949 * i386-dis.c (mod_table): Add vmfunc.
950
951 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
952 (cpu_flags): CpuVMFUNC.
953
954 * i386-opc.h (CpuVMFUNC): New.
955 (i386_cpu_flags): Add cpuvmfunc.
956
957 * i386-opc.tbl: Add vmfunc.
958 * i386-init.h: Regenerated.
959 * i386-tbl.h: Likewise.
5011093d 960
23e1d329 961For older changes see ChangeLog-2011
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RH		 962\f
963Local Variables:
2f6d2f85
NC		 964mode: change-log
965left-margin: 8
966fill-column: 74
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RH		 967version-control: never
968End:
GDB Binutils - Deliverables
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