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X86: Rename REG_82 to REG_83
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7148c369
L		 12016-11-03 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-dis.c (REG_82): Renamed to ...
4 (REG_83): This.
5 (dis386): Updated.
6 (reg_table): Likewise.
7
47acf0bd
IT		 82016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
9
10 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
11 * i386-dis-evex.h (evex_table): Updated.
12 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
13 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
14 (cpu_flags): Add CpuAVX512_4VNNIW.
15 * i386-opc.h (enum): (AVX512_4VNNIW): New.
16 (i386_cpu_flags): Add cpuavx512_4vnniw.
17 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
18 * i386-init.h: Regenerate.
19 * i386-tbl.h: Ditto.
20
920d2ddc
IT		 212016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
22
23 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
24 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
25 * i386-dis-evex.h (evex_table): Updated.
26 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
27 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
28 (cpu_flags): Add CpuAVX512_4FMAPS.
29 (opcode_modifiers): Add ImplicitQuadGroup modifier.
30 * i386-opc.h (AVX512_4FMAP): New.
31 (i386_cpu_flags): Add cpuavx512_4fmaps.
32 (ImplicitQuadGroup): New.
33 (i386_opcode_modifier): Add implicitquadgroup.
34 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
35 * i386-init.h: Regenerate.
36 * i386-tbl.h: Ditto.
37
e23eba97
NC		 382016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
39 Andrew Waterman <andrew@sifive.com>
40
41 Add support for RISC-V architecture.
42 * configure.ac: Add entry for bfd_riscv_arch.
43 * configure: Regenerate.
44 * disassemble.c (disassembler): Add support for riscv.
45 (disassembler_usage): Likewise.
46 * riscv-dis.c: New file.
47 * riscv-opc.c: New file.
48
b5cefcca
L		 492016-10-21 H.J. Lu <hongjiu.lu@intel.com>
50
51 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
52 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
53 (rm_table): Update the RM_0FAE_REG_7 entry.
54 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
55 (cpu_flags): Remove CpuPCOMMIT.
56 * i386-opc.h (CpuPCOMMIT): Removed.
57 (i386_cpu_flags): Remove cpupcommit.
58 * i386-opc.tbl: Remove pcommit.
59 * i386-init.h: Regenerated.
60 * i386-tbl.h: Likewise.
61
9889cbb1
L		 622016-10-20 H.J. Lu <hongjiu.lu@intel.com>
63
64 PR binutis/20705
65 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
66 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
67 32-bit mode. Don't check vex.register_specifier in 32-bit
68 mode.
69 (OP_VEX): Check for invalid mask registers.
70
28596323
L		 712016-10-18 H.J. Lu <hongjiu.lu@intel.com>
72
73 PR binutis/20699
74 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
75 sizeflag.
76
da8d7d66
L		 772016-10-18 H.J. Lu <hongjiu.lu@intel.com>
78
79 PR binutis/20704
80 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
81
eaf02703
MR		 822016-10-18 Maciej W. Rozycki <macro@imgtec.com>
83
84 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
85 local variable to `index_regno'.
86
decf5bd1
CM		 872016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
88
89 * arc-tbl.h: Removed any "inv.+" instructions from the table.
90
e5b06ef0
CZ		 912016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
92
93 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
94 usage on ISA basis.
95
93562a34
JW		 962016-10-11 Jiong Wang <jiong.wang@arm.com>
97
98 PR target/20666
99 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
100
362c0c4d
JW		 1012016-10-07 Jiong Wang <jiong.wang@arm.com>
102
103 PR target/20667
104 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
105 available.
106
1047201f
AM		 1072016-10-07 Alan Modra <amodra@gmail.com>
108
109 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
110
1a0670f3
AM		 1112016-10-06 Alan Modra <amodra@gmail.com>
112
113 * aarch64-opc.c: Spell fall through comments consistently.
114 * i386-dis.c: Likewise.
115 * aarch64-dis.c: Add missing fall through comments.
116 * aarch64-opc.c: Likewise.
117 * arc-dis.c: Likewise.
118 * arm-dis.c: Likewise.
119 * i386-dis.c: Likewise.
120 * m68k-dis.c: Likewise.
121 * mep-asm.c: Likewise.
122 * ns32k-dis.c: Likewise.
123 * sh-dis.c: Likewise.
124 * tic4x-dis.c: Likewise.
125 * tic6x-dis.c: Likewise.
126 * vax-dis.c: Likewise.
127
2b804145
AM		 1282016-10-06 Alan Modra <amodra@gmail.com>
129
130 * arc-ext.c (create_map): Add missing break.
131 * msp430-decode.opc (encode_as): Likewise.
132 * msp430-decode.c: Regenerate.
133
616ec358
AM		 1342016-10-06 Alan Modra <amodra@gmail.com>
135
136 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
137 * crx-dis.c (print_insn_crx): Likewise.
138
72da393d
L		 1392016-09-30 H.J. Lu <hongjiu.lu@intel.com>
140
141 PR binutils/20657
142 * i386-dis.c (putop): Don't assign alt twice.
143
744ce302
JW		 1442016-09-29 Jiong Wang <jiong.wang@arm.com>
145
146 PR target/20553
147 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
148
a5721ba2
AM		 1492016-09-29 Alan Modra <amodra@gmail.com>
150
151 * ppc-opc.c (L): Make compulsory.
152 (LOPT): New, optional form of L.
153 (HTM_R): Define as LOPT.
154 (L0, L1): Delete.
155 (L32OPT): New, optional for 32-bit L.
156 (L2OPT): New, 2-bit L for dcbf.
157 (SVC_LEC): Update.
158 (L2): Define.
159 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
160 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
161 <dcbf>: Use L2OPT.
162 <tlbiel, tlbie>: Use LOPT.
163 <wclr, wclrall>: Use L2.
164
c5da1932
VZ		 1652016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
166
167 * Makefile.in: Regenerate.
168 * configure: Likewise.
169
2b848ebd
CZ		 1702016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
171
172 * arc-ext-tbl.h (EXTINSN2OPF): Define.
173 (EXTINSN2OP): Use EXTINSN2OPF.
174 (bspeekm, bspop, modapp): New extension instructions.
175 * arc-opc.c (F_DNZ_ND): Define.
176 (F_DNZ_D): Likewise.
177 (F_SIZEB1): Changed.
178 (C_DNZ_D): Define.
179 (C_HARD): Changed.
180 * arc-tbl.h (dbnz): New instruction.
181 (prealloc): Allow it for ARC EM.
182 (xbfu): Likewise.
183
ad43e107
RS		 1842016-09-21 Richard Sandiford <richard.sandiford@arm.com>
185
186 * aarch64-opc.c (print_immediate_offset_address): Print spaces
187 after commas in addresses.
188 (aarch64_print_operand): Likewise.
189
ab3b8fcf
RS		 1902016-09-21 Richard Sandiford <richard.sandiford@arm.com>
191
192 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
193 rather than "should be" or "expected to be" in error messages.
194
bb7eff52
RS		 1952016-09-21 Richard Sandiford <richard.sandiford@arm.com>
196
197 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
198 (print_mnemonic_name): ...here.
199 (print_comment): New function.
200 (print_aarch64_insn): Call it.
201 * aarch64-opc.c (aarch64_conds): Add SVE names.
202 (aarch64_print_operand): Print alternative condition names in
203 a comment.
204
c0890d26
RS		 2052016-09-21 Richard Sandiford <richard.sandiford@arm.com>
206
207 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
208 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
209 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
210 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
211 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
212 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
213 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
214 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
215 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
216 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
217 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
218 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
219 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
220 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
221 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
222 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
223 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
224 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
225 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
226 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
227 (OP_SVE_XWU, OP_SVE_XXU): New macros.
228 (aarch64_feature_sve): New variable.
229 (SVE): New macro.
230 (_SVE_INSN): Likewise.
231 (aarch64_opcode_table): Add SVE instructions.
232 * aarch64-opc.h (extract_fields): Declare.
233 * aarch64-opc-2.c: Regenerate.
234 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
235 * aarch64-asm-2.c: Regenerate.
236 * aarch64-dis.c (extract_fields): Make global.
237 (do_misc_decoding): Handle the new SVE aarch64_ops.
238 * aarch64-dis-2.c: Regenerate.
239
116b6019
RS		 2402016-09-21 Richard Sandiford <richard.sandiford@arm.com>
241
242 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
243 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
244 aarch64_field_kinds.
245 * aarch64-opc.c (fields): Add corresponding entries.
246 * aarch64-asm.c (aarch64_get_variant): New function.
247 (aarch64_encode_variant_using_iclass): Likewise.
248 (aarch64_opcode_encode): Call it.
249 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
250 (aarch64_opcode_decode): Call it.
251
047cd301
RS		 2522016-09-21 Richard Sandiford <richard.sandiford@arm.com>
253
254 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
255 and FP register operands.
256 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
257 (FLD_SVE_Vn): New aarch64_field_kinds.
258 * aarch64-opc.c (fields): Add corresponding entries.
259 (aarch64_print_operand): Handle the new SVE core and FP register
260 operands.
261 * aarch64-opc-2.c: Regenerate.
262 * aarch64-asm-2.c: Likewise.
263 * aarch64-dis-2.c: Likewise.
264
165d4950
RS		 2652016-09-21 Richard Sandiford <richard.sandiford@arm.com>
266
267 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
268 immediate operands.
269 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
270 * aarch64-opc.c (fields): Add corresponding entry.
271 (operand_general_constraint_met_p): Handle the new SVE FP immediate
272 operands.
273 (aarch64_print_operand): Likewise.
274 * aarch64-opc-2.c: Regenerate.
275 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
276 (ins_sve_float_zero_one): New inserters.
277 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
278 (aarch64_ins_sve_float_half_two): Likewise.
279 (aarch64_ins_sve_float_zero_one): Likewise.
280 * aarch64-asm-2.c: Regenerate.
281 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
282 (ext_sve_float_zero_one): New extractors.
283 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
284 (aarch64_ext_sve_float_half_two): Likewise.
285 (aarch64_ext_sve_float_zero_one): Likewise.
286 * aarch64-dis-2.c: Regenerate.
287
e950b345
RS		 2882016-09-21 Richard Sandiford <richard.sandiford@arm.com>
289
290 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
291 integer immediate operands.
292 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
293 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
294 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
295 * aarch64-opc.c (fields): Add corresponding entries.
296 (operand_general_constraint_met_p): Handle the new SVE integer
297 immediate operands.
298 (aarch64_print_operand): Likewise.
299 (aarch64_sve_dupm_mov_immediate_p): New function.
300 * aarch64-opc-2.c: Regenerate.
301 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
302 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
303 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
304 (aarch64_ins_limm): ...here.
305 (aarch64_ins_inv_limm): New function.
306 (aarch64_ins_sve_aimm): Likewise.
307 (aarch64_ins_sve_asimm): Likewise.
308 (aarch64_ins_sve_limm_mov): Likewise.
309 (aarch64_ins_sve_shlimm): Likewise.
310 (aarch64_ins_sve_shrimm): Likewise.
311 * aarch64-asm-2.c: Regenerate.
312 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
313 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
314 * aarch64-dis.c (decode_limm): New function, split out from...
315 (aarch64_ext_limm): ...here.
316 (aarch64_ext_inv_limm): New function.
317 (decode_sve_aimm): Likewise.
318 (aarch64_ext_sve_aimm): Likewise.
319 (aarch64_ext_sve_asimm): Likewise.
320 (aarch64_ext_sve_limm_mov): Likewise.
321 (aarch64_top_bit): Likewise.
322 (aarch64_ext_sve_shlimm): Likewise.
323 (aarch64_ext_sve_shrimm): Likewise.
324 * aarch64-dis-2.c: Regenerate.
325
98907a70
RS		 3262016-09-21 Richard Sandiford <richard.sandiford@arm.com>
327
328 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
329 operands.
330 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
331 the AARCH64_MOD_MUL_VL entry.
332 (value_aligned_p): Cope with non-power-of-two alignments.
333 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
334 (print_immediate_offset_address): Likewise.
335 (aarch64_print_operand): Likewise.
336 * aarch64-opc-2.c: Regenerate.
337 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
338 (ins_sve_addr_ri_s9xvl): New inserters.
339 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
340 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
341 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
342 * aarch64-asm-2.c: Regenerate.
343 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
344 (ext_sve_addr_ri_s9xvl): New extractors.
345 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
346 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
347 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
348 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
349 * aarch64-dis-2.c: Regenerate.
350
4df068de
RS		 3512016-09-21 Richard Sandiford <richard.sandiford@arm.com>
352
353 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
354 address operands.
355 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
356 (FLD_SVE_xs_22): New aarch64_field_kinds.
357 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
358 (get_operand_specific_data): New function.
359 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
360 FLD_SVE_xs_14 and FLD_SVE_xs_22.
361 (operand_general_constraint_met_p): Handle the new SVE address
362 operands.
363 (sve_reg): New array.
364 (get_addr_sve_reg_name): New function.
365 (aarch64_print_operand): Handle the new SVE address operands.
366 * aarch64-opc-2.c: Regenerate.
367 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
368 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
369 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
370 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
371 (aarch64_ins_sve_addr_rr_lsl): Likewise.
372 (aarch64_ins_sve_addr_rz_xtw): Likewise.
373 (aarch64_ins_sve_addr_zi_u5): Likewise.
374 (aarch64_ins_sve_addr_zz): Likewise.
375 (aarch64_ins_sve_addr_zz_lsl): Likewise.
376 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
377 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
378 * aarch64-asm-2.c: Regenerate.
379 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
380 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
381 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
382 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
383 (aarch64_ext_sve_addr_ri_u6): Likewise.
384 (aarch64_ext_sve_addr_rr_lsl): Likewise.
385 (aarch64_ext_sve_addr_rz_xtw): Likewise.
386 (aarch64_ext_sve_addr_zi_u5): Likewise.
387 (aarch64_ext_sve_addr_zz): Likewise.
388 (aarch64_ext_sve_addr_zz_lsl): Likewise.
389 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
390 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
391 * aarch64-dis-2.c: Regenerate.
392
2442d846
RS		 3932016-09-21 Richard Sandiford <richard.sandiford@arm.com>
394
395 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
396 AARCH64_OPND_SVE_PATTERN_SCALED.
397 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
398 * aarch64-opc.c (fields): Add a corresponding entry.
399 (set_multiplier_out_of_range_error): New function.
400 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
401 (operand_general_constraint_met_p): Handle
402 AARCH64_OPND_SVE_PATTERN_SCALED.
403 (print_register_offset_address): Use PRIi64 to print the
404 shift amount.
405 (aarch64_print_operand): Likewise. Handle
406 AARCH64_OPND_SVE_PATTERN_SCALED.
407 * aarch64-opc-2.c: Regenerate.
408 * aarch64-asm.h (ins_sve_scale): New inserter.
409 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
410 * aarch64-asm-2.c: Regenerate.
411 * aarch64-dis.h (ext_sve_scale): New inserter.
412 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
413 * aarch64-dis-2.c: Regenerate.
414
245d2e3f
RS		 4152016-09-21 Richard Sandiford <richard.sandiford@arm.com>
416
417 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
418 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
419 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
420 (FLD_SVE_prfop): Likewise.
421 * aarch64-opc.c: Include libiberty.h.
422 (aarch64_sve_pattern_array): New variable.
423 (aarch64_sve_prfop_array): Likewise.
424 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
425 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
426 AARCH64_OPND_SVE_PRFOP.
427 * aarch64-asm-2.c: Regenerate.
428 * aarch64-dis-2.c: Likewise.
429 * aarch64-opc-2.c: Likewise.
430
d50c751e
RS		 4312016-09-21 Richard Sandiford <richard.sandiford@arm.com>
432
433 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
434 AARCH64_OPND_QLF_P_[ZM].
435 (aarch64_print_operand): Print /z and /m where appropriate.
436
f11ad6bc
RS		 4372016-09-21 Richard Sandiford <richard.sandiford@arm.com>
438
439 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
440 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
441 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
442 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
443 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
444 * aarch64-opc.c (fields): Add corresponding entries here.
445 (operand_general_constraint_met_p): Check that SVE register lists
446 have the correct length. Check the ranges of SVE index registers.
447 Check for cases where p8-p15 are used in 3-bit predicate fields.
448 (aarch64_print_operand): Handle the new SVE operands.
449 * aarch64-opc-2.c: Regenerate.
450 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
451 * aarch64-asm.c (aarch64_ins_sve_index): New function.
452 (aarch64_ins_sve_reglist): Likewise.
453 * aarch64-asm-2.c: Regenerate.
454 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
455 * aarch64-dis.c (aarch64_ext_sve_index): New function.
456 (aarch64_ext_sve_reglist): Likewise.
457 * aarch64-dis-2.c: Regenerate.
458
0c608d6b
RS		 4592016-09-21 Richard Sandiford <richard.sandiford@arm.com>
460
461 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
462 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
463 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
464 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
465 tied operands.
466
01dbfe4c
RS		 4672016-09-21 Richard Sandiford <richard.sandiford@arm.com>
468
469 * aarch64-opc.c (get_offset_int_reg_name): New function.
470 (print_immediate_offset_address): Likewise.
471 (print_register_offset_address): Take the base and offset
472 registers as parameters.
473 (aarch64_print_operand): Update caller accordingly. Use
474 print_immediate_offset_address.
475
72e9f319
RS		 4762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
477
478 * aarch64-opc.c (BANK): New macro.
479 (R32, R64): Take a register number as argument
480 (int_reg): Use BANK.
481
8a7f0c1b
RS		 4822016-09-21 Richard Sandiford <richard.sandiford@arm.com>
483
484 * aarch64-opc.c (print_register_list): Add a prefix parameter.
485 (aarch64_print_operand): Update accordingly.
486
aa2aa4c6
RS		 4872016-09-21 Richard Sandiford <richard.sandiford@arm.com>
488
489 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
490 for FPIMM.
491 * aarch64-asm.h (ins_fpimm): New inserter.
492 * aarch64-asm.c (aarch64_ins_fpimm): New function.
493 * aarch64-asm-2.c: Regenerate.
494 * aarch64-dis.h (ext_fpimm): New extractor.
495 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
496 (aarch64_ext_fpimm): New function.
497 * aarch64-dis-2.c: Regenerate.
498
b5464a68
RS		 4992016-09-21 Richard Sandiford <richard.sandiford@arm.com>
500
501 * aarch64-asm.c: Include libiberty.h.
502 (insert_fields): New function.
503 (aarch64_ins_imm): Use it.
504 * aarch64-dis.c (extract_fields): New function.
505 (aarch64_ext_imm): Use it.
506
42408347
RS		 5072016-09-21 Richard Sandiford <richard.sandiford@arm.com>
508
509 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
510 with an esize parameter.
511 (operand_general_constraint_met_p): Update accordingly.
512 Fix misindented code.
513 * aarch64-asm.c (aarch64_ins_limm): Update call to
514 aarch64_logical_immediate_p.
515
4989adac
RS		 5162016-09-21 Richard Sandiford <richard.sandiford@arm.com>
517
518 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
519
bd11d5d8
RS		 5202016-09-21 Richard Sandiford <richard.sandiford@arm.com>
521
522 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
523
f807f43d
CZ		 5242016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
525
526 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
527
fd486b63
PB		 5282016-09-14 Peter Bergner <bergner@vnet.ibm.com>
529
530 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
531 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
532 xor3>: Delete mnemonics.
533 <cp_abort>: Rename mnemonic from ...
534 <cpabort>: ...to this.
535 <setb>: Change to a X form instruction.
536 <sync>: Change to 1 operand form.
537 <copy>: Delete mnemonic.
538 <copy_first>: Rename mnemonic from ...
539 <copy>: ...to this.
540 <paste, paste.>: Delete mnemonics.
541 <paste_last>: Rename mnemonic from ...
542 <paste.>: ...to this.
543
dce08442
AK		 5442016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
545
546 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
547
952c3f51
AK		 5482016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
549
550 * s390-mkopc.c (main): Support alternate arch strings.
551
8b71537b
PS		 5522016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
553
554 * s390-opc.txt: Fix kmctr instruction type.
555
5b64d091
L		 5562016-09-07 H.J. Lu <hongjiu.lu@intel.com>
557
558 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
559 * i386-init.h: Regenerated.
560
7763838e
CM		 5612016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
562
563 * opcodes/arc-dis.c (print_insn_arc): Changed.
564
1b8b6532
JM		 5652016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
566
567 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
568 camellia_fl.
569
1a336194
TP		 5702016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
571
572 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
573 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
574 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
575
6b40c462
L		 5762016-08-24 H.J. Lu <hongjiu.lu@intel.com>
577
578 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
579 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
580 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
581 PREFIX_MOD_3_0FAE_REG_4.
582 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
583 PREFIX_MOD_3_0FAE_REG_4.
584 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
585 (cpu_flags): Add CpuPTWRITE.
586 * i386-opc.h (CpuPTWRITE): New.
587 (i386_cpu_flags): Add cpuptwrite.
588 * i386-opc.tbl: Add ptwrite instruction.
589 * i386-init.h: Regenerated.
590 * i386-tbl.h: Likewise.
591
ab548d2d
AK		 5922016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
593
594 * arc-dis.h: Wrap around in extern "C".
595
344bde0a
RS		 5962016-08-23 Richard Sandiford <richard.sandiford@arm.com>
597
598 * aarch64-tbl.h (V8_2_INSN): New macro.
599 (aarch64_opcode_table): Use it.
600
5ce912d8
RS		 6012016-08-23 Richard Sandiford <richard.sandiford@arm.com>
602
603 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
604 CORE_INSN, __FP_INSN and SIMD_INSN.
605
9d30b0bd
RS		 6062016-08-23 Richard Sandiford <richard.sandiford@arm.com>
607
608 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
609 (aarch64_opcode_table): Update uses accordingly.
610
dfdaec14
AJ		 6112016-07-25 Andrew Jenner <andrew@codesourcery.com>
612 Kwok Cheung Yeung <kcy@codesourcery.com>
613
614 opcodes/
615 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
616 'e_cmplwi' to 'e_cmpli' instead.
617 (OPVUPRT, OPVUPRT_MASK): Define.
618 (powerpc_opcodes): Add E200Z4 insns.
619 (vle_opcodes): Add context save/restore insns.
620
7bd374a4
MR		 6212016-07-27 Maciej W. Rozycki <macro@imgtec.com>
622
623 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
624 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
625 "j".
626
db18dbab
GM		 6272016-07-27 Graham Markall <graham.markall@embecosm.com>
628
629 * arc-nps400-tbl.h: Change block comments to GNU format.
630 * arc-dis.c: Add new globals addrtypenames,
631 addrtypenames_max, and addtypeunknown.
632 (get_addrtype): New function.
633 (print_insn_arc): Print colons and address types when
634 required.
635 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
636 define insert and extract functions for all address types.
637 (arc_operands): Add operands for colon and all address
638 types.
639 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
640 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
641 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
642 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
643 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
644 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
645
fecd57f9
L		 6462016-07-21 H.J. Lu <hongjiu.lu@intel.com>
647
648 * configure: Regenerated.
649
37fd5ef3
CZ		 6502016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
651
652 * arc-dis.c (skipclass): New structure.
653 (decodelist): New variable.
654 (is_compatible_p): New function.
655 (new_element): Likewise.
656 (skip_class_p): Likewise.
657 (find_format_from_table): Use skip_class_p function.
658 (find_format): Decode first the extension instructions.
659 (print_insn_arc): Select either ARCEM or ARCHS based on elf
660 e_flags.
661 (parse_option): New function.
662 (parse_disassembler_options): Likewise.
663 (print_arc_disassembler_options): Likewise.
664 (print_insn_arc): Use parse_disassembler_options function. Proper
665 select ARCv2 cpu variant.
666 * disassemble.c (disassembler_usage): Add ARC disassembler
667 options.
668
92281a5b
MR		 6692016-07-13 Maciej W. Rozycki <macro@imgtec.com>
670
671 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
672 annotation from the "nal" entry and reorder it beyond "bltzal".
673
6e7ced37
JM		 6742016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
675
676 * sparc-opc.c (ldtxa): New macro.
677 (sparc_opcodes): Use the macro defined above to add entries for
678 the LDTXA instructions.
679 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
680 instruction.
681
2f831b9a 6822016-07-07 James Bowman <james.bowman@ftdichip.com>
683
684 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
685 and "jmpc".
686
c07315e0
JB		 6872016-07-01 Jan Beulich <jbeulich@suse.com>
688
689 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
690 (movzb): Adjust to cover all permitted suffixes.
691 (movzw): New.
692 * i386-tbl.h: Re-generate.
693
9243100a
JB		 6942016-07-01 Jan Beulich <jbeulich@suse.com>
695
696 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
697 (lgdt): Remove Tbyte from non-64-bit variant.
698 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
699 xsaves64, xsavec64): Remove Disp16.
700 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
701 Remove Disp32S from non-64-bit variants. Remove Disp16 from
702 64-bit variants.
703 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
704 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
705 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
706 64-bit variants.
707 * i386-tbl.h: Re-generate.
708
8325cc63
JB		 7092016-07-01 Jan Beulich <jbeulich@suse.com>
710
711 * i386-opc.tbl (xlat): Remove RepPrefixOk.
712 * i386-tbl.h: Re-generate.
713
838441e4
YQ		 7142016-06-30 Yao Qi <yao.qi@linaro.org>
715
716 * arm-dis.c (print_insn): Fix typo in comment.
717
dab26bf4
RS		 7182016-06-28 Richard Sandiford <richard.sandiford@arm.com>
719
720 * aarch64-opc.c (operand_general_constraint_met_p): Check the
721 range of ldst_elemlist operands.
722 (print_register_list): Use PRIi64 to print the index.
723 (aarch64_print_operand): Likewise.
724
5703197e
TS		 7252016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
726
727 * mcore-opc.h: Remove sentinal.
728 * mcore-dis.c (print_insn_mcore): Adjust.
729
ce440d63
GM		 7302016-06-23 Graham Markall <graham.markall@embecosm.com>
731
732 * arc-opc.c: Correct description of availability of NPS400
733 features.
734
6fd3a02d
PB		 7352016-06-22 Peter Bergner <bergner@vnet.ibm.com>
736
737 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
738 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
739 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
740 xor3>: New mnemonics.
741 <setb>: Change to a VX form instruction.
742 (insert_sh6): Add support for rldixor.
743 (extract_sh6): Likewise.
744
6b477896
TS		 7452016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
746
747 * arc-ext.h: Wrap in extern C.
748
bdd582db
GM		 7492016-06-21 Graham Markall <graham.markall@embecosm.com>
750
751 * arc-dis.c (arc_insn_length): Add comment on instruction length.
752 Use same method for determining instruction length on ARC700 and
753 NPS-400.
754 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
755 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
756 with the NPS400 subclass.
757 * arc-opc.c: Likewise.
758
96074adc
JM		 7592016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
760
761 * sparc-opc.c (rdasr): New macro.
762 (wrasr): Likewise.
763 (rdpr): Likewise.
764 (wrpr): Likewise.
765 (rdhpr): Likewise.
766 (wrhpr): Likewise.
767 (sparc_opcodes): Use the macros above to fix and expand the
768 definition of read/write instructions from/to
769 asr/privileged/hyperprivileged instructions.
770 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
771 %hva_mask_nz. Prefer softint_set and softint_clear over
772 set_softint and clear_softint.
773 (print_insn_sparc): Support %ver in Rd.
774
7a10c22f
JM		 7752016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
776
777 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
778 architecture according to the hardware capabilities they require.
779
4f26fb3a
JM		 7802016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
781
782 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
783 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
784 bfd_mach_sparc_v9{c,d,e,v,m}.
785 * sparc-opc.c (MASK_V9C): Define.
786 (MASK_V9D): Likewise.
787 (MASK_V9E): Likewise.
788 (MASK_V9V): Likewise.
789 (MASK_V9M): Likewise.
790 (v6): Add MASK_V9{C,D,E,V,M}.
791 (v6notlet): Likewise.
792 (v7): Likewise.
793 (v8): Likewise.
794 (v9): Likewise.
795 (v9andleon): Likewise.
796 (v9a): Likewise.
797 (v9b): Likewise.
798 (v9c): Define.
799 (v9d): Likewise.
800 (v9e): Likewise.
801 (v9v): Likewise.
802 (v9m): Likewise.
803 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
804
3ee6e4fb
NC		 8052016-06-15 Nick Clifton <nickc@redhat.com>
806
807 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
808 constants to match expected behaviour.
809 (nds32_parse_opcode): Likewise. Also for whitespace.
810
02f3be19
AB		 8112016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
812
813 * arc-opc.c (extract_rhv1): Extract value from insn.
814
6f9f37ed 8152016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 816
817 * arc-nps400-tbl.h: Add ldbit instruction.
818 * arc-opc.c: Add flag classes required for ldbit.
819
6f9f37ed 8202016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 821
822 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
823 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
824 support the above instructions.
825
6f9f37ed 8262016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 827
828 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
829 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
830 csma, cbba, zncv, and hofs.
831 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
832 support the above instructions.
833
8342016-06-06 Graham Markall <graham.markall@embecosm.com>
835
836 * arc-nps400-tbl.h: Add andab and orab instructions.
837
8382016-06-06 Graham Markall <graham.markall@embecosm.com>
839
840 * arc-nps400-tbl.h: Add addl-like instructions.
841
8422016-06-06 Graham Markall <graham.markall@embecosm.com>
843
844 * arc-nps400-tbl.h: Add mxb and imxb instructions.
845
8462016-06-06 Graham Markall <graham.markall@embecosm.com>
847
848 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
849 instructions.
850
b2cc3f6f
AK		 8512016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
852
853 * s390-dis.c (option_use_insn_len_bits_p): New file scope
854 variable.
855 (init_disasm): Handle new command line option "insnlength".
856 (print_s390_disassembler_options): Mention new option in help
857 output.
858 (print_insn_s390): Use the encoded insn length when dumping
859 unknown instructions.
860
1857fe72
DC		 8612016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
862
863 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
864 to the address and set as symbol address for LDS/ STS immediate operands.
865
14b57c7c
AM		 8662016-06-07 Alan Modra <amodra@gmail.com>
867
868 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
869 cpu for "vle" to e500.
870 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
871 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
872 (PPCNONE): Delete, substitute throughout.
873 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
874 except for major opcode 4 and 31.
875 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
876
4d1464f2
MW		 8772016-06-07 Matthew Wahab <matthew.wahab@arm.com>
878
879 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
880 ARM_EXT_RAS in relevant entries.
881
026122a6
PB		 8822016-06-03 Peter Bergner <bergner@vnet.ibm.com>
883
884 PR binutils/20196
885 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
886 opcodes for E6500.
887
07f5af7d
L		 8882016-06-03 H.J. Lu <hongjiu.lu@intel.com>
889
890 PR binutis/18386
891 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
892 (indir_v_mode): New.
893 Add comments for '&'.
894 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
895 (putop): Handle '&'.
896 (intel_operand_size): Handle indir_v_mode.
897 (OP_E_register): Likewise.
898 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
899 64-bit indirect call/jmp for AMD64.
900 * i386-tbl.h: Regenerated
901
4eb6f892
AB		 9022016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
903
904 * arc-dis.c (struct arc_operand_iterator): New structure.
905 (find_format_from_table): All the old content from find_format,
906 with some minor adjustments, and parameter renaming.
907 (find_format_long_instructions): New function.
908 (find_format): Rewritten.
909 (arc_insn_length): Add LSB parameter.
910 (extract_operand_value): New function.
911 (operand_iterator_next): New function.
912 (print_insn_arc): Use new functions to find opcode, and iterator
913 over operands.
914 * arc-opc.c (insert_nps_3bit_dst_short): New function.
915 (extract_nps_3bit_dst_short): New function.
916 (insert_nps_3bit_src2_short): New function.
917 (extract_nps_3bit_src2_short): New function.
918 (insert_nps_bitop1_size): New function.
919 (extract_nps_bitop1_size): New function.
920 (insert_nps_bitop2_size): New function.
921 (extract_nps_bitop2_size): New function.
922 (insert_nps_bitop_mod4_msb): New function.
923 (extract_nps_bitop_mod4_msb): New function.
924 (insert_nps_bitop_mod4_lsb): New function.
925 (extract_nps_bitop_mod4_lsb): New function.
926 (insert_nps_bitop_dst_pos3_pos4): New function.
927 (extract_nps_bitop_dst_pos3_pos4): New function.
928 (insert_nps_bitop_ins_ext): New function.
929 (extract_nps_bitop_ins_ext): New function.
930 (arc_operands): Add new operands.
931 (arc_long_opcodes): New global array.
932 (arc_num_long_opcodes): New global.
933 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
934
1fe0971e
TS		 9352016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
936
937 * nds32-asm.h: Add extern "C".
938 * sh-opc.h: Likewise.
939
315f180f
GM		 9402016-06-01 Graham Markall <graham.markall@embecosm.com>
941
942 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
943 0,b,limm to the rflt instruction.
944
a2b5fccc
TS		 9452016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
946
947 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
948 constant.
949
0cbd0046
L		 9502016-05-29 H.J. Lu <hongjiu.lu@intel.com>
951
952 PR gas/20145
953 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
954 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
955 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
956 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
957 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
958 * i386-init.h: Regenerated.
959
1848e567
L		 9602016-05-27 H.J. Lu <hongjiu.lu@intel.com>
961
962 PR gas/20145
963 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
964 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
965 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
966 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
967 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
968 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
969 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
970 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
971 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
972 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
973 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
974 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
975 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
976 CpuRegMask for AVX512.
977 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
978 and CpuRegMask.
979 (set_bitfield_from_cpu_flag_init): New function.
980 (set_bitfield): Remove const on f. Call
981 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
982 * i386-opc.h (CpuRegMMX): New.
983 (CpuRegXMM): Likewise.
984 (CpuRegYMM): Likewise.
985 (CpuRegZMM): Likewise.
986 (CpuRegMask): Likewise.
987 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
988 and cpuregmask.
989 * i386-init.h: Regenerated.
990 * i386-tbl.h: Likewise.
991
e92bae62
L		 9922016-05-27 H.J. Lu <hongjiu.lu@intel.com>
993
994 PR gas/20154
995 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
996 (opcode_modifiers): Add AMD64 and Intel64.
997 (main): Properly verify CpuMax.
998 * i386-opc.h (CpuAMD64): Removed.
999 (CpuIntel64): Likewise.
1000 (CpuMax): Set to CpuNo64.
1001 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1002 (AMD64): New.
1003 (Intel64): Likewise.
1004 (i386_opcode_modifier): Add amd64 and intel64.
1005 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1006 on call and jmp.
1007 * i386-init.h: Regenerated.
1008 * i386-tbl.h: Likewise.
1009
e89c5eaa
L		 10102016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1011
1012 PR gas/20154
1013 * i386-gen.c (main): Fail if CpuMax is incorrect.
1014 * i386-opc.h (CpuMax): Set to CpuIntel64.
1015 * i386-tbl.h: Regenerated.
1016
77d66e7b
NC		 10172016-05-27 Nick Clifton <nickc@redhat.com>
1018
1019 PR target/20150
1020 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1021 (msp430dis_opcode_unsigned): New function.
1022 (msp430dis_opcode_signed): New function.
1023 (msp430_singleoperand): Use the new opcode reading functions.
1024 Only disassenmble bytes if they were successfully read.
1025 (msp430_doubleoperand): Likewise.
1026 (msp430_branchinstr): Likewise.
1027 (msp430x_callx_instr): Likewise.
1028 (print_insn_msp430): Check that it is safe to read bytes before
1029 attempting disassembly. Use the new opcode reading functions.
1030
19dfcc89
PB		 10312016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1032
1033 * ppc-opc.c (CY): New define. Document it.
1034 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1035
f3ad7637
L		 10362016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1037
1038 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1039 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1040 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1041 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1042 CPU_ANY_AVX_FLAGS.
1043 * i386-init.h: Regenerated.
1044
f1360d58
L		 10452016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1046
1047 PR gas/20141
1048 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1049 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1050 * i386-init.h: Regenerated.
1051
293f5f65
L		 10522016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1053
1054 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1055 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1056 * i386-init.h: Regenerated.
1057
d9eca1df
CZ		 10582016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1059
1060 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1061 information.
1062 (print_insn_arc): Set insn_type information.
1063 * arc-opc.c (C_CC): Add F_CLASS_COND.
1064 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1065 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1066 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1067 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1068 (brne, brne_s, jeq_s, jne_s): Likewise.
1069
87789e08
CZ		 10702016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1071
1072 * arc-tbl.h (neg): New instruction variant.
1073
c810e0b8
CZ		 10742016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1075
1076 * arc-dis.c (find_format, find_format, get_auxreg)
1077 (print_insn_arc): Changed.
1078 * arc-ext.h (INSERT_XOP): Likewise.
1079
3d207518
TS		 10802016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1081
1082 * tic54x-dis.c (sprint_mmr): Adjust.
1083 * tic54x-opc.c: Likewise.
1084
514e58b7
AM		 10852016-05-19 Alan Modra <amodra@gmail.com>
1086
1087 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1088
e43de63c
AM		 10892016-05-19 Alan Modra <amodra@gmail.com>
1090
1091 * ppc-opc.c: Formatting.
1092 (NSISIGNOPT): Define.
1093 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1094
1401d2fe
MR		 10952016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1096
1097 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1098 replacing references to `micromips_ase' throughout.
1099 (_print_insn_mips): Don't use file-level microMIPS annotation to
1100 determine the disassembly mode with the symbol table.
1101
1178da44
PB		 11022016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1103
1104 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1105
8f4f9071
MF		 11062016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1107
1108 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1109 mips64r6.
1110 * mips-opc.c (D34): New macro.
1111 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1112
8bc52696
AF		 11132016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1114
1115 * i386-dis.c (prefix_table): Add RDPID instruction.
1116 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1117 (cpu_flags): Add RDPID bitfield.
1118 * i386-opc.h (enum): Add RDPID element.
1119 (i386_cpu_flags): Add RDPID field.
1120 * i386-opc.tbl: Add RDPID instruction.
1121 * i386-init.h: Regenerate.
1122 * i386-tbl.h: Regenerate.
1123
39d911fc
TP		 11242016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1125
1126 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1127 branch type of a symbol.
1128 (print_insn): Likewise.
1129
16a1fa25
TP		 11302016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1131
1132 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1133 Mainline Security Extensions instructions.
1134 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1135 Extensions instructions.
1136 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1137 instructions.
1138 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1139 special registers.
1140
d751b79e
JM		 11412016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1142
1143 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1144
945e0f82
CZ		 11452016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1146
1147 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1148 (arcExtMap_genOpcode): Likewise.
1149 * arc-opc.c (arg_32bit_rc): Define new variable.
1150 (arg_32bit_u6): Likewise.
1151 (arg_32bit_limm): Likewise.
1152
20f55f38
SN		 11532016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1154
1155 * aarch64-gen.c (VERIFIER): Define.
1156 * aarch64-opc.c (VERIFIER): Define.
1157 (verify_ldpsw): Use static linkage.
1158 * aarch64-opc.h (verify_ldpsw): Remove.
1159 * aarch64-tbl.h: Use VERIFIER for verifiers.
1160
4bd13cde
NC		 11612016-04-28 Nick Clifton <nickc@redhat.com>
1162
1163 PR target/19722
1164 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1165 * aarch64-opc.c (verify_ldpsw): New function.
1166 * aarch64-opc.h (verify_ldpsw): New prototype.
1167 * aarch64-tbl.h: Add initialiser for verifier field.
1168 (LDPSW): Set verifier to verify_ldpsw.
1169
c0f92bf9
L		 11702016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1171
1172 PR binutils/19983
1173 PR binutils/19984
1174 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1175 smaller than address size.
1176
e6c7cdec
TS		 11772016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1178
1179 * alpha-dis.c: Regenerate.
1180 * crx-dis.c: Likewise.
1181 * disassemble.c: Likewise.
1182 * epiphany-opc.c: Likewise.
1183 * fr30-opc.c: Likewise.
1184 * frv-opc.c: Likewise.
1185 * ip2k-opc.c: Likewise.
1186 * iq2000-opc.c: Likewise.
1187 * lm32-opc.c: Likewise.
1188 * lm32-opinst.c: Likewise.
1189 * m32c-opc.c: Likewise.
1190 * m32r-opc.c: Likewise.
1191 * m32r-opinst.c: Likewise.
1192 * mep-opc.c: Likewise.
1193 * mt-opc.c: Likewise.
1194 * or1k-opc.c: Likewise.
1195 * or1k-opinst.c: Likewise.
1196 * tic80-opc.c: Likewise.
1197 * xc16x-opc.c: Likewise.
1198 * xstormy16-opc.c: Likewise.
1199
537aefaf
AB		 12002016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1201
1202 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1203 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1204 calcsd, and calcxd instructions.
1205 * arc-opc.c (insert_nps_bitop_size): Delete.
1206 (extract_nps_bitop_size): Delete.
1207 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1208 (extract_nps_qcmp_m3): Define.
1209 (extract_nps_qcmp_m2): Define.
1210 (extract_nps_qcmp_m1): Define.
1211 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1212 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1213 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1214 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1215 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1216 NPS_QCMP_M3.
1217
c8f785f2
AB		 12182016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1219
1220 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1221
6fd8e7c2
L		 12222016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1223
1224 * Makefile.in: Regenerated with automake 1.11.6.
1225 * aclocal.m4: Likewise.
1226
4b0c052e
AB		 12272016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1228
1229 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1230 instructions.
1231 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1232 (extract_nps_cmem_uimm16): New function.
1233 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1234
cb040366
AB		 12352016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1236
1237 * arc-dis.c (arc_insn_length): New function.
1238 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1239 (find_format): Change insnLen parameter to unsigned.
1240
accc0180
NC		 12412016-04-13 Nick Clifton <nickc@redhat.com>
1242
1243 PR target/19937
1244 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1245 the LD.B and LD.BU instructions.
1246
f36e33da
CZ		 12472016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1248
1249 * arc-dis.c (find_format): Check for extension flags.
1250 (print_flags): New function.
1251 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1252 .extAuxRegister.
1253 * arc-ext.c (arcExtMap_coreRegName): Use
1254 LAST_EXTENSION_CORE_REGISTER.
1255 (arcExtMap_coreReadWrite): Likewise.
1256 (dump_ARC_extmap): Update printing.
1257 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1258 (arc_aux_regs): Add cpu field.
1259 * arc-regs.h: Add cpu field, lower case name aux registers.
1260
1c2e355e
CZ		 12612016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1262
1263 * arc-tbl.h: Add rtsc, sleep with no arguments.
1264
b99747ae
CZ		 12652016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1266
1267 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1268 Initialize.
1269 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1270 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1271 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1272 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1273 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1274 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1275 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1276 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1277 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1278 (arc_opcode arc_opcodes): Null terminate the array.
1279 (arc_num_opcodes): Remove.
1280 * arc-ext.h (INSERT_XOP): Define.
1281 (extInstruction_t): Likewise.
1282 (arcExtMap_instName): Delete.
1283 (arcExtMap_insn): New function.
1284 (arcExtMap_genOpcode): Likewise.
1285 * arc-ext.c (ExtInstruction): Remove.
1286 (create_map): Zero initialize instruction fields.
1287 (arcExtMap_instName): Remove.
1288 (arcExtMap_insn): New function.
1289 (dump_ARC_extmap): More info while debuging.
1290 (arcExtMap_genOpcode): New function.
1291 * arc-dis.c (find_format): New function.
1292 (print_insn_arc): Use find_format.
1293 (arc_get_disassembler): Enable dump_ARC_extmap only when
1294 debugging.
1295
92708cec
MR		 12962016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1297
1298 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1299 instruction bits out.
1300
a42a4f84
AB		 13012016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1302
1303 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1304 * arc-opc.c (arc_flag_operands): Add new flags.
1305 (arc_flag_classes): Add new classes.
1306
1328504b
AB		 13072016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1308
1309 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1310
820f03ff
AB		 13112016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1312
1313 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1314 encode1, rflt, crc16, and crc32 instructions.
1315 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1316 (arc_flag_classes): Add C_NPS_R.
1317 (insert_nps_bitop_size_2b): New function.
1318 (extract_nps_bitop_size_2b): Likewise.
1319 (insert_nps_bitop_uimm8): Likewise.
1320 (extract_nps_bitop_uimm8): Likewise.
1321 (arc_operands): Add new operand entries.
1322
8ddf6b2a
CZ		 13232016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1324
b99747ae
CZ		 1325 * arc-regs.h: Add a new subclass field. Add double assist
1326 accumulator register values.
1327 * arc-tbl.h: Use DPA subclass to mark the double assist
1328 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1329 * arc-opc.c (RSP): Define instead of SP.
1330 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1331
589a7d88
JW		 13322016-04-05 Jiong Wang <jiong.wang@arm.com>
1333
1334 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1335
0a191de9 13362016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1337
1338 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1339 NPS_R_SRC1.
1340
0a106562
AB		 13412016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1342
1343 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1344 issues. No functional changes.
1345
bd05ac5f
CZ		 13462016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1347
b99747ae
CZ		 1348 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1349 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1350 (RTT): Remove duplicate.
1351 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1352 (PCT_CONFIG*): Remove.
1353 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1354
9885948f
CZ		 13552016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1356
b99747ae 1357 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1358
f2dd8838
CZ		 13592016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1360
b99747ae
CZ		 1361 * arc-tbl.h (invld07): Remove.
1362 * arc-ext-tbl.h: New file.
1363 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1364 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1365
0d2f91fe
JK		 13662016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1367
1368 Fix -Wstack-usage warnings.
1369 * aarch64-dis.c (print_operands): Substitute size.
1370 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1371
a6b71f42
JM		 13722016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1373
1374 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1375 to get a proper diagnostic when an invalid ASR register is used.
1376
9780e045
NC		 13772016-03-22 Nick Clifton <nickc@redhat.com>
1378
1379 * configure: Regenerate.
1380
e23e8ebe
AB		 13812016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1382
1383 * arc-nps400-tbl.h: New file.
1384 * arc-opc.c: Add top level comment.
1385 (insert_nps_3bit_dst): New function.
1386 (extract_nps_3bit_dst): New function.
1387 (insert_nps_3bit_src2): New function.
1388 (extract_nps_3bit_src2): New function.
1389 (insert_nps_bitop_size): New function.
1390 (extract_nps_bitop_size): New function.
1391 (arc_flag_operands): Add nps400 entries.
1392 (arc_flag_classes): Add nps400 entries.
1393 (arc_operands): Add nps400 entries.
1394 (arc_opcodes): Add nps400 include.
1395
1ae8ab47
AB		 13962016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1397
1398 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1399 the new class enum values.
1400
8699fc3e
AB		 14012016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1402
1403 * arc-dis.c (print_insn_arc): Handle nps400.
1404
24740d83
AB		 14052016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1406
1407 * arc-opc.c (BASE): Delete.
1408
8678914f
NC		 14092016-03-18 Nick Clifton <nickc@redhat.com>
1410
1411 PR target/19721
1412 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1413 of MOV insn that aliases an ORR insn.
1414
cc933301
JW		 14152016-03-16 Jiong Wang <jiong.wang@arm.com>
1416
1417 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1418
f86f5863
TS		 14192016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1420
1421 * mcore-opc.h: Add const qualifiers.
1422 * microblaze-opc.h (struct op_code_struct): Likewise.
1423 * sh-opc.h: Likewise.
1424 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1425 (tic4x_print_op): Likewise.
1426
62de1c63
AM		 14272016-03-02 Alan Modra <amodra@gmail.com>
1428
d11698cd 1429 * or1k-desc.h: Regenerate.
62de1c63 1430 * fr30-ibld.c: Regenerate.
c697cf0b 1431 * rl78-decode.c: Regenerate.
62de1c63 1432
020efce5
NC		 14332016-03-01 Nick Clifton <nickc@redhat.com>
1434
1435 PR target/19747
1436 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1437
b0c11777
RL		 14382016-02-24 Renlin Li <renlin.li@arm.com>
1439
1440 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1441 (print_insn_coprocessor): Support fp16 instructions.
1442
3e309328
RL		 14432016-02-24 Renlin Li <renlin.li@arm.com>
1444
1445 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1446 vminnm, vrint(mpna).
1447
8afc7bea
RL		 14482016-02-24 Renlin Li <renlin.li@arm.com>
1449
1450 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1451 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1452
4fd7268a
L		 14532016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1454
1455 * i386-dis.c (print_insn): Parenthesize expression to prevent
1456 truncated addresses.
1457 (OP_J): Likewise.
1458
4670103e
CZ		 14592016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1460 Janek van Oirschot <jvanoirs@synopsys.com>
1461
b99747ae
CZ		 1462 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1463 variable.
4670103e 1464
c1d9289f
NC		 14652016-02-04 Nick Clifton <nickc@redhat.com>
1466
1467 PR target/19561
1468 * msp430-dis.c (print_insn_msp430): Add a special case for
1469 decoding an RRC instruction with the ZC bit set in the extension
1470 word.
1471
a143b004
AB		 14722016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1473
1474 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1475 * epiphany-ibld.c: Regenerate.
1476 * fr30-ibld.c: Regenerate.
1477 * frv-ibld.c: Regenerate.
1478 * ip2k-ibld.c: Regenerate.
1479 * iq2000-ibld.c: Regenerate.
1480 * lm32-ibld.c: Regenerate.
1481 * m32c-ibld.c: Regenerate.
1482 * m32r-ibld.c: Regenerate.
1483 * mep-ibld.c: Regenerate.
1484 * mt-ibld.c: Regenerate.
1485 * or1k-ibld.c: Regenerate.
1486 * xc16x-ibld.c: Regenerate.
1487 * xstormy16-ibld.c: Regenerate.
1488
b89807c6
AB		 14892016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1490
1491 * epiphany-dis.c: Regenerated from latest cpu files.
1492
d8c823c8
MM		 14932016-02-01 Michael McConville <mmcco@mykolab.com>
1494
1495 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1496 test bit.
1497
5bc5ae88
RL		 14982016-01-25 Renlin Li <renlin.li@arm.com>
1499
1500 * arm-dis.c (mapping_symbol_for_insn): New function.
1501 (find_ifthen_state): Call mapping_symbol_for_insn().
1502
0bff6e2d
MW		 15032016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1504
1505 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1506 of MSR UAO immediate operand.
1507
100b4f2e
MR		 15082016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1509
1510 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1511 instruction support.
1512
5c14705f
AM		 15132016-01-17 Alan Modra <amodra@gmail.com>
1514
1515 * configure: Regenerate.
1516
4d82fe66
NC		 15172016-01-14 Nick Clifton <nickc@redhat.com>
1518
1519 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1520 instructions that can support stack pointer operations.
1521 * rl78-decode.c: Regenerate.
1522 * rl78-dis.c: Fix display of stack pointer in MOVW based
1523 instructions.
1524
651657fa
MW		 15252016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1526
1527 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1528 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1529 erxtatus_el1 and erxaddr_el1.
1530
105bde57
MW		 15312016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1532
1533 * arm-dis.c (arm_opcodes): Add "esb".
1534 (thumb_opcodes): Likewise.
1535
afa8d405
PB		 15362016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1537
1538 * ppc-opc.c <xscmpnedp>: Delete.
1539 <xvcmpnedp>: Likewise.
1540 <xvcmpnedp.>: Likewise.
1541 <xvcmpnesp>: Likewise.
1542 <xvcmpnesp.>: Likewise.
1543
83c3256e
AS		 15442016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1545
1546 PR gas/13050
1547 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1548 addition to ISA_A.
1549
6f2750fe
AM		 15502016-01-01 Alan Modra <amodra@gmail.com>
1551
1552 Update year range in copyright notice of all files.
1553
3499769a
AM		 1554For older changes see ChangeLog-2015
1555\f
1556Copyright (C) 2016 Free Software Foundation, Inc.
1557
1558Copying and distribution of this file, with or without modification,
1559are permitted in any medium without royalty provided the copyright
1560notice and this notice are preserved.
1561
1562Local Variables:
1563mode: change-log
1564left-margin: 8
1565fill-column: 74
1566version-control: never
1567End:
GDB Binutils - Deliverables
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