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* elf64-ppc.c (struct ppc64_elf_obj_tdata): Replace opd_relocs
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7e8b059b
L		 12013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
2 Kirill Yukhin <kirill.yukhin@intel.com>
3 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
4
5 * i386-dis.c (BND_Fixup): New.
6 (Ebnd): New.
7 (Ev_bnd): New.
8 (Gbnd): New.
9 (BND): New.
10 (v_bnd_mode): New.
11 (bnd_mode): New.
12 (MOD enum): Add new entries.
13 (PREFIX enum): Likewise.
14 (dis tables): Replace XX with BND for near branch and call
15 instructions.
16 (prefix_table): Add new entries.
17 (mod_table): Likewise.
18 (names_bnd): New.
19 (intel_names_bnd): New.
20 (att_names_bnd): New.
21 (BND_PREFIX): New.
22 (prefix_name): Handle BND_PREFIX.
23 (print_insn): Initialize names_bnd.
24 (intel_operand_size): Handle new modes.
25 (OP_E_register): Likewise.
26 (OP_E_memory): Likewise.
27 (OP_G): Likewise.
28 * i386-gen.c (cpu_flag_init): Add CpuMPX.
29 (cpu_flags): Add CpuMPX.
30 (operand_type_init): Add RegBND.
31 (opcode_modifiers): Add BNDPrefixOk.
32 (operand_types): Add RegBND.
33 * i386-init.h: Regenerate.
34 * i386-opc.h (CpuMPX): New.
35 (CpuUnused): Comment out.
36 (i386_cpu_flags): Add cpumpx.
37 (BNDPrefixOk): New.
38 (i386_opcode_modifier): Add bndprefixok.
39 (RegBND): New.
40 (i386_operand_type): Add regbnd.
41 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
42 Add MPX instructions and bnd prefix.
43 * i386-reg.tbl: Add bnd0-bnd3 registers.
44 * i386-tbl.h: Regenerate.
45
b56e23fb
RS		 462013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
47
48 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
49 ATTRIBUTE_UNUSED.
50
e7ae278d
RS		 512013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
52
53 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
54 special rules.
55 * Makefile.in: Regenerate.
56 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
57 all fields. Reformat.
58
c3c07478
RS		 592013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
60
61 * mips16-opc.c: Include mips-formats.h.
62 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
63 static arrays.
64 (decode_mips16_operand): New function.
65 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
66 (print_insn_arg): Handle OP_ENTRY_EXIT list.
67 Abort for OP_SAVE_RESTORE_LIST.
68 (print_mips16_insn_arg): Change interface. Use mips_operand
69 structures. Delete GET_OP_S. Move GET_OP definition to...
70 (print_insn_mips16): ...here. Call init_print_arg_state.
71 Update the call to print_mips16_insn_arg.
72
ab902481
RS		 732013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
74
75 * mips-formats.h: New file.
76 * mips-opc.c: Include mips-formats.h.
77 (reg_0_map): New static array.
78 (decode_mips_operand): New function.
79 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
80 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
81 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
82 (int_c_map): New static arrays.
83 (decode_micromips_operand): New function.
84 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
85 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
86 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
87 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
88 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
89 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
90 (micromips_imm_b_map, micromips_imm_c_map): Delete.
91 (print_reg): New function.
92 (mips_print_arg_state): New structure.
93 (init_print_arg_state, print_insn_arg): New functions.
94 (print_insn_args): Change interface and use mips_operand structures.
95 Delete GET_OP_S. Move GET_OP definition to...
96 (print_insn_mips): ...here. Update the call to print_insn_args.
97 (print_insn_micromips): Use print_insn_args.
98
cc537e56
RS		 992013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
100
101 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
102 in macros.
103
7a5f87ce
RS		 1042013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
105
106 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
107 ADDA.S, MULA.S and SUBA.S.
108
41741fa4
L		 1092013-07-08 H.J. Lu <hongjiu.lu@intel.com>
110
111 PR gas/13572
112 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
113 * i386-tbl.h: Regenerated.
114
f2ae14a1
RS		 1152013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
116
117 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
118 and SD A(B) macros up.
119 * micromips-opc.c (micromips_opcodes): Likewise.
120
04c9d415
RS		 1212013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
122
123 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
124 instructions.
125
5c324c16
RS		 1262013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
127
128 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
129 MDMX-like instructions.
130 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
131 printing "Q" operands for INSN_5400 instructions.
132
23e69e47
RS		 1332013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
134
135 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
136 "+S" for "cins".
137 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
138 Combine cases.
139
27c5c572
RS		 1402013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
141
142 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
143 "jalx".
144 * mips16-opc.c (mips16_opcodes): Likewise.
145 * micromips-opc.c (micromips_opcodes): Likewise.
146 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
147 (print_insn_mips16): Handle "+i".
148 (print_insn_micromips): Likewise. Conditionally preserve the
149 ISA bit for "a" but not for "+i".
150
e76ff5ab
RS		 1512013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
152
153 * micromips-opc.c (WR_mhi): Rename to..
154 (WR_mh): ...this.
155 (micromips_opcodes): Update "movep" entry accordingly. Replace
156 "mh,mi" with "mh".
157 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
158 (micromips_to_32_reg_h_map1): ...this.
159 (micromips_to_32_reg_i_map): Rename to...
160 (micromips_to_32_reg_h_map2): ...this.
161 (print_micromips_insn): Remove "mi" case. Print both registers
162 in the pair for "mh".
163
fa7616a4
RS		 1642013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
165
166 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
167 * micromips-opc.c (micromips_opcodes): Likewise.
168 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
169 and "+T" handling. Check for a "0" suffix when deciding whether to
170 use coprocessor 0 names. In that case, also check for ",H" selectors.
171
fb798c50
AK		 1722013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
173
174 * s390-opc.c (J12_12, J24_24): New macros.
175 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
176 (MASK_MII_UPI): Rename to MASK_MII_UPP.
177 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
178
58ae08f2
AM		 1792013-07-04 Alan Modra <amodra@gmail.com>
180
181 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
182
b5e04c2b
NC		 1832013-06-26 Nick Clifton <nickc@redhat.com>
184
185 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
186 field when checking for type 2 nop.
187 * rx-decode.c: Regenerate.
188
833794fc
MR		 1892013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
190
191 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
192 and "movep" macros.
193
1bbce132
MR		 1942013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
195
196 * mips-dis.c (is_mips16_plt_tail): New function.
197 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
198 word.
199 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
200
34c911a4
NC		 2012013-06-21 DJ Delorie <dj@redhat.com>
202
203 * msp430-decode.opc: New.
204 * msp430-decode.c: New/generated.
205 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
206 (MAINTAINER_CLEANFILES): Likewise.
207 Add rule to build msp430-decode.c frommsp430decode.opc
208 using the opc2c program.
209 * Makefile.in: Regenerate.
210 * configure.in: Add msp430-decode.lo to msp430 architecture files.
211 * configure: Regenerate.
212
b9eead84
YZ		 2132013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
214
215 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
216 (SYMTAB_AVAILABLE): Removed.
217 (#include "elf/aarch64.h): Ditto.
218
7f3c4072
CM		 2192013-06-17 Catherine Moore <clm@codesourcery.com>
220 Maciej W. Rozycki <macro@codesourcery.com>
221 Chao-Ying Fu <fu@mips.com>
222
223 * micromips-opc.c (EVA): Define.
224 (TLBINV): Define.
225 (micromips_opcodes): Add EVA opcodes.
226 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
227 (print_insn_args): Handle EVA offsets.
228 (print_insn_micromips): Likewise.
229 * mips-opc.c (EVA): Define.
230 (TLBINV): Define.
231 (mips_builtin_opcodes): Add EVA opcodes.
232
de40ceb6
AM		 2332013-06-17 Alan Modra <amodra@gmail.com>
234
235 * Makefile.am (mips-opc.lo): Add rules to create automatic
236 dependency files. Pass archdefs.
237 (micromips-opc.lo, mips16-opc.lo): Likewise.
238 * Makefile.in: Regenerate.
239
3531d549
DD		 2402013-06-14 DJ Delorie <dj@redhat.com>
241
242 * rx-decode.opc (rx_decode_opcode): Bit operations on
243 registers are 32-bit operations, not 8-bit operations.
244 * rx-decode.c: Regenerate.
245
ba92f7fb
CF		 2462013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
247
248 * micromips-opc.c (IVIRT): New define.
249 (IVIRT64): New define.
250 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
251 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
252
253 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
254 dmtgc0 to print cp0 names.
255
9daf7bab
SL		 2562013-06-09 Sandra Loosemore <sandra@codesourcery.com>
257
258 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
259 argument.
260
d301a56b
RS		 2612013-06-08 Catherine Moore <clm@codesourcery.com>
262 Richard Sandiford <rdsandiford@googlemail.com>
263
264 * micromips-opc.c (D32, D33, MC): Update definitions.
265 (micromips_opcodes): Initialize ase field.
266 * mips-dis.c (mips_arch_choice): Add ase field.
267 (mips_arch_choices): Initialize ase field.
268 (set_default_mips_dis_options): Declare and setup mips_ase.
269 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
270 MT32, MC): Update definitions.
271 (mips_builtin_opcodes): Initialize ase field.
272
a3dcb6c5
RS		 2732013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
274
275 * s390-opc.txt (flogr): Require a register pair destination.
276
6cf1d90c
AK		 2772013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
278
279 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
280 instruction format.
281
c77c0862
RS		 2822013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
283
284 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
285
c0637f3a
PB		 2862013-05-20 Peter Bergner <bergner@vnet.ibm.com>
287
288 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
289 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
290 XLS_MASK, PPCVSX2): New defines.
291 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
292 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
293 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
294 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
295 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
296 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
297 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
298 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
299 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
300 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
301 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
302 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
303 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
304 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
305 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
306 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
307 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
308 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
309 <lxvx, stxvx>: New extended mnemonics.
310
4934fdaf
AM		 3112013-05-17 Alan Modra <amodra@gmail.com>
312
313 * ia64-raw.tbl: Replace non-ASCII char.
314 * ia64-waw.tbl: Likewise.
315 * ia64-asmtab.c: Regenerate.
316
6091d651
SE		 3172013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
318
319 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
320 * i386-init.h: Regenerated.
321
d2865ed3
YZ		 3222013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
323
324 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
325 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
326 check from [0, 255] to [-128, 255].
327
b015e599
AP		 3282013-05-09 Andrew Pinski <apinski@cavium.com>
329
330 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
331 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
332 (parse_mips_dis_option): Handle the virt option.
333 (print_insn_args): Handle "+J".
334 (print_mips_disassembler_options): Print out message about virt64.
335 * mips-opc.c (IVIRT): New define.
336 (IVIRT64): New define.
337 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
338 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
339 Move rfe to the bottom as it conflicts with tlbgp.
340
9f0682fe
AM		 3412013-05-09 Alan Modra <amodra@gmail.com>
342
343 * ppc-opc.c (extract_vlesi): Properly sign extend.
344 (extract_vlensi): Likewise. Comment reason for setting invalid.
345
13761a11
NC		 3462013-05-02 Nick Clifton <nickc@redhat.com>
347
348 * msp430-dis.c: Add support for MSP430X instructions.
349
e3031850
SL		 3502013-04-24 Sandra Loosemore <sandra@codesourcery.com>
351
352 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
353 to "eccinj".
354
17310e56
NC		 3552013-04-17 Wei-chen Wang <cole945@gmail.com>
356
357 PR binutils/15369
358 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
359 of CGEN_CPU_ENDIAN.
360 (hash_insns_list): Likewise.
361
731df338
JK		 3622013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
363
364 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
365 warning workaround.
366
5f77db52
JB		 3672013-04-08 Jan Beulich <jbeulich@suse.com>
368
369 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
370 * i386-tbl.h: Re-generate.
371
0afd1215
DM		 3722013-04-06 David S. Miller <davem@davemloft.net>
373
374 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
375 of an opcode, prefer the one with F_PREFERRED set.
376 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
377 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
378 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
379 mark existing mnenomics as aliases. Add "cc" suffix to edge
380 instructions generating condition codes, mark existing mnenomics
381 as aliases. Add "fp" prefix to VIS compare instructions, mark
382 existing mnenomics as aliases.
383
41702d50
NC		 3842013-04-03 Nick Clifton <nickc@redhat.com>
385
386 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
387 destination address by subtracting the operand from the current
388 address.
389 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
390 a positive value in the insn.
391 (extract_u16_loop): Do not negate the returned value.
392 (D16_LOOP): Add V850_INVERSE_PCREL flag.
393
394 (ceilf.sw): Remove duplicate entry.
395 (cvtf.hs): New entry.
396 (cvtf.sh): Likewise.
397 (fmaf.s): Likewise.
398 (fmsf.s): Likewise.
399 (fnmaf.s): Likewise.
400 (fnmsf.s): Likewise.
401 (maddf.s): Restrict to E3V5 architectures.
402 (msubf.s): Likewise.
403 (nmaddf.s): Likewise.
404 (nmsubf.s): Likewise.
405
55cf16e1
L		 4062013-03-27 H.J. Lu <hongjiu.lu@intel.com>
407
408 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
409 check address mode.
410 (print_insn): Pass sizeflag to get_sib.
411
51dcdd4d
NC		 4122013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
413
414 PR binutils/15068
415 * tic6x-dis.c: Add support for displaying 16-bit insns.
416
795b8e6b
NC		 4172013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
418
419 PR gas/15095
420 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
421 individual msb and lsb halves in src1 & src2 fields. Discard the
422 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
423 follow what Ti SDK does in that case as any value in the src1
424 field yields the same output with SDK disassembler.
425
314d60dd
ME		 4262013-03-12 Michael Eager <eager@eagercon.com>
427
795b8e6b 428 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 429
dad60f8e
SL		 4302013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
431
432 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
433
f5cb796a
SL		 4342013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
435
436 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
437
21fde85c
SL		 4382013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
439
440 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
441
dd5181d5
KT		 4422013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
443
444 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
445 (thumb32_opcodes): Likewise.
446 (print_insn_thumb32): Handle 'S' control char.
447
87a8d6cb
NC		 4482013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
449
450 * lm32-desc.c: Regenerate.
451
99dce992
L		 4522013-03-01 H.J. Lu <hongjiu.lu@intel.com>
453
454 * i386-reg.tbl (riz): Add RegRex64.
455 * i386-tbl.h: Regenerated.
456
e60bb1dd
YZ		 4572013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
458
459 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
460 (aarch64_feature_crc): New static.
461 (CRC): New macro.
462 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
463 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
464 * aarch64-asm-2.c: Re-generate.
465 * aarch64-dis-2.c: Ditto.
466 * aarch64-opc-2.c: Ditto.
467
c7570fcd
AM		 4682013-02-27 Alan Modra <amodra@gmail.com>
469
470 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
471 * rl78-decode.c: Regenerate.
472
151fa98f
NC		 4732013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
474
475 * rl78-decode.opc: Fix encoding of DIVWU insn.
476 * rl78-decode.c: Regenerate.
477
5c111e37
L		 4782013-02-19 H.J. Lu <hongjiu.lu@intel.com>
479
480 PR gas/15159
481 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
482
483 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
484 (cpu_flags): Add CpuSMAP.
485
486 * i386-opc.h (CpuSMAP): New.
487 (i386_cpu_flags): Add cpusmap.
488
489 * i386-opc.tbl: Add clac and stac.
490
491 * i386-init.h: Regenerated.
492 * i386-tbl.h: Likewise.
493
9d1df426
NC		 4942013-02-15 Markos Chandras <markos.chandras@imgtec.com>
495
496 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
497 which also makes the disassembler output be in little
498 endian like it should be.
499
a1ccaec9
YZ		 5002013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
501
502 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
503 fields to NULL.
504 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
505
ef068ef4 5062013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 507
508 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
509 section disassembled.
510
6fe6ded9
RE		 5112013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
512
513 * arm-dis.c: Update strht pattern.
514
0aa27725
RS		 5152013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
516
517 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
518 single-float. Disable ll, lld, sc and scd for EE. Disable the
519 trunc.w.s macro for EE.
520
36591ba1
SL		 5212013-02-06 Sandra Loosemore <sandra@codesourcery.com>
522 Andrew Jenner <andrew@codesourcery.com>
523
524 Based on patches from Altera Corporation.
525
526 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
527 nios2-opc.c.
528 * Makefile.in: Regenerated.
529 * configure.in: Add case for bfd_nios2_arch.
530 * configure: Regenerated.
531 * disassemble.c (ARCH_nios2): Define.
532 (disassembler): Add case for bfd_arch_nios2.
533 * nios2-dis.c: New file.
534 * nios2-opc.c: New file.
535
545093a4
AM		 5362013-02-04 Alan Modra <amodra@gmail.com>
537
538 * po/POTFILES.in: Regenerate.
539 * rl78-decode.c: Regenerate.
540 * rx-decode.c: Regenerate.
541
e30181a5
YZ		 5422013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
543
544 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
545 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
546 * aarch64-asm.c (convert_xtl_to_shll): New function.
547 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
548 calling convert_xtl_to_shll.
549 * aarch64-dis.c (convert_shll_to_xtl): New function.
550 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
551 calling convert_shll_to_xtl.
552 * aarch64-gen.c: Update copyright year.
553 * aarch64-asm-2.c: Re-generate.
554 * aarch64-dis-2.c: Re-generate.
555 * aarch64-opc-2.c: Re-generate.
556
78c8d46c
NC		 5572013-01-24 Nick Clifton <nickc@redhat.com>
558
559 * v850-dis.c: Add support for e3v5 architecture.
560 * v850-opc.c: Likewise.
561
f5555712
YZ		 5622013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
563
564 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
565 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
566 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 567 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 568 alignment check; change to call set_sft_amount_out_of_range_error
569 instead of set_imm_out_of_range_error.
570 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
571 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
572 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
573 SIMD_IMM_SFT.
574
2f81ff92
L		 5752013-01-16 H.J. Lu <hongjiu.lu@intel.com>
576
577 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
578
579 * i386-init.h: Regenerated.
580 * i386-tbl.h: Likewise.
581
dd42f060
NC		 5822013-01-15 Nick Clifton <nickc@redhat.com>
583
584 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
585 values.
586 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
587
a4533ed8
NC		 5882013-01-14 Will Newton <will.newton@imgtec.com>
589
590 * metag-dis.c (REG_WIDTH): Increase to 64.
591
5817ffd1
PB		 5922013-01-10 Peter Bergner <bergner@vnet.ibm.com>
593
594 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
595 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
596 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
597 (SH6): Update.
598 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
599 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
600 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
601 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
602
a3c62988
NC		 6032013-01-10 Will Newton <will.newton@imgtec.com>
604
605 * Makefile.am: Add Meta.
606 * configure.in: Add Meta.
607 * disassemble.c: Add Meta support.
608 * metag-dis.c: New file.
609 * Makefile.in: Regenerate.
610 * configure: Regenerate.
611
73335eae
NC		 6122013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
613
614 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
615 (match_opcode): Rename to cr16_match_opcode.
616
e407c74b
NC		 6172013-01-04 Juergen Urban <JuergenUrban@gmx.de>
618
619 * mips-dis.c: Add names for CP0 registers of r5900.
620 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
621 instructions sq and lq.
622 Add support for MIPS r5900 CPU.
623 Add support for 128 bit MMI (Multimedia Instructions).
624 Add support for EE instructions (Emotion Engine).
625 Disable unsupported floating point instructions (64 bit and
626 undefined compare operations).
627 Enable instructions of MIPS ISA IV which are supported by r5900.
628 Disable 64 bit co processor instructions.
629 Disable 64 bit multiplication and division instructions.
630 Disable instructions for co-processor 2 and 3, because these are
631 not supported (preparation for later VU0 support (Vector Unit)).
632 Disable cvt.w.s because this behaves like trunc.w.s and the
633 correct execution can't be ensured on r5900.
634 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
635 will confuse less developers and compilers.
636
a32c3ff8
NC		 6372013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
638
fb098a1e
YZ		 639 * aarch64-opc.c (aarch64_print_operand): Change to print
640 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
641 in comment.
642 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
643 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
644 OP_MOV_IMM_WIDE.
645
6462013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
647
648 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
649 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 650
62658407
L		 6512013-01-02 H.J. Lu <hongjiu.lu@intel.com>
652
653 * i386-gen.c (process_copyright): Update copyright year to 2013.
654
bab4becb 6552013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 656
bab4becb
NC		 657 * cr16-dis.c (match_opcode,make_instruction): Remove static
658 declaration.
659 (dwordU,wordU): Moved typedefs to opcode/cr16.h
660 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 661
bab4becb 662For older changes see ChangeLog-2012
252b5132 663\f
bab4becb 664Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 665
666Copying and distribution of this file, with or without modification,
667are permitted in any medium without royalty provided the copyright
668notice and this notice are preserved.
669
252b5132 670Local Variables:
2f6d2f85
NC		 671mode: change-log
672left-margin: 8
673fill-column: 74
252b5132
RH		 674version-control: never
675End:
GDB Binutils - Deliverables
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