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Add canonical JALR for RISC-V
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
755c5297
AW		 12016-12-20 Andrew Waterman <andrew@sifive.com>
2
3 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
4 format.
5
2922d21d
AW		 62016-12-20 Andrew Waterman <andrew@sifive.com>
7
8 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
9 XLEN when none is provided.
10
1d65abb5
AW		 112016-12-20 Andrew Waterman <andrew@sifive.com>
12
13 * riscv-opc.c: Formatting fixes.
14
dd1d944e
AM		 152016-12-20 Alan Modra <amodra@gmail.com>
16
17 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
18 * Makefile.in: Regenerate.
19 * po/POTFILES.in: Regenerate.
20
91068ec6
MR		 212016-12-19 Maciej W. Rozycki <macro@imgtec.com>
22
23 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
24 Only examine ELF file structures here.
25
4df995c7
MR		 262016-12-19 Maciej W. Rozycki <macro@imgtec.com>
27
28 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
29 `bfd_mips_elf_get_abiflags' here.
30
db7b55fa
NC		 312016-12-16 Nick Clifton <nickc@redhat.com>
32
33 * arm-dis.c (print_insn_thumb32): Fix compile time warning
34 computing value_in_comment.
35
5e7fc731
MR		 362016-12-14 Maciej W. Rozycki <macro@imgtec.com>
37
38 * mips-dis.c (mips_convert_abiflags_ases): New function.
39 (set_default_mips_dis_options): Also infer ASE flags from ELF
40 file structures.
41
8184783a
MR		 422016-12-14 Maciej W. Rozycki <macro@imgtec.com>
43
44 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
45 header flag interpretation code.
46
353abf7c
MR		 472016-12-14 Maciej W. Rozycki <macro@imgtec.com>
48
49 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
50 `pinfo2' with SP-relative "sd" entries.
51
63e014fc
MR		 522016-12-14 Maciej W. Rozycki <macro@imgtec.com>
53
54 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
55 compact jumps.
56
a6a51754
RL		 572016-12-13 Renlin Li <renlin.li@arm.com>
58
59 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
60 qualifier.
61 (operand_general_constraint_met_p): Remove case for CP_REG.
62 (aarch64_print_operand): Print CRn, CRm operand using imm field.
63 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
64 (QL_SYSL): Likewise.
65 (aarch64_opcode_table): Change CRn, CRm operand class and type.
66 * aarch64-opc-2.c : Regenerate.
67 * aarch64-asm-2.c : Likewise.
68 * aarch64-dis-2.c : Likewise.
69
029e9d52
YQ		 702016-12-12 Yao Qi <yao.qi@linaro.org>
71
72 * rx-dis.c: Include <setjmp.h>
73 (struct private): New.
74 (rx_get_byte): Check return value of read_memory_func, and
75 call memory_error_func and OPCODES_SIGLONGJMP on error.
76 (print_insn_rx): Call OPCODES_SIGSETJMP.
77
3a0b8f7d
YQ		 782016-12-12 Yao Qi <yao.qi@linaro.org>
79
80 * rl78-dis.c: Include <setjmp.h>.
81 (struct private): New.
82 (rl78_get_byte): Check return value of read_memory_func, and
83 call memory_error_func and OPCODES_SIGLONGJMP on error.
84 (print_insn_rl78_common): Call OPCODES_SIGJMP.
85
64c11183
MR		 862016-12-09 Maciej W. Rozycki <macro@imgtec.com>
87
88 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
89
f17ecb4b
MR		 902016-12-09 Maciej W. Rozycki <macro@imgtec.com>
91
92 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
93 than UINT.
94
55af4784
MR		 952016-12-09 Maciej W. Rozycki <macro@imgtec.com>
96
97 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
98 to separate `extend' and its uninterpreted argument output.
99 Separate hexadecimal halves of undecoded extended instructions
100 output.
101
39f66f3a
MR		 1022016-12-08 Maciej W. Rozycki <macro@imgtec.com>
103
104 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
105 indentation space across.
106
860b03a8
MR		 1072016-12-08 Maciej W. Rozycki <macro@imgtec.com>
108
109 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
110 adjustment for PC-relative operations following MIPS16e compact
111 jumps or undefined RR/J(AL)R(C) encodings.
112
329d01f7
MR		 1132016-12-08 Maciej W. Rozycki <macro@imgtec.com>
114
115 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
116 variable to `reglane_index'.
117
3a2488dd
LM		 1182016-12-08 Luis Machado <lgustavo@codesourcery.com>
119
120 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
121
5f5c6e03
MR		 1222016-12-07 Maciej W. Rozycki <macro@imgtec.com>
123
124 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
125
343fa690
MR		 1262016-12-07 Maciej W. Rozycki <macro@imgtec.com>
127
128 * mips16-opc.c (mips16_opcodes): Update comment naming structure
129 members.
130
6725647c
MR		 1312016-12-07 Maciej W. Rozycki <macro@imgtec.com>
132
133 * mips-dis.c (print_mips_disassembler_options): Reformat output.
134
c28eeff2
SN		 1352016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
136
137 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
138 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
139
49e8a725
SN		 1402016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
141
142 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
143
a37a2806
NC		 1442016-12-01 Nick Clifton <nickc@redhat.com>
145
146 PR binutils/20893
147 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
148 opcode designator.
149
abe7c33b
CZ		 1502016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
151
152 * arc-opc.c (insert_ra_chk): New function.
153 (insert_rb_chk): Likewise.
154 (insert_rad): Update text error message.
155 (insert_rcd): Likewise.
156 (insert_rhv2): Likewise.
157 (insert_r0): Likewise.
158 (insert_r1): Likewise.
159 (insert_r2): Likewise.
160 (insert_r3): Likewise.
161 (insert_sp): Likewise.
162 (insert_gp): Likewise.
163 (insert_pcl): Likewise.
164 (insert_blink): Likewise.
165 (insert_ilink1): Likewise.
166 (insert_ilink2): Likewise.
167 (insert_ras): Likewise.
168 (insert_rbs): Likewise.
169 (insert_rcs): Likewise.
170 (insert_simm3s): Likewise.
171 (insert_rrange): Likewise.
172 (insert_fpel): Likewise.
173 (insert_blinkel): Likewise.
174 (insert_pcel): Likewise.
175 (insert_nps_3bit_dst): Likewise.
176 (insert_nps_3bit_dst_short): Likewise.
177 (insert_nps_3bit_src2_short): Likewise.
178 (insert_nps_bitop_size_2b): Likewise.
179 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
180 (RA_CHK): Define.
181 (RB): Adjust.
182 (RB_CHK): Define.
183 (RC): Adjust.
184 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
185 * arc-tbl.h (div, divu): All instructions are DIVREM class.
186 Change first insn argument to check for LP_COUNT usage.
187 (rem): Likewise.
188 (ld, ldd): All instructions are LOAD class. Change first insn
189 argument to check for LP_COUNT usage.
190 (st, std): All instructions are STORE class.
191 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
192 Change first insn argument to check for LP_COUNT usage.
193 (mov): All instructions are MOVE class. Change first insn
194 argument to check for LP_COUNT usage.
195
ee881e5d
CZ		 1962016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
197
198 * arc-dis.c (is_compatible_p): Remove function.
199 (skip_this_opcode): Don't add any decoding class to decode list.
200 Remove warning.
201 (find_format_from_table): Go through all opcodes, and warn if we
202 use a guessed mnemonic.
203
abfcb414
AP		 2042016-11-28 Ramiro Polla <ramiro@hex-rays.com>
205 Amit Pawar <amit.pawar@amd.com>
206
207 PR binutils/20637
208 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
209 instructions.
210
96fe4562
AM		 2112016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
212
213 * configure: Regenerate.
214
6884417a
JM		 2152016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
216
217 * sparc-opc.c (HWS_V8): Definition moved from
218 gas/config/tc-sparc.c.
219 (HWS_V9): Likewise.
220 (HWS_VA): Likewise.
221 (HWS_VB): Likewise.
222 (HWS_VC): Likewise.
223 (HWS_VD): Likewise.
224 (HWS_VE): Likewise.
225 (HWS_VV): Likewise.
226 (HWS_VM): Likewise.
227 (HWS2_VM): Likewise.
228 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
229 existing entries.
230
c4b943d7
CZ		 2312016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
232
233 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
234 instructions.
235
c2c4ff8d
SN		 2362016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
237
238 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
239 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
240 (aarch64_opcode_table): Add fcmla and fcadd.
241 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
242 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
243 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
244 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
245 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
246 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
247 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
248 (operand_general_constraint_met_p): Rotate and index range check.
249 (aarch64_print_operand): Handle rotate operand.
250 * aarch64-asm-2.c: Regenerate.
251 * aarch64-dis-2.c: Likewise.
252 * aarch64-opc-2.c: Likewise.
253
28617675
SN		 2542016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
255
256 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
257 * aarch64-asm-2.c: Regenerate.
258 * aarch64-dis-2.c: Regenerate.
259 * aarch64-opc-2.c: Regenerate.
260
ccfc90a3
SN		 2612016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
262
263 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
264 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
265 * aarch64-asm-2.c: Regenerate.
266 * aarch64-dis-2.c: Regenerate.
267 * aarch64-opc-2.c: Regenerate.
268
3f06e550
SN		 2692016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
270
271 * aarch64-tbl.h (QL_X1NIL): New.
272 (arch64_opcode_table): Add ldraa, ldrab.
273 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
274 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
275 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
276 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
277 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
278 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
279 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
280 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
281 (aarch64_print_operand): Likewise.
282 * aarch64-asm-2.c: Regenerate.
283 * aarch64-dis-2.c: Regenerate.
284 * aarch64-opc-2.c: Regenerate.
285
74f5402d
SN		 2862016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
287
288 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
289 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
290 * aarch64-asm-2.c: Regenerate.
291 * aarch64-dis-2.c: Regenerate.
292 * aarch64-opc-2.c: Regenerate.
293
c84364ec
SN		 2942016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
295
296 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
297 (AARCH64_OPERANDS): Add Rm_SP.
298 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
299 * aarch64-asm-2.c: Regenerate.
300 * aarch64-dis-2.c: Regenerate.
301 * aarch64-opc-2.c: Regenerate.
302
a2cfc830
SN		 3032016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
304
305 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
306 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
307 autdzb, xpaci, xpacd.
308 * aarch64-asm-2.c: Regenerate.
309 * aarch64-dis-2.c: Regenerate.
310 * aarch64-opc-2.c: Regenerate.
311
b0bfa7b5
SN		 3122016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
313
314 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
315 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
316 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
317 (aarch64_sys_reg_supported_p): Add feature test for new registers.
318
8787d804
SN		 3192016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
320
321 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
322 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
323 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
324 autibsp.
325 * aarch64-asm-2.c: Regenerate.
326 * aarch64-dis-2.c: Regenerate.
327
3d731f69
SN		 3282016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
329
330 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
331
60227d64
L		 3322016-11-09 H.J. Lu <hongjiu.lu@intel.com>
333
334 PR binutils/20799
335 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
336 * i386-dis.c (EdqwS): Removed.
337 (dqw_swap_mode): Likewise.
338 (intel_operand_size): Don't check dqw_swap_mode.
339 (OP_E_register): Likewise.
340 (OP_E_memory): Likewise.
341 (OP_G): Likewise.
342 (OP_EX): Likewise.
343 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
344 * i386-tbl.h: Regerated.
345
7efeed17
L		 3462016-11-09 H.J. Lu <hongjiu.lu@intel.com>
347
348 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 349 * i386-tbl.h: Regerated.
7efeed17 350
1f334aeb
L		 3512016-11-08 H.J. Lu <hongjiu.lu@intel.com>
352
353 PR binutils/20701
354 * i386-dis.c (THREE_BYTE_0F7A): Removed.
355 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
356 (three_byte_table): Remove THREE_BYTE_0F7A.
357
48c97fa1
L		 3582016-11-07 H.J. Lu <hongjiu.lu@intel.com>
359
360 PR binutils/20775
361 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
362 (FGRPd9_4): Replace 1 with 2.
363 (FGRPd9_5): Replace 2 with 3.
364 (FGRPd9_6): Replace 3 with 4.
365 (FGRPd9_7): Replace 4 with 5.
366 (FGRPda_5): Replace 5 with 6.
367 (FGRPdb_4): Replace 6 with 7.
368 (FGRPde_3): Replace 7 with 8.
369 (FGRPdf_4): Replace 8 with 9.
370 (fgrps): Add an entry for Bad_Opcode.
371
b437d035
AB		 3722016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
373
374 * arc-opc.c (arc_flag_operands): Add F_DI14.
375 (arc_flag_classes): Add C_DI14.
376 * arc-nps400-tbl.h: Add new exc instructions.
377
5a736821
GM		 3782016-11-03 Graham Markall <graham.markall@embecosm.com>
379
380 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
381 major opcode 0xa.
382 * arc-nps-400-tbl.h: Add dcmac instruction.
383 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
384 (insert_nps_rbdouble_64): Added.
385 (extract_nps_rbdouble_64): Added.
386 (insert_nps_proto_size): Added.
387 (extract_nps_proto_size): Added.
388
bdfe53e3
AB		 3892016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
390
391 * arc-dis.c (struct arc_operand_iterator): Remove all fields
392 relating to long instruction processing, add new limm field.
393 (OPCODE): Rename to...
394 (OPCODE_32BIT_INSN): ...this.
395 (OPCODE_AC): Delete.
396 (skip_this_opcode): Handle different instruction lengths, update
397 macro name.
398 (special_flag_p): Update parameter type.
399 (find_format_from_table): Update for more instruction lengths.
400 (find_format_long_instructions): Delete.
401 (find_format): Update for more instruction lengths.
402 (arc_insn_length): Likewise.
403 (extract_operand_value): Update for more instruction lengths.
404 (operand_iterator_next): Remove code relating to long
405 instructions.
406 (arc_opcode_to_insn_type): New function.
407 (print_insn_arc):Update for more instructions lengths.
408 * arc-ext.c (extInstruction_t): Change argument type.
409 * arc-ext.h (extInstruction_t): Change argument type.
410 * arc-fxi.h: Change type unsigned to unsigned long long
411 extensively throughout.
412 * arc-nps400-tbl.h: Add long instructions taken from
413 arc_long_opcodes table in arc-opc.c.
414 * arc-opc.c: Update parameter types on insert/extract handlers.
415 (arc_long_opcodes): Delete.
416 (arc_num_long_opcodes): Delete.
417 (arc_opcode_len): Update for more instruction lengths.
418
90f61cce
GM		 4192016-11-03 Graham Markall <graham.markall@embecosm.com>
420
421 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
422
06fe285f
GM		 4232016-11-03 Graham Markall <graham.markall@embecosm.com>
424
425 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
426 with arc_opcode_len.
427 (find_format_long_instructions): Likewise.
428 * arc-opc.c (arc_opcode_len): New function.
429
ecf64ec6
AB		 4302016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
431
432 * arc-nps400-tbl.h: Fix some instruction masks.
433
d039fef3
L		 4342016-11-03 H.J. Lu <hongjiu.lu@intel.com>
435
436 * i386-dis.c (REG_82): Removed.
437 (X86_64_82_REG_0): Likewise.
438 (X86_64_82_REG_1): Likewise.
439 (X86_64_82_REG_2): Likewise.
440 (X86_64_82_REG_3): Likewise.
441 (X86_64_82_REG_4): Likewise.
442 (X86_64_82_REG_5): Likewise.
443 (X86_64_82_REG_6): Likewise.
444 (X86_64_82_REG_7): Likewise.
445 (X86_64_82): New.
446 (dis386): Use X86_64_82 instead of REG_82.
447 (reg_table): Remove REG_82.
448 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
449 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
450 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
451 X86_64_82_REG_7.
452
8b89fe14
L		 4532016-11-03 H.J. Lu <hongjiu.lu@intel.com>
454
455 PR binutils/20754
456 * i386-dis.c (REG_82): New.
457 (X86_64_82_REG_0): Likewise.
458 (X86_64_82_REG_1): Likewise.
459 (X86_64_82_REG_2): Likewise.
460 (X86_64_82_REG_3): Likewise.
461 (X86_64_82_REG_4): Likewise.
462 (X86_64_82_REG_5): Likewise.
463 (X86_64_82_REG_6): Likewise.
464 (X86_64_82_REG_7): Likewise.
465 (dis386): Use REG_82.
466 (reg_table): Add REG_82.
467 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
468 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
469 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
470
7148c369
L		 4712016-11-03 H.J. Lu <hongjiu.lu@intel.com>
472
473 * i386-dis.c (REG_82): Renamed to ...
474 (REG_83): This.
475 (dis386): Updated.
476 (reg_table): Likewise.
477
47acf0bd
IT		 4782016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
479
480 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
481 * i386-dis-evex.h (evex_table): Updated.
482 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
483 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
484 (cpu_flags): Add CpuAVX512_4VNNIW.
485 * i386-opc.h (enum): (AVX512_4VNNIW): New.
486 (i386_cpu_flags): Add cpuavx512_4vnniw.
487 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
488 * i386-init.h: Regenerate.
489 * i386-tbl.h: Ditto.
490
920d2ddc
IT		 4912016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
492
493 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
494 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
495 * i386-dis-evex.h (evex_table): Updated.
496 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
497 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
498 (cpu_flags): Add CpuAVX512_4FMAPS.
499 (opcode_modifiers): Add ImplicitQuadGroup modifier.
500 * i386-opc.h (AVX512_4FMAP): New.
501 (i386_cpu_flags): Add cpuavx512_4fmaps.
502 (ImplicitQuadGroup): New.
503 (i386_opcode_modifier): Add implicitquadgroup.
504 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
505 * i386-init.h: Regenerate.
506 * i386-tbl.h: Ditto.
507
e23eba97
NC		 5082016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
509 Andrew Waterman <andrew@sifive.com>
510
511 Add support for RISC-V architecture.
512 * configure.ac: Add entry for bfd_riscv_arch.
513 * configure: Regenerate.
514 * disassemble.c (disassembler): Add support for riscv.
515 (disassembler_usage): Likewise.
516 * riscv-dis.c: New file.
517 * riscv-opc.c: New file.
518
b5cefcca
L		 5192016-10-21 H.J. Lu <hongjiu.lu@intel.com>
520
521 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
522 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
523 (rm_table): Update the RM_0FAE_REG_7 entry.
524 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
525 (cpu_flags): Remove CpuPCOMMIT.
526 * i386-opc.h (CpuPCOMMIT): Removed.
527 (i386_cpu_flags): Remove cpupcommit.
528 * i386-opc.tbl: Remove pcommit.
529 * i386-init.h: Regenerated.
530 * i386-tbl.h: Likewise.
531
9889cbb1
L		 5322016-10-20 H.J. Lu <hongjiu.lu@intel.com>
533
534 PR binutis/20705
535 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
536 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
537 32-bit mode. Don't check vex.register_specifier in 32-bit
538 mode.
539 (OP_VEX): Check for invalid mask registers.
540
28596323
L		 5412016-10-18 H.J. Lu <hongjiu.lu@intel.com>
542
543 PR binutis/20699
544 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
545 sizeflag.
546
da8d7d66
L		 5472016-10-18 H.J. Lu <hongjiu.lu@intel.com>
548
549 PR binutis/20704
550 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
551
eaf02703
MR		 5522016-10-18 Maciej W. Rozycki <macro@imgtec.com>
553
554 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
555 local variable to `index_regno'.
556
decf5bd1
CM		 5572016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
558
559 * arc-tbl.h: Removed any "inv.+" instructions from the table.
560
e5b06ef0
CZ		 5612016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
562
563 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
564 usage on ISA basis.
565
93562a34
JW		 5662016-10-11 Jiong Wang <jiong.wang@arm.com>
567
568 PR target/20666
569 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
570
362c0c4d
JW		 5712016-10-07 Jiong Wang <jiong.wang@arm.com>
572
573 PR target/20667
574 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
575 available.
576
1047201f
AM		 5772016-10-07 Alan Modra <amodra@gmail.com>
578
579 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
580
1a0670f3
AM		 5812016-10-06 Alan Modra <amodra@gmail.com>
582
583 * aarch64-opc.c: Spell fall through comments consistently.
584 * i386-dis.c: Likewise.
585 * aarch64-dis.c: Add missing fall through comments.
586 * aarch64-opc.c: Likewise.
587 * arc-dis.c: Likewise.
588 * arm-dis.c: Likewise.
589 * i386-dis.c: Likewise.
590 * m68k-dis.c: Likewise.
591 * mep-asm.c: Likewise.
592 * ns32k-dis.c: Likewise.
593 * sh-dis.c: Likewise.
594 * tic4x-dis.c: Likewise.
595 * tic6x-dis.c: Likewise.
596 * vax-dis.c: Likewise.
597
2b804145
AM		 5982016-10-06 Alan Modra <amodra@gmail.com>
599
600 * arc-ext.c (create_map): Add missing break.
601 * msp430-decode.opc (encode_as): Likewise.
602 * msp430-decode.c: Regenerate.
603
616ec358
AM		 6042016-10-06 Alan Modra <amodra@gmail.com>
605
606 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
607 * crx-dis.c (print_insn_crx): Likewise.
608
72da393d
L		 6092016-09-30 H.J. Lu <hongjiu.lu@intel.com>
610
611 PR binutils/20657
612 * i386-dis.c (putop): Don't assign alt twice.
613
744ce302
JW		 6142016-09-29 Jiong Wang <jiong.wang@arm.com>
615
616 PR target/20553
617 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
618
a5721ba2
AM		 6192016-09-29 Alan Modra <amodra@gmail.com>
620
621 * ppc-opc.c (L): Make compulsory.
622 (LOPT): New, optional form of L.
623 (HTM_R): Define as LOPT.
624 (L0, L1): Delete.
625 (L32OPT): New, optional for 32-bit L.
626 (L2OPT): New, 2-bit L for dcbf.
627 (SVC_LEC): Update.
628 (L2): Define.
629 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
630 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
631 <dcbf>: Use L2OPT.
632 <tlbiel, tlbie>: Use LOPT.
633 <wclr, wclrall>: Use L2.
634
c5da1932
VZ		 6352016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
636
637 * Makefile.in: Regenerate.
638 * configure: Likewise.
639
2b848ebd
CZ		 6402016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
641
642 * arc-ext-tbl.h (EXTINSN2OPF): Define.
643 (EXTINSN2OP): Use EXTINSN2OPF.
644 (bspeekm, bspop, modapp): New extension instructions.
645 * arc-opc.c (F_DNZ_ND): Define.
646 (F_DNZ_D): Likewise.
647 (F_SIZEB1): Changed.
648 (C_DNZ_D): Define.
649 (C_HARD): Changed.
650 * arc-tbl.h (dbnz): New instruction.
651 (prealloc): Allow it for ARC EM.
652 (xbfu): Likewise.
653
ad43e107
RS		 6542016-09-21 Richard Sandiford <richard.sandiford@arm.com>
655
656 * aarch64-opc.c (print_immediate_offset_address): Print spaces
657 after commas in addresses.
658 (aarch64_print_operand): Likewise.
659
ab3b8fcf
RS		 6602016-09-21 Richard Sandiford <richard.sandiford@arm.com>
661
662 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
663 rather than "should be" or "expected to be" in error messages.
664
bb7eff52
RS		 6652016-09-21 Richard Sandiford <richard.sandiford@arm.com>
666
667 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
668 (print_mnemonic_name): ...here.
669 (print_comment): New function.
670 (print_aarch64_insn): Call it.
671 * aarch64-opc.c (aarch64_conds): Add SVE names.
672 (aarch64_print_operand): Print alternative condition names in
673 a comment.
674
c0890d26
RS		 6752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
676
677 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
678 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
679 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
680 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
681 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
682 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
683 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
684 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
685 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
686 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
687 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
688 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
689 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
690 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
691 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
692 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
693 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
694 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
695 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
696 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
697 (OP_SVE_XWU, OP_SVE_XXU): New macros.
698 (aarch64_feature_sve): New variable.
699 (SVE): New macro.
700 (_SVE_INSN): Likewise.
701 (aarch64_opcode_table): Add SVE instructions.
702 * aarch64-opc.h (extract_fields): Declare.
703 * aarch64-opc-2.c: Regenerate.
704 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
705 * aarch64-asm-2.c: Regenerate.
706 * aarch64-dis.c (extract_fields): Make global.
707 (do_misc_decoding): Handle the new SVE aarch64_ops.
708 * aarch64-dis-2.c: Regenerate.
709
116b6019
RS		 7102016-09-21 Richard Sandiford <richard.sandiford@arm.com>
711
712 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
713 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
714 aarch64_field_kinds.
715 * aarch64-opc.c (fields): Add corresponding entries.
716 * aarch64-asm.c (aarch64_get_variant): New function.
717 (aarch64_encode_variant_using_iclass): Likewise.
718 (aarch64_opcode_encode): Call it.
719 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
720 (aarch64_opcode_decode): Call it.
721
047cd301
RS		 7222016-09-21 Richard Sandiford <richard.sandiford@arm.com>
723
724 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
725 and FP register operands.
726 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
727 (FLD_SVE_Vn): New aarch64_field_kinds.
728 * aarch64-opc.c (fields): Add corresponding entries.
729 (aarch64_print_operand): Handle the new SVE core and FP register
730 operands.
731 * aarch64-opc-2.c: Regenerate.
732 * aarch64-asm-2.c: Likewise.
733 * aarch64-dis-2.c: Likewise.
734
165d4950
RS		 7352016-09-21 Richard Sandiford <richard.sandiford@arm.com>
736
737 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
738 immediate operands.
739 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
740 * aarch64-opc.c (fields): Add corresponding entry.
741 (operand_general_constraint_met_p): Handle the new SVE FP immediate
742 operands.
743 (aarch64_print_operand): Likewise.
744 * aarch64-opc-2.c: Regenerate.
745 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
746 (ins_sve_float_zero_one): New inserters.
747 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
748 (aarch64_ins_sve_float_half_two): Likewise.
749 (aarch64_ins_sve_float_zero_one): Likewise.
750 * aarch64-asm-2.c: Regenerate.
751 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
752 (ext_sve_float_zero_one): New extractors.
753 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
754 (aarch64_ext_sve_float_half_two): Likewise.
755 (aarch64_ext_sve_float_zero_one): Likewise.
756 * aarch64-dis-2.c: Regenerate.
757
e950b345
RS		 7582016-09-21 Richard Sandiford <richard.sandiford@arm.com>
759
760 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
761 integer immediate operands.
762 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
763 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
764 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
765 * aarch64-opc.c (fields): Add corresponding entries.
766 (operand_general_constraint_met_p): Handle the new SVE integer
767 immediate operands.
768 (aarch64_print_operand): Likewise.
769 (aarch64_sve_dupm_mov_immediate_p): New function.
770 * aarch64-opc-2.c: Regenerate.
771 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
772 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
773 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
774 (aarch64_ins_limm): ...here.
775 (aarch64_ins_inv_limm): New function.
776 (aarch64_ins_sve_aimm): Likewise.
777 (aarch64_ins_sve_asimm): Likewise.
778 (aarch64_ins_sve_limm_mov): Likewise.
779 (aarch64_ins_sve_shlimm): Likewise.
780 (aarch64_ins_sve_shrimm): Likewise.
781 * aarch64-asm-2.c: Regenerate.
782 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
783 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
784 * aarch64-dis.c (decode_limm): New function, split out from...
785 (aarch64_ext_limm): ...here.
786 (aarch64_ext_inv_limm): New function.
787 (decode_sve_aimm): Likewise.
788 (aarch64_ext_sve_aimm): Likewise.
789 (aarch64_ext_sve_asimm): Likewise.
790 (aarch64_ext_sve_limm_mov): Likewise.
791 (aarch64_top_bit): Likewise.
792 (aarch64_ext_sve_shlimm): Likewise.
793 (aarch64_ext_sve_shrimm): Likewise.
794 * aarch64-dis-2.c: Regenerate.
795
98907a70
RS		 7962016-09-21 Richard Sandiford <richard.sandiford@arm.com>
797
798 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
799 operands.
800 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
801 the AARCH64_MOD_MUL_VL entry.
802 (value_aligned_p): Cope with non-power-of-two alignments.
803 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
804 (print_immediate_offset_address): Likewise.
805 (aarch64_print_operand): Likewise.
806 * aarch64-opc-2.c: Regenerate.
807 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
808 (ins_sve_addr_ri_s9xvl): New inserters.
809 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
810 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
811 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
812 * aarch64-asm-2.c: Regenerate.
813 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
814 (ext_sve_addr_ri_s9xvl): New extractors.
815 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
816 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
817 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
818 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
819 * aarch64-dis-2.c: Regenerate.
820
4df068de
RS		 8212016-09-21 Richard Sandiford <richard.sandiford@arm.com>
822
823 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
824 address operands.
825 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
826 (FLD_SVE_xs_22): New aarch64_field_kinds.
827 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
828 (get_operand_specific_data): New function.
829 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
830 FLD_SVE_xs_14 and FLD_SVE_xs_22.
831 (operand_general_constraint_met_p): Handle the new SVE address
832 operands.
833 (sve_reg): New array.
834 (get_addr_sve_reg_name): New function.
835 (aarch64_print_operand): Handle the new SVE address operands.
836 * aarch64-opc-2.c: Regenerate.
837 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
838 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
839 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
840 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
841 (aarch64_ins_sve_addr_rr_lsl): Likewise.
842 (aarch64_ins_sve_addr_rz_xtw): Likewise.
843 (aarch64_ins_sve_addr_zi_u5): Likewise.
844 (aarch64_ins_sve_addr_zz): Likewise.
845 (aarch64_ins_sve_addr_zz_lsl): Likewise.
846 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
847 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
848 * aarch64-asm-2.c: Regenerate.
849 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
850 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
851 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
852 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
853 (aarch64_ext_sve_addr_ri_u6): Likewise.
854 (aarch64_ext_sve_addr_rr_lsl): Likewise.
855 (aarch64_ext_sve_addr_rz_xtw): Likewise.
856 (aarch64_ext_sve_addr_zi_u5): Likewise.
857 (aarch64_ext_sve_addr_zz): Likewise.
858 (aarch64_ext_sve_addr_zz_lsl): Likewise.
859 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
860 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
861 * aarch64-dis-2.c: Regenerate.
862
2442d846
RS		 8632016-09-21 Richard Sandiford <richard.sandiford@arm.com>
864
865 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
866 AARCH64_OPND_SVE_PATTERN_SCALED.
867 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
868 * aarch64-opc.c (fields): Add a corresponding entry.
869 (set_multiplier_out_of_range_error): New function.
870 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
871 (operand_general_constraint_met_p): Handle
872 AARCH64_OPND_SVE_PATTERN_SCALED.
873 (print_register_offset_address): Use PRIi64 to print the
874 shift amount.
875 (aarch64_print_operand): Likewise. Handle
876 AARCH64_OPND_SVE_PATTERN_SCALED.
877 * aarch64-opc-2.c: Regenerate.
878 * aarch64-asm.h (ins_sve_scale): New inserter.
879 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
880 * aarch64-asm-2.c: Regenerate.
881 * aarch64-dis.h (ext_sve_scale): New inserter.
882 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
883 * aarch64-dis-2.c: Regenerate.
884
245d2e3f
RS		 8852016-09-21 Richard Sandiford <richard.sandiford@arm.com>
886
887 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
888 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
889 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
890 (FLD_SVE_prfop): Likewise.
891 * aarch64-opc.c: Include libiberty.h.
892 (aarch64_sve_pattern_array): New variable.
893 (aarch64_sve_prfop_array): Likewise.
894 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
895 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
896 AARCH64_OPND_SVE_PRFOP.
897 * aarch64-asm-2.c: Regenerate.
898 * aarch64-dis-2.c: Likewise.
899 * aarch64-opc-2.c: Likewise.
900
d50c751e
RS		 9012016-09-21 Richard Sandiford <richard.sandiford@arm.com>
902
903 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
904 AARCH64_OPND_QLF_P_[ZM].
905 (aarch64_print_operand): Print /z and /m where appropriate.
906
f11ad6bc
RS		 9072016-09-21 Richard Sandiford <richard.sandiford@arm.com>
908
909 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
910 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
911 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
912 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
913 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
914 * aarch64-opc.c (fields): Add corresponding entries here.
915 (operand_general_constraint_met_p): Check that SVE register lists
916 have the correct length. Check the ranges of SVE index registers.
917 Check for cases where p8-p15 are used in 3-bit predicate fields.
918 (aarch64_print_operand): Handle the new SVE operands.
919 * aarch64-opc-2.c: Regenerate.
920 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
921 * aarch64-asm.c (aarch64_ins_sve_index): New function.
922 (aarch64_ins_sve_reglist): Likewise.
923 * aarch64-asm-2.c: Regenerate.
924 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
925 * aarch64-dis.c (aarch64_ext_sve_index): New function.
926 (aarch64_ext_sve_reglist): Likewise.
927 * aarch64-dis-2.c: Regenerate.
928
0c608d6b
RS		 9292016-09-21 Richard Sandiford <richard.sandiford@arm.com>
930
931 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
932 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
933 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
934 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
935 tied operands.
936
01dbfe4c
RS		 9372016-09-21 Richard Sandiford <richard.sandiford@arm.com>
938
939 * aarch64-opc.c (get_offset_int_reg_name): New function.
940 (print_immediate_offset_address): Likewise.
941 (print_register_offset_address): Take the base and offset
942 registers as parameters.
943 (aarch64_print_operand): Update caller accordingly. Use
944 print_immediate_offset_address.
945
72e9f319
RS		 9462016-09-21 Richard Sandiford <richard.sandiford@arm.com>
947
948 * aarch64-opc.c (BANK): New macro.
949 (R32, R64): Take a register number as argument
950 (int_reg): Use BANK.
951
8a7f0c1b
RS		 9522016-09-21 Richard Sandiford <richard.sandiford@arm.com>
953
954 * aarch64-opc.c (print_register_list): Add a prefix parameter.
955 (aarch64_print_operand): Update accordingly.
956
aa2aa4c6
RS		 9572016-09-21 Richard Sandiford <richard.sandiford@arm.com>
958
959 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
960 for FPIMM.
961 * aarch64-asm.h (ins_fpimm): New inserter.
962 * aarch64-asm.c (aarch64_ins_fpimm): New function.
963 * aarch64-asm-2.c: Regenerate.
964 * aarch64-dis.h (ext_fpimm): New extractor.
965 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
966 (aarch64_ext_fpimm): New function.
967 * aarch64-dis-2.c: Regenerate.
968
b5464a68
RS		 9692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
970
971 * aarch64-asm.c: Include libiberty.h.
972 (insert_fields): New function.
973 (aarch64_ins_imm): Use it.
974 * aarch64-dis.c (extract_fields): New function.
975 (aarch64_ext_imm): Use it.
976
42408347
RS		 9772016-09-21 Richard Sandiford <richard.sandiford@arm.com>
978
979 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
980 with an esize parameter.
981 (operand_general_constraint_met_p): Update accordingly.
982 Fix misindented code.
983 * aarch64-asm.c (aarch64_ins_limm): Update call to
984 aarch64_logical_immediate_p.
985
4989adac
RS		 9862016-09-21 Richard Sandiford <richard.sandiford@arm.com>
987
988 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
989
bd11d5d8
RS		 9902016-09-21 Richard Sandiford <richard.sandiford@arm.com>
991
992 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
993
f807f43d
CZ		 9942016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
995
996 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
997
fd486b63
PB		 9982016-09-14 Peter Bergner <bergner@vnet.ibm.com>
999
1000 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1001 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1002 xor3>: Delete mnemonics.
1003 <cp_abort>: Rename mnemonic from ...
1004 <cpabort>: ...to this.
1005 <setb>: Change to a X form instruction.
1006 <sync>: Change to 1 operand form.
1007 <copy>: Delete mnemonic.
1008 <copy_first>: Rename mnemonic from ...
1009 <copy>: ...to this.
1010 <paste, paste.>: Delete mnemonics.
1011 <paste_last>: Rename mnemonic from ...
1012 <paste.>: ...to this.
1013
dce08442
AK		 10142016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1015
1016 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1017
952c3f51
AK		 10182016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1019
1020 * s390-mkopc.c (main): Support alternate arch strings.
1021
8b71537b
PS		 10222016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1023
1024 * s390-opc.txt: Fix kmctr instruction type.
1025
5b64d091
L		 10262016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1027
1028 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1029 * i386-init.h: Regenerated.
1030
7763838e
CM		 10312016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1032
1033 * opcodes/arc-dis.c (print_insn_arc): Changed.
1034
1b8b6532
JM		 10352016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1036
1037 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1038 camellia_fl.
1039
1a336194
TP		 10402016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1041
1042 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1043 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1044 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1045
6b40c462
L		 10462016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1047
1048 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1049 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1050 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1051 PREFIX_MOD_3_0FAE_REG_4.
1052 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1053 PREFIX_MOD_3_0FAE_REG_4.
1054 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1055 (cpu_flags): Add CpuPTWRITE.
1056 * i386-opc.h (CpuPTWRITE): New.
1057 (i386_cpu_flags): Add cpuptwrite.
1058 * i386-opc.tbl: Add ptwrite instruction.
1059 * i386-init.h: Regenerated.
1060 * i386-tbl.h: Likewise.
1061
ab548d2d
AK		 10622016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1063
1064 * arc-dis.h: Wrap around in extern "C".
1065
344bde0a
RS		 10662016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1067
1068 * aarch64-tbl.h (V8_2_INSN): New macro.
1069 (aarch64_opcode_table): Use it.
1070
5ce912d8
RS		 10712016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1072
1073 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1074 CORE_INSN, __FP_INSN and SIMD_INSN.
1075
9d30b0bd
RS		 10762016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1077
1078 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1079 (aarch64_opcode_table): Update uses accordingly.
1080
dfdaec14
AJ		 10812016-07-25 Andrew Jenner <andrew@codesourcery.com>
1082 Kwok Cheung Yeung <kcy@codesourcery.com>
1083
1084 opcodes/
1085 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1086 'e_cmplwi' to 'e_cmpli' instead.
1087 (OPVUPRT, OPVUPRT_MASK): Define.
1088 (powerpc_opcodes): Add E200Z4 insns.
1089 (vle_opcodes): Add context save/restore insns.
1090
7bd374a4
MR		 10912016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1092
1093 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1094 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1095 "j".
1096
db18dbab
GM		 10972016-07-27 Graham Markall <graham.markall@embecosm.com>
1098
1099 * arc-nps400-tbl.h: Change block comments to GNU format.
1100 * arc-dis.c: Add new globals addrtypenames,
1101 addrtypenames_max, and addtypeunknown.
1102 (get_addrtype): New function.
1103 (print_insn_arc): Print colons and address types when
1104 required.
1105 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1106 define insert and extract functions for all address types.
1107 (arc_operands): Add operands for colon and all address
1108 types.
1109 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1110 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1111 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1112 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1113 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1114 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1115
fecd57f9
L		 11162016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1117
1118 * configure: Regenerated.
1119
37fd5ef3
CZ		 11202016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1121
1122 * arc-dis.c (skipclass): New structure.
1123 (decodelist): New variable.
1124 (is_compatible_p): New function.
1125 (new_element): Likewise.
1126 (skip_class_p): Likewise.
1127 (find_format_from_table): Use skip_class_p function.
1128 (find_format): Decode first the extension instructions.
1129 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1130 e_flags.
1131 (parse_option): New function.
1132 (parse_disassembler_options): Likewise.
1133 (print_arc_disassembler_options): Likewise.
1134 (print_insn_arc): Use parse_disassembler_options function. Proper
1135 select ARCv2 cpu variant.
1136 * disassemble.c (disassembler_usage): Add ARC disassembler
1137 options.
1138
92281a5b
MR		 11392016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1140
1141 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1142 annotation from the "nal" entry and reorder it beyond "bltzal".
1143
6e7ced37
JM		 11442016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1145
1146 * sparc-opc.c (ldtxa): New macro.
1147 (sparc_opcodes): Use the macro defined above to add entries for
1148 the LDTXA instructions.
1149 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1150 instruction.
1151
2f831b9a 11522016-07-07 James Bowman <james.bowman@ftdichip.com>
1153
1154 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1155 and "jmpc".
1156
c07315e0
JB		 11572016-07-01 Jan Beulich <jbeulich@suse.com>
1158
1159 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1160 (movzb): Adjust to cover all permitted suffixes.
1161 (movzw): New.
1162 * i386-tbl.h: Re-generate.
1163
9243100a
JB		 11642016-07-01 Jan Beulich <jbeulich@suse.com>
1165
1166 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1167 (lgdt): Remove Tbyte from non-64-bit variant.
1168 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1169 xsaves64, xsavec64): Remove Disp16.
1170 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1171 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1172 64-bit variants.
1173 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1174 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1175 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1176 64-bit variants.
1177 * i386-tbl.h: Re-generate.
1178
8325cc63
JB		 11792016-07-01 Jan Beulich <jbeulich@suse.com>
1180
1181 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1182 * i386-tbl.h: Re-generate.
1183
838441e4
YQ		 11842016-06-30 Yao Qi <yao.qi@linaro.org>
1185
1186 * arm-dis.c (print_insn): Fix typo in comment.
1187
dab26bf4
RS		 11882016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1189
1190 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1191 range of ldst_elemlist operands.
1192 (print_register_list): Use PRIi64 to print the index.
1193 (aarch64_print_operand): Likewise.
1194
5703197e
TS		 11952016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1196
1197 * mcore-opc.h: Remove sentinal.
1198 * mcore-dis.c (print_insn_mcore): Adjust.
1199
ce440d63
GM		 12002016-06-23 Graham Markall <graham.markall@embecosm.com>
1201
1202 * arc-opc.c: Correct description of availability of NPS400
1203 features.
1204
6fd3a02d
PB		 12052016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1206
1207 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1208 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1209 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1210 xor3>: New mnemonics.
1211 <setb>: Change to a VX form instruction.
1212 (insert_sh6): Add support for rldixor.
1213 (extract_sh6): Likewise.
1214
6b477896
TS		 12152016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1216
1217 * arc-ext.h: Wrap in extern C.
1218
bdd582db
GM		 12192016-06-21 Graham Markall <graham.markall@embecosm.com>
1220
1221 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1222 Use same method for determining instruction length on ARC700 and
1223 NPS-400.
1224 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1225 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1226 with the NPS400 subclass.
1227 * arc-opc.c: Likewise.
1228
96074adc
JM		 12292016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1230
1231 * sparc-opc.c (rdasr): New macro.
1232 (wrasr): Likewise.
1233 (rdpr): Likewise.
1234 (wrpr): Likewise.
1235 (rdhpr): Likewise.
1236 (wrhpr): Likewise.
1237 (sparc_opcodes): Use the macros above to fix and expand the
1238 definition of read/write instructions from/to
1239 asr/privileged/hyperprivileged instructions.
1240 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1241 %hva_mask_nz. Prefer softint_set and softint_clear over
1242 set_softint and clear_softint.
1243 (print_insn_sparc): Support %ver in Rd.
1244
7a10c22f
JM		 12452016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1246
1247 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1248 architecture according to the hardware capabilities they require.
1249
4f26fb3a
JM		 12502016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1251
1252 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1253 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1254 bfd_mach_sparc_v9{c,d,e,v,m}.
1255 * sparc-opc.c (MASK_V9C): Define.
1256 (MASK_V9D): Likewise.
1257 (MASK_V9E): Likewise.
1258 (MASK_V9V): Likewise.
1259 (MASK_V9M): Likewise.
1260 (v6): Add MASK_V9{C,D,E,V,M}.
1261 (v6notlet): Likewise.
1262 (v7): Likewise.
1263 (v8): Likewise.
1264 (v9): Likewise.
1265 (v9andleon): Likewise.
1266 (v9a): Likewise.
1267 (v9b): Likewise.
1268 (v9c): Define.
1269 (v9d): Likewise.
1270 (v9e): Likewise.
1271 (v9v): Likewise.
1272 (v9m): Likewise.
1273 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1274
3ee6e4fb
NC		 12752016-06-15 Nick Clifton <nickc@redhat.com>
1276
1277 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1278 constants to match expected behaviour.
1279 (nds32_parse_opcode): Likewise. Also for whitespace.
1280
02f3be19
AB		 12812016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1282
1283 * arc-opc.c (extract_rhv1): Extract value from insn.
1284
6f9f37ed 12852016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1286
1287 * arc-nps400-tbl.h: Add ldbit instruction.
1288 * arc-opc.c: Add flag classes required for ldbit.
1289
6f9f37ed 12902016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1291
1292 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1293 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1294 support the above instructions.
1295
6f9f37ed 12962016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1297
1298 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1299 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1300 csma, cbba, zncv, and hofs.
1301 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1302 support the above instructions.
1303
13042016-06-06 Graham Markall <graham.markall@embecosm.com>
1305
1306 * arc-nps400-tbl.h: Add andab and orab instructions.
1307
13082016-06-06 Graham Markall <graham.markall@embecosm.com>
1309
1310 * arc-nps400-tbl.h: Add addl-like instructions.
1311
13122016-06-06 Graham Markall <graham.markall@embecosm.com>
1313
1314 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1315
13162016-06-06 Graham Markall <graham.markall@embecosm.com>
1317
1318 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1319 instructions.
1320
b2cc3f6f
AK		 13212016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1322
1323 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1324 variable.
1325 (init_disasm): Handle new command line option "insnlength".
1326 (print_s390_disassembler_options): Mention new option in help
1327 output.
1328 (print_insn_s390): Use the encoded insn length when dumping
1329 unknown instructions.
1330
1857fe72
DC		 13312016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1332
1333 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1334 to the address and set as symbol address for LDS/ STS immediate operands.
1335
14b57c7c
AM		 13362016-06-07 Alan Modra <amodra@gmail.com>
1337
1338 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1339 cpu for "vle" to e500.
1340 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1341 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1342 (PPCNONE): Delete, substitute throughout.
1343 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1344 except for major opcode 4 and 31.
1345 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1346
4d1464f2
MW		 13472016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1348
1349 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1350 ARM_EXT_RAS in relevant entries.
1351
026122a6
PB		 13522016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1353
1354 PR binutils/20196
1355 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1356 opcodes for E6500.
1357
07f5af7d
L		 13582016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1359
1360 PR binutis/18386
1361 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1362 (indir_v_mode): New.
1363 Add comments for '&'.
1364 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1365 (putop): Handle '&'.
1366 (intel_operand_size): Handle indir_v_mode.
1367 (OP_E_register): Likewise.
1368 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1369 64-bit indirect call/jmp for AMD64.
1370 * i386-tbl.h: Regenerated
1371
4eb6f892
AB		 13722016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1373
1374 * arc-dis.c (struct arc_operand_iterator): New structure.
1375 (find_format_from_table): All the old content from find_format,
1376 with some minor adjustments, and parameter renaming.
1377 (find_format_long_instructions): New function.
1378 (find_format): Rewritten.
1379 (arc_insn_length): Add LSB parameter.
1380 (extract_operand_value): New function.
1381 (operand_iterator_next): New function.
1382 (print_insn_arc): Use new functions to find opcode, and iterator
1383 over operands.
1384 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1385 (extract_nps_3bit_dst_short): New function.
1386 (insert_nps_3bit_src2_short): New function.
1387 (extract_nps_3bit_src2_short): New function.
1388 (insert_nps_bitop1_size): New function.
1389 (extract_nps_bitop1_size): New function.
1390 (insert_nps_bitop2_size): New function.
1391 (extract_nps_bitop2_size): New function.
1392 (insert_nps_bitop_mod4_msb): New function.
1393 (extract_nps_bitop_mod4_msb): New function.
1394 (insert_nps_bitop_mod4_lsb): New function.
1395 (extract_nps_bitop_mod4_lsb): New function.
1396 (insert_nps_bitop_dst_pos3_pos4): New function.
1397 (extract_nps_bitop_dst_pos3_pos4): New function.
1398 (insert_nps_bitop_ins_ext): New function.
1399 (extract_nps_bitop_ins_ext): New function.
1400 (arc_operands): Add new operands.
1401 (arc_long_opcodes): New global array.
1402 (arc_num_long_opcodes): New global.
1403 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1404
1fe0971e
TS		 14052016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1406
1407 * nds32-asm.h: Add extern "C".
1408 * sh-opc.h: Likewise.
1409
315f180f
GM		 14102016-06-01 Graham Markall <graham.markall@embecosm.com>
1411
1412 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1413 0,b,limm to the rflt instruction.
1414
a2b5fccc
TS		 14152016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1416
1417 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1418 constant.
1419
0cbd0046
L		 14202016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1421
1422 PR gas/20145
1423 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1424 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1425 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1426 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1427 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1428 * i386-init.h: Regenerated.
1429
1848e567
L		 14302016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1431
1432 PR gas/20145
1433 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1434 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1435 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1436 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1437 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1438 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1439 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1440 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1441 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1442 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1443 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1444 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1445 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1446 CpuRegMask for AVX512.
1447 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1448 and CpuRegMask.
1449 (set_bitfield_from_cpu_flag_init): New function.
1450 (set_bitfield): Remove const on f. Call
1451 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1452 * i386-opc.h (CpuRegMMX): New.
1453 (CpuRegXMM): Likewise.
1454 (CpuRegYMM): Likewise.
1455 (CpuRegZMM): Likewise.
1456 (CpuRegMask): Likewise.
1457 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1458 and cpuregmask.
1459 * i386-init.h: Regenerated.
1460 * i386-tbl.h: Likewise.
1461
e92bae62
L		 14622016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1463
1464 PR gas/20154
1465 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1466 (opcode_modifiers): Add AMD64 and Intel64.
1467 (main): Properly verify CpuMax.
1468 * i386-opc.h (CpuAMD64): Removed.
1469 (CpuIntel64): Likewise.
1470 (CpuMax): Set to CpuNo64.
1471 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1472 (AMD64): New.
1473 (Intel64): Likewise.
1474 (i386_opcode_modifier): Add amd64 and intel64.
1475 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1476 on call and jmp.
1477 * i386-init.h: Regenerated.
1478 * i386-tbl.h: Likewise.
1479
e89c5eaa
L		 14802016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1481
1482 PR gas/20154
1483 * i386-gen.c (main): Fail if CpuMax is incorrect.
1484 * i386-opc.h (CpuMax): Set to CpuIntel64.
1485 * i386-tbl.h: Regenerated.
1486
77d66e7b
NC		 14872016-05-27 Nick Clifton <nickc@redhat.com>
1488
1489 PR target/20150
1490 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1491 (msp430dis_opcode_unsigned): New function.
1492 (msp430dis_opcode_signed): New function.
1493 (msp430_singleoperand): Use the new opcode reading functions.
1494 Only disassenmble bytes if they were successfully read.
1495 (msp430_doubleoperand): Likewise.
1496 (msp430_branchinstr): Likewise.
1497 (msp430x_callx_instr): Likewise.
1498 (print_insn_msp430): Check that it is safe to read bytes before
1499 attempting disassembly. Use the new opcode reading functions.
1500
19dfcc89
PB		 15012016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1502
1503 * ppc-opc.c (CY): New define. Document it.
1504 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1505
f3ad7637
L		 15062016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1507
1508 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1509 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1510 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1511 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1512 CPU_ANY_AVX_FLAGS.
1513 * i386-init.h: Regenerated.
1514
f1360d58
L		 15152016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1516
1517 PR gas/20141
1518 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1519 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1520 * i386-init.h: Regenerated.
1521
293f5f65
L		 15222016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1523
1524 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1525 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1526 * i386-init.h: Regenerated.
1527
d9eca1df
CZ		 15282016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1529
1530 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1531 information.
1532 (print_insn_arc): Set insn_type information.
1533 * arc-opc.c (C_CC): Add F_CLASS_COND.
1534 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1535 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1536 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1537 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1538 (brne, brne_s, jeq_s, jne_s): Likewise.
1539
87789e08
CZ		 15402016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1541
1542 * arc-tbl.h (neg): New instruction variant.
1543
c810e0b8
CZ		 15442016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1545
1546 * arc-dis.c (find_format, find_format, get_auxreg)
1547 (print_insn_arc): Changed.
1548 * arc-ext.h (INSERT_XOP): Likewise.
1549
3d207518
TS		 15502016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1551
1552 * tic54x-dis.c (sprint_mmr): Adjust.
1553 * tic54x-opc.c: Likewise.
1554
514e58b7
AM		 15552016-05-19 Alan Modra <amodra@gmail.com>
1556
1557 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1558
e43de63c
AM		 15592016-05-19 Alan Modra <amodra@gmail.com>
1560
1561 * ppc-opc.c: Formatting.
1562 (NSISIGNOPT): Define.
1563 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1564
1401d2fe
MR		 15652016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1566
1567 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1568 replacing references to `micromips_ase' throughout.
1569 (_print_insn_mips): Don't use file-level microMIPS annotation to
1570 determine the disassembly mode with the symbol table.
1571
1178da44
PB		 15722016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1573
1574 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1575
8f4f9071
MF		 15762016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1577
1578 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1579 mips64r6.
1580 * mips-opc.c (D34): New macro.
1581 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1582
8bc52696
AF		 15832016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1584
1585 * i386-dis.c (prefix_table): Add RDPID instruction.
1586 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1587 (cpu_flags): Add RDPID bitfield.
1588 * i386-opc.h (enum): Add RDPID element.
1589 (i386_cpu_flags): Add RDPID field.
1590 * i386-opc.tbl: Add RDPID instruction.
1591 * i386-init.h: Regenerate.
1592 * i386-tbl.h: Regenerate.
1593
39d911fc
TP		 15942016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1595
1596 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1597 branch type of a symbol.
1598 (print_insn): Likewise.
1599
16a1fa25
TP		 16002016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1601
1602 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1603 Mainline Security Extensions instructions.
1604 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1605 Extensions instructions.
1606 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1607 instructions.
1608 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1609 special registers.
1610
d751b79e
JM		 16112016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1612
1613 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1614
945e0f82
CZ		 16152016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1616
1617 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1618 (arcExtMap_genOpcode): Likewise.
1619 * arc-opc.c (arg_32bit_rc): Define new variable.
1620 (arg_32bit_u6): Likewise.
1621 (arg_32bit_limm): Likewise.
1622
20f55f38
SN		 16232016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1624
1625 * aarch64-gen.c (VERIFIER): Define.
1626 * aarch64-opc.c (VERIFIER): Define.
1627 (verify_ldpsw): Use static linkage.
1628 * aarch64-opc.h (verify_ldpsw): Remove.
1629 * aarch64-tbl.h: Use VERIFIER for verifiers.
1630
4bd13cde
NC		 16312016-04-28 Nick Clifton <nickc@redhat.com>
1632
1633 PR target/19722
1634 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1635 * aarch64-opc.c (verify_ldpsw): New function.
1636 * aarch64-opc.h (verify_ldpsw): New prototype.
1637 * aarch64-tbl.h: Add initialiser for verifier field.
1638 (LDPSW): Set verifier to verify_ldpsw.
1639
c0f92bf9
L		 16402016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1641
1642 PR binutils/19983
1643 PR binutils/19984
1644 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1645 smaller than address size.
1646
e6c7cdec
TS		 16472016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1648
1649 * alpha-dis.c: Regenerate.
1650 * crx-dis.c: Likewise.
1651 * disassemble.c: Likewise.
1652 * epiphany-opc.c: Likewise.
1653 * fr30-opc.c: Likewise.
1654 * frv-opc.c: Likewise.
1655 * ip2k-opc.c: Likewise.
1656 * iq2000-opc.c: Likewise.
1657 * lm32-opc.c: Likewise.
1658 * lm32-opinst.c: Likewise.
1659 * m32c-opc.c: Likewise.
1660 * m32r-opc.c: Likewise.
1661 * m32r-opinst.c: Likewise.
1662 * mep-opc.c: Likewise.
1663 * mt-opc.c: Likewise.
1664 * or1k-opc.c: Likewise.
1665 * or1k-opinst.c: Likewise.
1666 * tic80-opc.c: Likewise.
1667 * xc16x-opc.c: Likewise.
1668 * xstormy16-opc.c: Likewise.
1669
537aefaf
AB		 16702016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1671
1672 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1673 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1674 calcsd, and calcxd instructions.
1675 * arc-opc.c (insert_nps_bitop_size): Delete.
1676 (extract_nps_bitop_size): Delete.
1677 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1678 (extract_nps_qcmp_m3): Define.
1679 (extract_nps_qcmp_m2): Define.
1680 (extract_nps_qcmp_m1): Define.
1681 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1682 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1683 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1684 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1685 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1686 NPS_QCMP_M3.
1687
c8f785f2
AB		 16882016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1689
1690 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1691
6fd8e7c2
L		 16922016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1693
1694 * Makefile.in: Regenerated with automake 1.11.6.
1695 * aclocal.m4: Likewise.
1696
4b0c052e
AB		 16972016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1698
1699 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1700 instructions.
1701 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1702 (extract_nps_cmem_uimm16): New function.
1703 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1704
cb040366
AB		 17052016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1706
1707 * arc-dis.c (arc_insn_length): New function.
1708 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1709 (find_format): Change insnLen parameter to unsigned.
1710
accc0180
NC		 17112016-04-13 Nick Clifton <nickc@redhat.com>
1712
1713 PR target/19937
1714 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1715 the LD.B and LD.BU instructions.
1716
f36e33da
CZ		 17172016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1718
1719 * arc-dis.c (find_format): Check for extension flags.
1720 (print_flags): New function.
1721 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1722 .extAuxRegister.
1723 * arc-ext.c (arcExtMap_coreRegName): Use
1724 LAST_EXTENSION_CORE_REGISTER.
1725 (arcExtMap_coreReadWrite): Likewise.
1726 (dump_ARC_extmap): Update printing.
1727 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1728 (arc_aux_regs): Add cpu field.
1729 * arc-regs.h: Add cpu field, lower case name aux registers.
1730
1c2e355e
CZ		 17312016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1732
1733 * arc-tbl.h: Add rtsc, sleep with no arguments.
1734
b99747ae
CZ		 17352016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1736
1737 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1738 Initialize.
1739 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1740 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1741 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1742 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1743 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1744 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1745 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1746 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1747 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1748 (arc_opcode arc_opcodes): Null terminate the array.
1749 (arc_num_opcodes): Remove.
1750 * arc-ext.h (INSERT_XOP): Define.
1751 (extInstruction_t): Likewise.
1752 (arcExtMap_instName): Delete.
1753 (arcExtMap_insn): New function.
1754 (arcExtMap_genOpcode): Likewise.
1755 * arc-ext.c (ExtInstruction): Remove.
1756 (create_map): Zero initialize instruction fields.
1757 (arcExtMap_instName): Remove.
1758 (arcExtMap_insn): New function.
1759 (dump_ARC_extmap): More info while debuging.
1760 (arcExtMap_genOpcode): New function.
1761 * arc-dis.c (find_format): New function.
1762 (print_insn_arc): Use find_format.
1763 (arc_get_disassembler): Enable dump_ARC_extmap only when
1764 debugging.
1765
92708cec
MR		 17662016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1767
1768 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1769 instruction bits out.
1770
a42a4f84
AB		 17712016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1772
1773 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1774 * arc-opc.c (arc_flag_operands): Add new flags.
1775 (arc_flag_classes): Add new classes.
1776
1328504b
AB		 17772016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1778
1779 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1780
820f03ff
AB		 17812016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1782
1783 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1784 encode1, rflt, crc16, and crc32 instructions.
1785 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1786 (arc_flag_classes): Add C_NPS_R.
1787 (insert_nps_bitop_size_2b): New function.
1788 (extract_nps_bitop_size_2b): Likewise.
1789 (insert_nps_bitop_uimm8): Likewise.
1790 (extract_nps_bitop_uimm8): Likewise.
1791 (arc_operands): Add new operand entries.
1792
8ddf6b2a
CZ		 17932016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1794
b99747ae
CZ		 1795 * arc-regs.h: Add a new subclass field. Add double assist
1796 accumulator register values.
1797 * arc-tbl.h: Use DPA subclass to mark the double assist
1798 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1799 * arc-opc.c (RSP): Define instead of SP.
1800 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1801
589a7d88
JW		 18022016-04-05 Jiong Wang <jiong.wang@arm.com>
1803
1804 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1805
0a191de9 18062016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1807
1808 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1809 NPS_R_SRC1.
1810
0a106562
AB		 18112016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1812
1813 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1814 issues. No functional changes.
1815
bd05ac5f
CZ		 18162016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1817
b99747ae
CZ		 1818 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1819 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1820 (RTT): Remove duplicate.
1821 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1822 (PCT_CONFIG*): Remove.
1823 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1824
9885948f
CZ		 18252016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1826
b99747ae 1827 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1828
f2dd8838
CZ		 18292016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1830
b99747ae
CZ		 1831 * arc-tbl.h (invld07): Remove.
1832 * arc-ext-tbl.h: New file.
1833 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1834 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1835
0d2f91fe
JK		 18362016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1837
1838 Fix -Wstack-usage warnings.
1839 * aarch64-dis.c (print_operands): Substitute size.
1840 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1841
a6b71f42
JM		 18422016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1843
1844 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1845 to get a proper diagnostic when an invalid ASR register is used.
1846
9780e045
NC		 18472016-03-22 Nick Clifton <nickc@redhat.com>
1848
1849 * configure: Regenerate.
1850
e23e8ebe
AB		 18512016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1852
1853 * arc-nps400-tbl.h: New file.
1854 * arc-opc.c: Add top level comment.
1855 (insert_nps_3bit_dst): New function.
1856 (extract_nps_3bit_dst): New function.
1857 (insert_nps_3bit_src2): New function.
1858 (extract_nps_3bit_src2): New function.
1859 (insert_nps_bitop_size): New function.
1860 (extract_nps_bitop_size): New function.
1861 (arc_flag_operands): Add nps400 entries.
1862 (arc_flag_classes): Add nps400 entries.
1863 (arc_operands): Add nps400 entries.
1864 (arc_opcodes): Add nps400 include.
1865
1ae8ab47
AB		 18662016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1867
1868 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1869 the new class enum values.
1870
8699fc3e
AB		 18712016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1872
1873 * arc-dis.c (print_insn_arc): Handle nps400.
1874
24740d83
AB		 18752016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1876
1877 * arc-opc.c (BASE): Delete.
1878
8678914f
NC		 18792016-03-18 Nick Clifton <nickc@redhat.com>
1880
1881 PR target/19721
1882 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1883 of MOV insn that aliases an ORR insn.
1884
cc933301
JW		 18852016-03-16 Jiong Wang <jiong.wang@arm.com>
1886
1887 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1888
f86f5863
TS		 18892016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1890
1891 * mcore-opc.h: Add const qualifiers.
1892 * microblaze-opc.h (struct op_code_struct): Likewise.
1893 * sh-opc.h: Likewise.
1894 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1895 (tic4x_print_op): Likewise.
1896
62de1c63
AM		 18972016-03-02 Alan Modra <amodra@gmail.com>
1898
d11698cd 1899 * or1k-desc.h: Regenerate.
62de1c63 1900 * fr30-ibld.c: Regenerate.
c697cf0b 1901 * rl78-decode.c: Regenerate.
62de1c63 1902
020efce5
NC		 19032016-03-01 Nick Clifton <nickc@redhat.com>
1904
1905 PR target/19747
1906 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1907
b0c11777
RL		 19082016-02-24 Renlin Li <renlin.li@arm.com>
1909
1910 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1911 (print_insn_coprocessor): Support fp16 instructions.
1912
3e309328
RL		 19132016-02-24 Renlin Li <renlin.li@arm.com>
1914
1915 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1916 vminnm, vrint(mpna).
1917
8afc7bea
RL		 19182016-02-24 Renlin Li <renlin.li@arm.com>
1919
1920 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1921 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1922
4fd7268a
L		 19232016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1924
1925 * i386-dis.c (print_insn): Parenthesize expression to prevent
1926 truncated addresses.
1927 (OP_J): Likewise.
1928
4670103e
CZ		 19292016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1930 Janek van Oirschot <jvanoirs@synopsys.com>
1931
b99747ae
CZ		 1932 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1933 variable.
4670103e 1934
c1d9289f
NC		 19352016-02-04 Nick Clifton <nickc@redhat.com>
1936
1937 PR target/19561
1938 * msp430-dis.c (print_insn_msp430): Add a special case for
1939 decoding an RRC instruction with the ZC bit set in the extension
1940 word.
1941
a143b004
AB		 19422016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1943
1944 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1945 * epiphany-ibld.c: Regenerate.
1946 * fr30-ibld.c: Regenerate.
1947 * frv-ibld.c: Regenerate.
1948 * ip2k-ibld.c: Regenerate.
1949 * iq2000-ibld.c: Regenerate.
1950 * lm32-ibld.c: Regenerate.
1951 * m32c-ibld.c: Regenerate.
1952 * m32r-ibld.c: Regenerate.
1953 * mep-ibld.c: Regenerate.
1954 * mt-ibld.c: Regenerate.
1955 * or1k-ibld.c: Regenerate.
1956 * xc16x-ibld.c: Regenerate.
1957 * xstormy16-ibld.c: Regenerate.
1958
b89807c6
AB		 19592016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1960
1961 * epiphany-dis.c: Regenerated from latest cpu files.
1962
d8c823c8
MM		 19632016-02-01 Michael McConville <mmcco@mykolab.com>
1964
1965 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1966 test bit.
1967
5bc5ae88
RL		 19682016-01-25 Renlin Li <renlin.li@arm.com>
1969
1970 * arm-dis.c (mapping_symbol_for_insn): New function.
1971 (find_ifthen_state): Call mapping_symbol_for_insn().
1972
0bff6e2d
MW		 19732016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1974
1975 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1976 of MSR UAO immediate operand.
1977
100b4f2e
MR		 19782016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1979
1980 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1981 instruction support.
1982
5c14705f
AM		 19832016-01-17 Alan Modra <amodra@gmail.com>
1984
1985 * configure: Regenerate.
1986
4d82fe66
NC		 19872016-01-14 Nick Clifton <nickc@redhat.com>
1988
1989 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1990 instructions that can support stack pointer operations.
1991 * rl78-decode.c: Regenerate.
1992 * rl78-dis.c: Fix display of stack pointer in MOVW based
1993 instructions.
1994
651657fa
MW		 19952016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1996
1997 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1998 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1999 erxtatus_el1 and erxaddr_el1.
2000
105bde57
MW		 20012016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2002
2003 * arm-dis.c (arm_opcodes): Add "esb".
2004 (thumb_opcodes): Likewise.
2005
afa8d405
PB		 20062016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2007
2008 * ppc-opc.c <xscmpnedp>: Delete.
2009 <xvcmpnedp>: Likewise.
2010 <xvcmpnedp.>: Likewise.
2011 <xvcmpnesp>: Likewise.
2012 <xvcmpnesp.>: Likewise.
2013
83c3256e
AS		 20142016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2015
2016 PR gas/13050
2017 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2018 addition to ISA_A.
2019
6f2750fe
AM		 20202016-01-01 Alan Modra <amodra@gmail.com>
2021
2022 Update year range in copyright notice of all files.
2023
3499769a
AM		 2024For older changes see ChangeLog-2015
2025\f
2026Copyright (C) 2016 Free Software Foundation, Inc.
2027
2028Copying and distribution of this file, with or without modification,
2029are permitted in any medium without royalty provided the copyright
2030notice and this notice are preserved.
2031
2032Local Variables:
2033mode: change-log
2034left-margin: 8
2035fill-column: 74
2036version-control: never
2037End:
GDB Binutils - Deliverables
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