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Add SIGRIE instruction for MIPS R6
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
75fb7498
RS		 12015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
2
3 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
4
36aed29d
AP		 52015-08-07 Amit Pawar <Amit.Pawar@amd.com>
6
7 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
8 * i386-init.h: Regenerated.
9
a8484f96
L		 102015-07-30 H.J. Lu <hongjiu.lu@intel.com>
11
12 PR binutils/13571
13 * i386-dis.c (MOD_0FC3): New.
14 (PREFIX_0FC3): Renamed to ...
15 (PREFIX_MOD_0_0FC3): This.
16 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
17 (prefix_table): Replace Ma with Ev on movntiS.
18 (mod_table): Add MOD_0FC3.
19
37a42ee9
L		 202015-07-27 H.J. Lu <hongjiu.lu@intel.com>
21
22 * configure: Regenerated.
23
070fe95d
AM		 242015-07-23 Alan Modra <amodra@gmail.com>
25
26 PR 18708
27 * i386-dis.c (get64): Avoid signed integer overflow.
28
20c2a615
L		 292015-07-22 Alexander Fomin <alexander.fomin@intel.com>
30
31 PR binutils/18631
32 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
33 "EXEvexHalfBcstXmmq" for the second operand.
34 (EVEX_W_0F79_P_2): Likewise.
35 (EVEX_W_0F7A_P_2): Likewise.
36 (EVEX_W_0F7B_P_2): Likewise.
37
6f1c2142
AM		 382015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
39
40 * arm-dis.c (print_insn_coprocessor): Added support for quarter
41 float bitfield format.
42 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
43 quarter float bitfield format.
44
8a643cc3
L		 452015-07-14 H.J. Lu <hongjiu.lu@intel.com>
46
47 * configure: Regenerated.
48
ef5a96d5
AM		 492015-07-03 Alan Modra <amodra@gmail.com>
50
51 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
52 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
53 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
54
c8c8175b
SL		 552015-07-01 Sandra Loosemore <sandra@codesourcery.com>
56 Cesar Philippidis <cesar@codesourcery.com>
57
58 * nios2-dis.c (nios2_extract_opcode): New.
59 (nios2_disassembler_state): New.
60 (nios2_find_opcode_hash): Use mach parameter to select correct
61 disassembler state.
62 (nios2_print_insn_arg): Extend to support new R2 argument letters
63 and formats.
64 (print_insn_nios2): Check for 16-bit instruction at end of memory.
65 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
66 (NIOS2_NUM_OPCODES): Rename to...
67 (NIOS2_NUM_R1_OPCODES): This.
68 (nios2_r2_opcodes): New.
69 (NIOS2_NUM_R2_OPCODES): New.
70 (nios2_num_r2_opcodes): New.
71 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
72 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
73 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
74 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
75 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
76
9916071f
AP		 772015-06-30 Amit Pawar <Amit.Pawar@amd.com>
78
79 * i386-dis.c (OP_Mwaitx): New.
80 (rm_table): Add monitorx/mwaitx.
81 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
82 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
83 (operand_type_init): Add CpuMWAITX.
84 * i386-opc.h (CpuMWAITX): New.
85 (i386_cpu_flags): Add cpumwaitx.
86 * i386-opc.tbl: Add monitorx and mwaitx.
87 * i386-init.h: Regenerated.
88 * i386-tbl.h: Likewise.
89
7b934113
PB		 902015-06-22 Peter Bergner <bergner@vnet.ibm.com>
91
92 * ppc-opc.c (insert_ls): Test for invalid LS operands.
93 (insert_esync): New function.
94 (LS, WC): Use insert_ls.
95 (ESYNC): Use insert_esync.
96
bdc4de1b
NC		 972015-06-22 Nick Clifton <nickc@redhat.com>
98
99 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
100 requested region lies beyond it.
101 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
102 looking for 32-bit insns.
103 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
104 data.
105 * sh-dis.c (print_insn_sh): Likewise.
106 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
107 blocks of instructions.
108 * vax-dis.c (print_insn_vax): Check that the requested address
109 does not clash with the stop_vma.
110
11a0cf2e
PB		 1112015-06-19 Peter Bergner <bergner@vnet.ibm.com>
112
070fe95d 113 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 114 * ppc-opc.c (FXM4): Add non-zero optional value.
115 (TBR): Likewise.
116 (SXL): Likewise.
117 (insert_fxm): Handle new default operand value.
118 (extract_fxm): Likewise.
119 (insert_tbr): Likewise.
120 (extract_tbr): Likewise.
121
bdfa8b95
MW		 1222015-06-16 Matthew Wahab <matthew.wahab@arm.com>
123
124 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
125
24b4cf66
SN		 1262015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
127
128 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
129
99a2c561
PB		 1302015-06-12 Peter Bergner <bergner@vnet.ibm.com>
131
132 * ppc-opc.c: Add comment accidentally removed by old commit.
133 (MTMSRD_L): Delete.
134
40f77f82
AM		 1352015-06-04 Peter Bergner <bergner@vnet.ibm.com>
136
137 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
138
13be46a2
NC		 1392015-06-04 Nick Clifton <nickc@redhat.com>
140
141 PR 18474
142 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
143
ddfded2f
MW		 1442015-06-02 Matthew Wahab <matthew.wahab@arm.com>
145
146 * arm-dis.c (arm_opcodes): Add "setpan".
147 (thumb_opcodes): Add "setpan".
148
1af1dd51
MW		 1492015-06-02 Matthew Wahab <matthew.wahab@arm.com>
150
151 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
152 macros.
153
9e1f0fa7
MW		 1542015-06-02 Matthew Wahab <matthew.wahab@arm.com>
155
156 * aarch64-tbl.h (aarch64_feature_rdma): New.
157 (RDMA): New.
158 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
159 * aarch64-asm-2.c: Regenerate.
160 * aarch64-dis-2.c: Regenerate.
161 * aarch64-opc-2.c: Regenerate.
162
290806fd
MW		 1632015-06-02 Matthew Wahab <matthew.wahab@arm.com>
164
165 * aarch64-tbl.h (aarch64_feature_lor): New.
166 (LOR): New.
167 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
168 "stllrb", "stllrh".
169 * aarch64-asm-2.c: Regenerate.
170 * aarch64-dis-2.c: Regenerate.
171 * aarch64-opc-2.c: Regenerate.
172
f21cce2c
MW		 1732015-06-01 Matthew Wahab <matthew.wahab@arm.com>
174
175 * aarch64-opc.c (F_ARCHEXT): New.
176 (aarch64_sys_regs): Add "pan".
177 (aarch64_sys_reg_supported_p): New.
178 (aarch64_pstatefields): Add "pan".
179 (aarch64_pstatefield_supported_p): New.
180
d194d186
JB		 1812015-06-01 Jan Beulich <jbeulich@suse.com>
182
183 * i386-tbl.h: Regenerate.
184
3a8547d2
JB		 1852015-06-01 Jan Beulich <jbeulich@suse.com>
186
187 * i386-dis.c (print_insn): Swap rounding mode specifier and
188 general purpose register in Intel mode.
189
015c54d5
JB		 1902015-06-01 Jan Beulich <jbeulich@suse.com>
191
192 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
193 * i386-tbl.h: Regenerate.
194
071f0063
L		 1952015-05-18 H.J. Lu <hongjiu.lu@intel.com>
196
197 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
198 * i386-init.h: Regenerated.
199
5db04b09
L		 2002015-05-15 H.J. Lu <hongjiu.lu@intel.com>
201
202 PR binutis/18386
203 * i386-dis.c: Add comments for '@'.
204 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
205 (enum x86_64_isa): New.
206 (isa64): Likewise.
207 (print_i386_disassembler_options): Add amd64 and intel64.
208 (print_insn): Handle amd64 and intel64.
209 (putop): Handle '@'.
210 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
211 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
212 * i386-opc.h (AMD64): New.
213 (CpuIntel64): Likewise.
214 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
215 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
216 Mark direct call/jmp without Disp16|Disp32 as Intel64.
217 * i386-init.h: Regenerated.
218 * i386-tbl.h: Likewise.
219
4bc0608a
PB		 2202015-05-14 Peter Bergner <bergner@vnet.ibm.com>
221
222 * ppc-opc.c (IH) New define.
223 (powerpc_opcodes) <wait>: Do not enable for POWER7.
224 <tlbie>: Add RS operand for POWER7.
225 <slbia>: Add IH operand for POWER6.
226
70cead07
L		 2272015-05-11 H.J. Lu <hongjiu.lu@intel.com>
228
229 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
230 direct branch.
231 (jmp): Likewise.
232 * i386-tbl.h: Regenerated.
233
7b6d09fb
L		 2342015-05-11 H.J. Lu <hongjiu.lu@intel.com>
235
236 * configure.ac: Support bfd_iamcu_arch.
237 * disassemble.c (disassembler): Support bfd_iamcu_arch.
238 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
239 CPU_IAMCU_COMPAT_FLAGS.
240 (cpu_flags): Add CpuIAMCU.
241 * i386-opc.h (CpuIAMCU): New.
242 (i386_cpu_flags): Add cpuiamcu.
243 * configure: Regenerated.
244 * i386-init.h: Likewise.
245 * i386-tbl.h: Likewise.
246
31955f99
L		 2472015-05-08 H.J. Lu <hongjiu.lu@intel.com>
248
249 PR binutis/18386
250 * i386-dis.c (X86_64_E8): New.
251 (X86_64_E9): Likewise.
252 Update comments on 'T', 'U', 'V'. Add comments for '^'.
253 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
254 (x86_64_table): Add X86_64_E8 and X86_64_E9.
255 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
256 (putop): Handle '^'.
257 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
258 REX_W.
259
0952813b
DD		 2602015-04-30 DJ Delorie <dj@redhat.com>
261
262 * disassemble.c (disassembler): Choose suitable disassembler based
263 on E_ABI.
264 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
265 it to decode mul/div insns.
266 * rl78-decode.c: Regenerate.
267 * rl78-dis.c (print_insn_rl78): Rename to...
268 (print_insn_rl78_common): ...this, take ISA parameter.
269 (print_insn_rl78): New.
270 (print_insn_rl78_g10): New.
271 (print_insn_rl78_g13): New.
272 (print_insn_rl78_g14): New.
273 (rl78_get_disassembler): New.
274
f9d3ecaa
NC		 2752015-04-29 Nick Clifton <nickc@redhat.com>
276
277 * po/fr.po: Updated French translation.
278
4fff86c5
PB		 2792015-04-27 Peter Bergner <bergner@vnet.ibm.com>
280
281 * ppc-opc.c (DCBT_EO): New define.
282 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
283 <lharx>: Likewise.
284 <stbcx.>: Likewise.
285 <sthcx.>: Likewise.
286 <waitrsv>: Do not enable for POWER7 and later.
287 <waitimpl>: Likewise.
288 <dcbt>: Default to the two operand form of the instruction for all
289 "old" cpus. For "new" cpus, use the operand ordering that matches
290 whether the cpu is server or embedded.
291 <dcbtst>: Likewise.
292
3b78cfe1
AK		 2932015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
294
295 * s390-opc.c: New instruction type VV0UU2.
296 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
297 and WFC.
298
04d824a4
JB		 2992015-04-23 Jan Beulich <jbeulich@suse.com>
300
301 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
302 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
303 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
304 (vfpclasspd, vfpclassps): Add %XZ.
305
09708981
L		 3062015-04-15 H.J. Lu <hongjiu.lu@intel.com>
307
308 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
309 (PREFIX_UD_REPZ): Likewise.
310 (PREFIX_UD_REPNZ): Likewise.
311 (PREFIX_UD_DATA): Likewise.
312 (PREFIX_UD_ADDR): Likewise.
313 (PREFIX_UD_LOCK): Likewise.
314
3888916d
L		 3152015-04-15 H.J. Lu <hongjiu.lu@intel.com>
316
317 * i386-dis.c (prefix_requirement): Removed.
318 (print_insn): Don't set prefix_requirement. Check
319 dp->prefix_requirement instead of prefix_requirement.
320
f24bcbaa
L		 3212015-04-15 H.J. Lu <hongjiu.lu@intel.com>
322
323 PR binutils/17898
324 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
325 (PREFIX_MOD_0_0FC7_REG_6): This.
326 (PREFIX_MOD_3_0FC7_REG_6): New.
327 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
328 (prefix_table): Replace PREFIX_0FC7_REG_6 with
329 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
330 PREFIX_MOD_3_0FC7_REG_7.
331 (mod_table): Replace PREFIX_0FC7_REG_6 with
332 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
333 PREFIX_MOD_3_0FC7_REG_7.
334
507bd325
L		 3352015-04-15 H.J. Lu <hongjiu.lu@intel.com>
336
337 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
338 (PREFIX_MANDATORY_REPNZ): Likewise.
339 (PREFIX_MANDATORY_DATA): Likewise.
340 (PREFIX_MANDATORY_ADDR): Likewise.
341 (PREFIX_MANDATORY_LOCK): Likewise.
342 (PREFIX_MANDATORY): Likewise.
343 (PREFIX_UD_SHIFT): Set to 8
344 (PREFIX_UD_REPZ): Updated.
345 (PREFIX_UD_REPNZ): Likewise.
346 (PREFIX_UD_DATA): Likewise.
347 (PREFIX_UD_ADDR): Likewise.
348 (PREFIX_UD_LOCK): Likewise.
349 (PREFIX_IGNORED_SHIFT): New.
350 (PREFIX_IGNORED_REPZ): Likewise.
351 (PREFIX_IGNORED_REPNZ): Likewise.
352 (PREFIX_IGNORED_DATA): Likewise.
353 (PREFIX_IGNORED_ADDR): Likewise.
354 (PREFIX_IGNORED_LOCK): Likewise.
355 (PREFIX_OPCODE): Likewise.
356 (PREFIX_IGNORED): Likewise.
357 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
358 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
359 (three_byte_table): Likewise.
360 (mod_table): Likewise.
361 (mandatory_prefix): Renamed to ...
362 (prefix_requirement): This.
363 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
364 Update PREFIX_90 entry.
365 (get_valid_dis386): Check prefix_requirement to see if a prefix
366 should be ignored.
367 (print_insn): Replace mandatory_prefix with prefix_requirement.
368
f0fba320
RL		 3692015-04-15 Renlin Li <renlin.li@arm.com>
370
371 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
372 use it for ssat and ssat16.
373 (print_insn_thumb32): Add handle case for 'D' control code.
374
bf890a93
IT		 3752015-04-06 Ilya Tocar <ilya.tocar@intel.com>
376 H.J. Lu <hongjiu.lu@intel.com>
377
378 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
379 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
380 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
381 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
382 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
383 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
384 Fill prefix_requirement field.
385 (struct dis386): Add prefix_requirement field.
386 (dis386): Fill prefix_requirement field.
387 (dis386_twobyte): Ditto.
388 (twobyte_has_mandatory_prefix_: Remove.
389 (reg_table): Fill prefix_requirement field.
390 (prefix_table): Ditto.
391 (x86_64_table): Ditto.
392 (three_byte_table): Ditto.
393 (xop_table): Ditto.
394 (vex_table): Ditto.
395 (vex_len_table): Ditto.
396 (vex_w_table): Ditto.
397 (mod_table): Ditto.
398 (bad_opcode): Ditto.
399 (print_insn): Use prefix_requirement.
400 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
401 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
402 (float_reg): Ditto.
403
2f783c1f
MF		 4042015-03-30 Mike Frysinger <vapier@gentoo.org>
405
406 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
407
b9d94d62
L		 4082015-03-29 H.J. Lu <hongjiu.lu@intel.com>
409
410 * Makefile.in: Regenerated.
411
27c49e9a
AB		 4122015-03-25 Anton Blanchard <anton@samba.org>
413
414 * ppc-dis.c (disassemble_init_powerpc): Only initialise
415 powerpc_opcd_indices and vle_opcd_indices once.
416
c4e676f1
AB		 4172015-03-25 Anton Blanchard <anton@samba.org>
418
419 * ppc-opc.c (powerpc_opcodes): Add slbfee.
420
823d2571
TG		 4212015-03-24 Terry Guo <terry.guo@arm.com>
422
423 * arm-dis.c (opcode32): Updated to use new arm feature struct.
424 (opcode16): Likewise.
425 (coprocessor_opcodes): Replace bit with feature struct.
426 (neon_opcodes): Likewise.
427 (arm_opcodes): Likewise.
428 (thumb_opcodes): Likewise.
429 (thumb32_opcodes): Likewise.
430 (print_insn_coprocessor): Likewise.
431 (print_insn_arm): Likewise.
432 (select_arm_features): Follow new feature struct.
433
029f3522
GG		 4342015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
435
436 * i386-dis.c (rm_table): Add clzero.
437 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
438 Add CPU_CLZERO_FLAGS.
439 (cpu_flags): Add CpuCLZERO.
440 * i386-opc.h: Add CpuCLZERO.
441 * i386-opc.tbl: Add clzero.
442 * i386-init.h: Re-generated.
443 * i386-tbl.h: Re-generated.
444
6914869a
AB		 4452015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
446
447 * mips-opc.c (decode_mips_operand): Fix constraint issues
448 with u and y operands.
449
21e20815
AB		 4502015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
451
452 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
453
6b1d7593
AK		 4542015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
455
456 * s390-opc.c: Add new IBM z13 instructions.
457 * s390-opc.txt: Likewise.
458
c8f89a34
JW		 4592015-03-10 Renlin Li <renlin.li@arm.com>
460
461 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
462 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
463 related alias.
464 * aarch64-asm-2.c: Regenerate.
465 * aarch64-dis-2.c: Likewise.
466 * aarch64-opc-2.c: Likewise.
467
d8282f0e
JW		 4682015-03-03 Jiong Wang <jiong.wang@arm.com>
469
470 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
471
ac994365
OE		 4722015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
473
474 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
475 arch_sh_up.
476 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
477 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
478
fd63f640
V		 4792015-02-23 Vinay <Vinay.G@kpit.com>
480
481 * rl78-decode.opc (MOV): Added space between two operands for
482 'mov' instruction in index addressing mode.
483 * rl78-decode.c: Regenerate.
484
f63c1776
PA		 4852015-02-19 Pedro Alves <palves@redhat.com>
486
487 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
488
07774fcc
PA		 4892015-02-10 Pedro Alves <palves@redhat.com>
490 Tom Tromey <tromey@redhat.com>
491
492 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
493 microblaze_and, microblaze_xor.
494 * microblaze-opc.h (opcodes): Adjust.
495
3f8107ab
AM		 4962015-01-28 James Bowman <james.bowman@ftdichip.com>
497
498 * Makefile.am: Add FT32 files.
499 * configure.ac: Handle FT32.
500 * disassemble.c (disassembler): Call print_insn_ft32.
501 * ft32-dis.c: New file.
502 * ft32-opc.c: New file.
503 * Makefile.in: Regenerate.
504 * configure: Regenerate.
505 * po/POTFILES.in: Regenerate.
506
e5fe4957
KLC		 5072015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
508
509 * nds32-asm.c (keyword_sr): Add new system registers.
510
1e2e8c52
AK		 5112015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
512
513 * s390-dis.c (s390_extract_operand): Support vector register
514 operands.
515 (s390_print_insn_with_opcode): Support new operands types and add
516 new handling of optional operands.
517 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
518 and include opcode/s390.h instead.
519 (struct op_struct): New field `flags'.
520 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
521 (dumpTable): Dump flags.
522 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
523 string.
524 * s390-opc.c: Add new operands types, instruction formats, and
525 instruction masks.
526 (s390_opformats): Add new formats for .insn.
527 * s390-opc.txt: Add new instructions.
528
b90efa5b 5292015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 530
b90efa5b 531 Update year range in copyright notice of all files.
bffb6004 532
b90efa5b 533For older changes see ChangeLog-2014
252b5132 534\f
b90efa5b 535Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 536
537Copying and distribution of this file, with or without modification,
538are permitted in any medium without royalty provided the copyright
539notice and this notice are preserved.
540
252b5132 541Local Variables:
2f6d2f85
NC		 542mode: change-log
543left-margin: 8
544fill-column: 74
252b5132
RH		 545version-control: never
546End:
GDB Binutils - Deliverables
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