projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| a680de9a PB |
1 | 2015-11-11 Alan Modra <amodra@gmail.com> |
| 2 | Peter Bergner <bergner@vnet.ibm.com> | |
| 3 | ||
| 4 | * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. | |
| 5 | Add PPC_OPCODE_VSX3 to the vsx entry. | |
| 6 | (powerpc_init_dialect): Set default dialect to power9. | |
| 7 | * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, | |
| 8 | insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, | |
| 9 | extract_l1 insert_xtq6, extract_xtq6): New static functions. | |
| 10 | (insert_esync): Test for illegal L operand value. | |
| 11 | (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, | |
| 12 | XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, | |
| 13 | XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, | |
| 14 | XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, | |
| 15 | PPCVSX3): New defines. | |
| 16 | (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu, | |
| 17 | fcmpo, ftdiv, ftsqrt>: Use XBF_MASK. | |
| 18 | <mcrxr>: Use XBFRARB_MASK. | |
| 19 | <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq., | |
| 20 | bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc., | |
| 21 | cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first, | |
| 22 | cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx, | |
| 23 | lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll, | |
| 24 | lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw, | |
| 25 | modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last, | |
| 26 | rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx, | |
| 27 | stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx, | |
| 28 | subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh, | |
| 29 | vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., | |
| 30 | vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd, | |
| 31 | vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d, | |
| 32 | vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx, | |
| 33 | vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq, | |
| 34 | vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd, | |
| 35 | vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait, | |
| 36 | xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp, | |
| 37 | xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp, | |
| 38 | xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz, | |
| 39 | xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp, | |
| 40 | xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp, | |
| 41 | xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo, | |
| 42 | xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo, | |
| 43 | xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo, | |
| 44 | xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp, | |
| 45 | xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp, | |
| 46 | xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp, | |
| 47 | xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw, | |
| 48 | xxinsertw, xxperm, xxpermr, xxspltib>: New instructions. | |
| 49 | <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9. | |
| 50 | <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands. | |
| 51 | ||
| 854eb72b NC |
52 | 2015-11-02 Nick Clifton <nickc@redhat.com> |
| 53 | ||
| 54 | * rx-decode.opc (rx_decode_opcode): Decode extra NOP | |
| 55 | instructions. | |
| 56 | * rx-decode.c: Regenerate. | |
| 57 | ||
| e292aa7a NC |
58 | 2015-11-02 Nick Clifton <nickc@redhat.com> |
| 59 | ||
| 60 | * rx-decode.opc (rx_disp): If the displacement is zero, set the | |
| 61 | type to RX_Operand_Zero_Indirect. | |
| 62 | * rx-decode.c: Regenerate. | |
| 63 | * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect. | |
| 64 | ||
| 43cdf5ae YQ |
65 | 2015-10-28 Yao Qi <yao.qi@linaro.org> |
| 66 | ||
| 67 | * aarch64-dis.c (aarch64_decode_insn): Add one argument | |
| 68 | noaliases_p. Update comments. Pass noaliases_p rather than | |
| 69 | no_aliases to aarch64_opcode_decode. | |
| 70 | (print_insn_aarch64_word): Pass no_aliases to | |
| 71 | aarch64_decode_insn. | |
| 72 | ||
| c2f28758 VK |
73 | 2015-10-27 Vinay <Vinay.G@kpit.com> |
| 74 | ||
| 75 | PR binutils/19159 | |
| 76 | * rl78-decode.opc (MOV): Added offset to DE register in index | |
| 77 | addressing mode. | |
| 78 | * rl78-decode.c: Regenerate. | |
| 79 | ||
| 46662804 VK |
80 | 2015-10-27 Vinay Kumar <vinay.g@kpit.com> |
| 81 | ||
| 82 | PR binutils/19158 | |
| 83 | * rl78-decode.opc: Add 's' print operator to instructions that | |
| 84 | access system registers. | |
| 85 | * rl78-decode.c: Regenerate. | |
| 86 | * rl78-dis.c (print_insn_rl78_common): Decode all system | |
| 87 | registers. | |
| 88 | ||
| 02f12cd4 VK |
89 | 2015-10-27 Vinay Kumar <vinay.g@kpit.com> |
| 90 | ||
| 91 | PR binutils/19157 | |
| 92 | * rl78-decode.opc: Add 'a' print operator to mov instructions | |
| 93 | using stack pointer plus index addressing. | |
| 94 | * rl78-decode.c: Regenerate. | |
| 95 | ||
| 485f23cf AK |
96 | 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| 97 | ||
| 98 | * s390-opc.c: Fix comment. | |
| 99 | * s390-opc.txt: Change instruction type for troo, trot, trto, and | |
| 100 | trtt to RRF_U0RER since the second parameter does not need to be a | |
| 101 | register pair. | |
| 102 | ||
| 3f94e60d NC |
103 | 2015-10-08 Nick Clifton <nickc@redhat.com> |
| 104 | ||
| 105 | * arc-dis.c (print_insn_arc): Initiallise insn array. | |
| 106 | ||
| 875880c6 YQ |
107 | 2015-10-07 Yao Qi <yao.qi@linaro.org> |
| 108 | ||
| 109 | * aarch64-dis.c (aarch64_ext_sysins_op): Access field | |
| 110 | 'name' rather than 'template'. | |
| 111 | * aarch64-opc.c (aarch64_print_operand): Likewise. | |
| 112 | ||
| 886a2506 NC |
113 | 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com> |
| 114 | ||
| 115 | * arc-dis.c: Revamped file for ARC support | |
| 116 | * arc-dis.h: Likewise. | |
| 117 | * arc-ext.c: Likewise. | |
| 118 | * arc-ext.h: Likewise. | |
| 119 | * arc-opc.c: Likewise. | |
| 120 | * arc-fxi.h: New file. | |
| 121 | * arc-regs.h: Likewise. | |
| 122 | * arc-tbl.h: Likewise. | |
| 123 | ||
| 36f4aab1 YQ |
124 | 2015-10-02 Yao Qi <yao.qi@linaro.org> |
| 125 | ||
| 126 | * aarch64-dis.c (disas_aarch64_insn): Remove static. Change | |
| 127 | argument insn type to aarch64_insn. Rename to ... | |
| 128 | (aarch64_decode_insn): ... it. | |
| 129 | (print_insn_aarch64_word): Caller updated. | |
| 130 | ||
| 7232d389 YQ |
131 | 2015-10-02 Yao Qi <yao.qi@linaro.org> |
| 132 | ||
| 133 | * aarch64-dis.c (disas_aarch64_insn): Remove argument PC. | |
| 134 | (print_insn_aarch64_word): Caller updated. | |
| 135 | ||
| 7ecc513a DV |
136 | 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com> |
| 137 | ||
| 138 | * s390-mkopc.c (main): Parse htm and vx flag. | |
| 139 | * s390-opc.txt: Mark instructions from the hardware transactional | |
| 140 | memory and vector facilities with the "htm"/"vx" flag. | |
| 141 | ||
| b08b78e7 NC |
142 | 2015-09-28 Nick Clifton <nickc@redhat.com> |
| 143 | ||
| 144 | * po/de.po: Updated German translation. | |
| 145 | ||
| 36f7a941 TR |
146 | 2015-09-28 Tom Rix <tom@bumblecow.com> |
| 147 | ||
| 148 | * ppc-opc.c (PPC500): Mark some opcodes as invalid | |
| 149 | ||
| b6518b38 NC |
150 | 2015-09-23 Nick Clifton <nickc@redhat.com> |
| 151 | ||
| 152 | * bfin-dis.c (fmtconst): Remove unnecessary call to the abs | |
| 153 | function. | |
| 154 | * tic30-dis.c (print_branch): Likewise. | |
| 155 | * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed | |
| 156 | value before left shifting. | |
| 157 | * fr30-ibld.c (fr30_cgen_extract_operand): Likewise. | |
| 158 | * hppa-dis.c (print_insn_hppa): Likewise. | |
| 159 | * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static | |
| 160 | array. | |
| 161 | * msp430-dis.c (msp430_singleoperand): Likewise. | |
| 162 | (msp430_doubleoperand): Likewise. | |
| 163 | (print_insn_msp430): Likewise. | |
| 164 | * nds32-asm.c (parse_operand): Likewise. | |
| 165 | * sh-opc.h (MASK): Likewise. | |
| 166 | * v850-dis.c (get_operand_value): Likewise. | |
| 167 | ||
| f04265ec NC |
168 | 2015-09-22 Nick Clifton <nickc@redhat.com> |
| 169 | ||
| 170 | * rx-decode.opc (bwl): Use RX_Bad_Size. | |
| 171 | (sbwl): Likewise. | |
| 172 | (ubwl): Likewise. Rename to ubw. | |
| 173 | (uBWL): Rename to uBW. | |
| 174 | Replace all references to uBWL with uBW. | |
| 175 | * rx-decode.c: Regenerate. | |
| 176 | * rx-dis.c (size_names): Add entry for RX_Bad_Size. | |
| 177 | (opsize_names): Likewise. | |
| 178 | (print_insn_rx): Detect and report RX_Bad_Size. | |
| 179 | ||
| 6dca4fd1 AB |
180 | 2015-09-22 Anton Blanchard <anton@samba.org> |
| 181 | ||
| 182 | * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl. | |
| 183 | ||
| 38074311 JM |
184 | 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 185 | ||
| 186 | * sparc-dis.c (print_insn_sparc): Handle the privileged register | |
| 187 | %pmcdper. | |
| 188 | ||
| 5f40e14d JS |
189 | 2015-08-24 Jan Stancek <jstancek@redhat.com> |
| 190 | ||
| 191 | * i386-dis.c (print_insn): Fix decoding of three byte operands. | |
| 192 | ||
| ab4e4ed5 AF |
193 | 2015-08-21 Alexander Fomin <alexander.fomin@intel.com> |
| 194 | ||
| 195 | PR binutils/18257 | |
| 196 | * i386-dis.c: Use MOD_TABLE for most of mask instructions. | |
| 197 | (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1, | |
| 198 | MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, | |
| 199 | MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, | |
| 200 | MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, | |
| 201 | MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, | |
| 202 | MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, | |
| 203 | MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, | |
| 204 | MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, | |
| 205 | MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, | |
| 206 | MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, | |
| 207 | MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, | |
| 208 | MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, | |
| 209 | MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
| 210 | MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
| 211 | MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
| 212 | MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
| 213 | MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, | |
| 214 | MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, | |
| 215 | MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, | |
| 216 | MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0, | |
| 217 | MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0, | |
| 218 | MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0, | |
| 219 | MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, | |
| 220 | MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, | |
| 221 | MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, | |
| 222 | MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, | |
| 223 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
| 224 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
| 225 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
| 226 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0. | |
| 227 | (vex_w_table): Replace terminals with MOD_TABLE entries for | |
| 228 | most of mask instructions. | |
| 229 | ||
| 919b75f7 AM |
230 | 2015-08-17 Alan Modra <amodra@gmail.com> |
| 231 | ||
| 232 | * cgen.sh: Trim trailing space from cgen output. | |
| 233 | * ia64-gen.c (print_dependency_table): Don't generate trailing space. | |
| 234 | (print_dis_table): Likewise. | |
| 235 | * opc2c.c (dump_lines): Likewise. | |
| 236 | (orig_filename): Warning fix. | |
| 237 | * ia64-asmtab.c: Regenerate. | |
| 238 | ||
| 4ab90a7a AV |
239 | 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 240 | ||
| 241 | * arm-dis.c (print_insn_arm): Disassembling for all targets V6 | |
| 242 | and higher with ARM instruction set will now mark the 26-bit | |
| 243 | versions of teq,tst,cmn and cmp as UNPREDICTABLE. | |
| 244 | (arm_opcodes): Fix for unpredictable nop being recognized as a | |
| 245 | teq. | |
| 246 | ||
| 40fc1451 SD |
247 | 2015-08-12 Simon Dardis <simon.dardis@imgtec.com> |
| 248 | ||
| 249 | * micromips-opc.c (micromips_opcodes): Re-order table so that move | |
| 250 | based on 'or' is first. | |
| 251 | * mips-opc.c (mips_builtin_opcodes): Ditto. | |
| 252 | ||
| 922c5db5 NC |
253 | 2015-08-11 Nick Clifton <nickc@redhat.com> |
| 254 | ||
| 255 | PR 18800 | |
| 256 | * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT | |
| 257 | instruction. | |
| 258 | ||
| 75fb7498 RS |
259 | 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com> |
| 260 | ||
| 261 | * mips-opc.c (mips_builtin_opcodes): Add "sigrie". | |
| 262 | ||
| 36aed29d AP |
263 | 2015-08-07 Amit Pawar <Amit.Pawar@amd.com> |
| 264 | ||
| 265 | * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS. | |
| 266 | * i386-init.h: Regenerated. | |
| 267 | ||
| a8484f96 L |
268 | 2015-07-30 H.J. Lu <hongjiu.lu@intel.com> |
| 269 | ||
| 270 | PR binutils/13571 | |
| 271 | * i386-dis.c (MOD_0FC3): New. | |
| 272 | (PREFIX_0FC3): Renamed to ... | |
| 273 | (PREFIX_MOD_0_0FC3): This. | |
| 274 | (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3. | |
| 275 | (prefix_table): Replace Ma with Ev on movntiS. | |
| 276 | (mod_table): Add MOD_0FC3. | |
| 277 | ||
| 37a42ee9 L |
278 | 2015-07-27 H.J. Lu <hongjiu.lu@intel.com> |
| 279 | ||
| 280 | * configure: Regenerated. | |
| 281 | ||
| 070fe95d AM |
282 | 2015-07-23 Alan Modra <amodra@gmail.com> |
| 283 | ||
| 284 | PR 18708 | |
| 285 | * i386-dis.c (get64): Avoid signed integer overflow. | |
| 286 | ||
| 20c2a615 L |
287 | 2015-07-22 Alexander Fomin <alexander.fomin@intel.com> |
| 288 | ||
| 289 | PR binutils/18631 | |
| 290 | * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with | |
| 291 | "EXEvexHalfBcstXmmq" for the second operand. | |
| 292 | (EVEX_W_0F79_P_2): Likewise. | |
| 293 | (EVEX_W_0F7A_P_2): Likewise. | |
| 294 | (EVEX_W_0F7B_P_2): Likewise. | |
| 295 | ||
| 6f1c2142 AM |
296 | 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com> |
| 297 | ||
| 298 | * arm-dis.c (print_insn_coprocessor): Added support for quarter | |
| 299 | float bitfield format. | |
| 300 | (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new | |
| 301 | quarter float bitfield format. | |
| 302 | ||
| 8a643cc3 L |
303 | 2015-07-14 H.J. Lu <hongjiu.lu@intel.com> |
| 304 | ||
| 305 | * configure: Regenerated. | |
| 306 | ||
| ef5a96d5 AM |
307 | 2015-07-03 Alan Modra <amodra@gmail.com> |
| 308 | ||
| 309 | * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*. | |
| 310 | * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add | |
| 311 | PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry. | |
| 312 | ||
| c8c8175b SL |
313 | 2015-07-01 Sandra Loosemore <sandra@codesourcery.com> |
| 314 | Cesar Philippidis <cesar@codesourcery.com> | |
| 315 | ||
| 316 | * nios2-dis.c (nios2_extract_opcode): New. | |
| 317 | (nios2_disassembler_state): New. | |
| 318 | (nios2_find_opcode_hash): Use mach parameter to select correct | |
| 319 | disassembler state. | |
| 320 | (nios2_print_insn_arg): Extend to support new R2 argument letters | |
| 321 | and formats. | |
| 322 | (print_insn_nios2): Check for 16-bit instruction at end of memory. | |
| 323 | * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes. | |
| 324 | (NIOS2_NUM_OPCODES): Rename to... | |
| 325 | (NIOS2_NUM_R1_OPCODES): This. | |
| 326 | (nios2_r2_opcodes): New. | |
| 327 | (NIOS2_NUM_R2_OPCODES): New. | |
| 328 | (nios2_num_r2_opcodes): New. | |
| 329 | (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New. | |
| 330 | (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New. | |
| 331 | (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New. | |
| 332 | (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New. | |
| 333 | (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New. | |
| 334 | ||
| 9916071f AP |
335 | 2015-06-30 Amit Pawar <Amit.Pawar@amd.com> |
| 336 | ||
| 337 | * i386-dis.c (OP_Mwaitx): New. | |
| 338 | (rm_table): Add monitorx/mwaitx. | |
| 339 | * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS | |
| 340 | and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS. | |
| 341 | (operand_type_init): Add CpuMWAITX. | |
| 342 | * i386-opc.h (CpuMWAITX): New. | |
| 343 | (i386_cpu_flags): Add cpumwaitx. | |
| 344 | * i386-opc.tbl: Add monitorx and mwaitx. | |
| 345 | * i386-init.h: Regenerated. | |
| 346 | * i386-tbl.h: Likewise. | |
| 347 | ||
| 7b934113 PB |
348 | 2015-06-22 Peter Bergner <bergner@vnet.ibm.com> |
| 349 | ||
| 350 | * ppc-opc.c (insert_ls): Test for invalid LS operands. | |
| 351 | (insert_esync): New function. | |
| 352 | (LS, WC): Use insert_ls. | |
| 353 | (ESYNC): Use insert_esync. | |
| 354 | ||
| bdc4de1b NC |
355 | 2015-06-22 Nick Clifton <nickc@redhat.com> |
| 356 | ||
| 357 | * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the | |
| 358 | requested region lies beyond it. | |
| 359 | * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when | |
| 360 | looking for 32-bit insns. | |
| 361 | * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading | |
| 362 | data. | |
| 363 | * sh-dis.c (print_insn_sh): Likewise. | |
| 364 | * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading | |
| 365 | blocks of instructions. | |
| 366 | * vax-dis.c (print_insn_vax): Check that the requested address | |
| 367 | does not clash with the stop_vma. | |
| 368 | ||
| 11a0cf2e PB |
369 | 2015-06-19 Peter Bergner <bergner@vnet.ibm.com> |
| 370 | ||
| 070fe95d | 371 | * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value. |
| 11a0cf2e PB |
372 | * ppc-opc.c (FXM4): Add non-zero optional value. |
| 373 | (TBR): Likewise. | |
| 374 | (SXL): Likewise. | |
| 375 | (insert_fxm): Handle new default operand value. | |
| 376 | (extract_fxm): Likewise. | |
| 377 | (insert_tbr): Likewise. | |
| 378 | (extract_tbr): Likewise. | |
| 379 | ||
| bdfa8b95 MW |
380 | 2015-06-16 Matthew Wahab <matthew.wahab@arm.com> |
| 381 | ||
| 382 | * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1". | |
| 383 | ||
| 24b4cf66 SN |
384 | 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| 385 | ||
| 386 | * arm-dis.c (print_insn_coprocessor): Avoid negative shift. | |
| 387 | ||
| 99a2c561 PB |
388 | 2015-06-12 Peter Bergner <bergner@vnet.ibm.com> |
| 389 | ||
| 390 | * ppc-opc.c: Add comment accidentally removed by old commit. | |
| 391 | (MTMSRD_L): Delete. | |
| 392 | ||
| 40f77f82 AM |
393 | 2015-06-04 Peter Bergner <bergner@vnet.ibm.com> |
| 394 | ||
| 395 | * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic. | |
| 396 | ||
| 13be46a2 NC |
397 | 2015-06-04 Nick Clifton <nickc@redhat.com> |
| 398 | ||
| 399 | PR 18474 | |
| 400 | * msp430-dis.c (msp430_nooperands): Fix check for emulated insns. | |
| 401 | ||
| ddfded2f MW |
402 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
| 403 | ||
| 404 | * arm-dis.c (arm_opcodes): Add "setpan". | |
| 405 | (thumb_opcodes): Add "setpan". | |
| 406 | ||
| 1af1dd51 MW |
407 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
| 408 | ||
| 409 | * arm-dis.c (select_arm_features): Rework to avoid used of redefined | |
| 410 | macros. | |
| 411 | ||
| 9e1f0fa7 MW |
412 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
| 413 | ||
| 414 | * aarch64-tbl.h (aarch64_feature_rdma): New. | |
| 415 | (RDMA): New. | |
| 416 | (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions. | |
| 417 | * aarch64-asm-2.c: Regenerate. | |
| 418 | * aarch64-dis-2.c: Regenerate. | |
| 419 | * aarch64-opc-2.c: Regenerate. | |
| 420 | ||
| 290806fd MW |
421 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
| 422 | ||
| 423 | * aarch64-tbl.h (aarch64_feature_lor): New. | |
| 424 | (LOR): New. | |
| 425 | (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr", | |
| 426 | "stllrb", "stllrh". | |
| 427 | * aarch64-asm-2.c: Regenerate. | |
| 428 | * aarch64-dis-2.c: Regenerate. | |
| 429 | * aarch64-opc-2.c: Regenerate. | |
| 430 | ||
| f21cce2c MW |
431 | 2015-06-01 Matthew Wahab <matthew.wahab@arm.com> |
| 432 | ||
| 433 | * aarch64-opc.c (F_ARCHEXT): New. | |
| 434 | (aarch64_sys_regs): Add "pan". | |
| 435 | (aarch64_sys_reg_supported_p): New. | |
| 436 | (aarch64_pstatefields): Add "pan". | |
| 437 | (aarch64_pstatefield_supported_p): New. | |
| 438 | ||
| d194d186 JB |
439 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
| 440 | ||
| 441 | * i386-tbl.h: Regenerate. | |
| 442 | ||
| 3a8547d2 JB |
443 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
| 444 | ||
| 445 | * i386-dis.c (print_insn): Swap rounding mode specifier and | |
| 446 | general purpose register in Intel mode. | |
| 447 | ||
| 015c54d5 JB |
448 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
| 449 | ||
| 450 | * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. | |
| 451 | * i386-tbl.h: Regenerate. | |
| 452 | ||
| 071f0063 L |
453 | 2015-05-18 H.J. Lu <hongjiu.lu@intel.com> |
| 454 | ||
| 455 | * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp. | |
| 456 | * i386-init.h: Regenerated. | |
| 457 | ||
| 5db04b09 L |
458 | 2015-05-15 H.J. Lu <hongjiu.lu@intel.com> |
| 459 | ||
| 460 | PR binutis/18386 | |
| 461 | * i386-dis.c: Add comments for '@'. | |
| 462 | (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9. | |
| 463 | (enum x86_64_isa): New. | |
| 464 | (isa64): Likewise. | |
| 465 | (print_i386_disassembler_options): Add amd64 and intel64. | |
| 466 | (print_insn): Handle amd64 and intel64. | |
| 467 | (putop): Handle '@'. | |
| 468 | (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit. | |
| 469 | * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64. | |
| 470 | * i386-opc.h (AMD64): New. | |
| 471 | (CpuIntel64): Likewise. | |
| 472 | (i386_cpu_flags): Add cpuamd64 and cpuintel64. | |
| 473 | * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64. | |
| 474 | Mark direct call/jmp without Disp16|Disp32 as Intel64. | |
| 475 | * i386-init.h: Regenerated. | |
| 476 | * i386-tbl.h: Likewise. | |
| 477 | ||
| 4bc0608a PB |
478 | 2015-05-14 Peter Bergner <bergner@vnet.ibm.com> |
| 479 | ||
| 480 | * ppc-opc.c (IH) New define. | |
| 481 | (powerpc_opcodes) <wait>: Do not enable for POWER7. | |
| 482 | <tlbie>: Add RS operand for POWER7. | |
| 483 | <slbia>: Add IH operand for POWER6. | |
| 484 | ||
| 70cead07 L |
485 | 2015-05-11 H.J. Lu <hongjiu.lu@intel.com> |
| 486 | ||
| 487 | * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit | |
| 488 | direct branch. | |
| 489 | (jmp): Likewise. | |
| 490 | * i386-tbl.h: Regenerated. | |
| 491 | ||
| 7b6d09fb L |
492 | 2015-05-11 H.J. Lu <hongjiu.lu@intel.com> |
| 493 | ||
| 494 | * configure.ac: Support bfd_iamcu_arch. | |
| 495 | * disassemble.c (disassembler): Support bfd_iamcu_arch. | |
| 496 | * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and | |
| 497 | CPU_IAMCU_COMPAT_FLAGS. | |
| 498 | (cpu_flags): Add CpuIAMCU. | |
| 499 | * i386-opc.h (CpuIAMCU): New. | |
| 500 | (i386_cpu_flags): Add cpuiamcu. | |
| 501 | * configure: Regenerated. | |
| 502 | * i386-init.h: Likewise. | |
| 503 | * i386-tbl.h: Likewise. | |
| 504 | ||
| 31955f99 L |
505 | 2015-05-08 H.J. Lu <hongjiu.lu@intel.com> |
| 506 | ||
| 507 | PR binutis/18386 | |
| 508 | * i386-dis.c (X86_64_E8): New. | |
| 509 | (X86_64_E9): Likewise. | |
| 510 | Update comments on 'T', 'U', 'V'. Add comments for '^'. | |
| 511 | (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9. | |
| 512 | (x86_64_table): Add X86_64_E8 and X86_64_E9. | |
| 513 | (mod_table): Replace {T|} with ^ on Jcall/Jmp. | |
| 514 | (putop): Handle '^'. | |
| 515 | (OP_J): Ignore the operand size prefix in 64-bit. Don't check | |
| 516 | REX_W. | |
| 517 | ||
| 0952813b DD |
518 | 2015-04-30 DJ Delorie <dj@redhat.com> |
| 519 | ||
| 520 | * disassemble.c (disassembler): Choose suitable disassembler based | |
| 521 | on E_ABI. | |
| 522 | * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use | |
| 523 | it to decode mul/div insns. | |
| 524 | * rl78-decode.c: Regenerate. | |
| 525 | * rl78-dis.c (print_insn_rl78): Rename to... | |
| 526 | (print_insn_rl78_common): ...this, take ISA parameter. | |
| 527 | (print_insn_rl78): New. | |
| 528 | (print_insn_rl78_g10): New. | |
| 529 | (print_insn_rl78_g13): New. | |
| 530 | (print_insn_rl78_g14): New. | |
| 531 | (rl78_get_disassembler): New. | |
| 532 | ||
| f9d3ecaa NC |
533 | 2015-04-29 Nick Clifton <nickc@redhat.com> |
| 534 | ||
| 535 | * po/fr.po: Updated French translation. | |
| 536 | ||
| 4fff86c5 PB |
537 | 2015-04-27 Peter Bergner <bergner@vnet.ibm.com> |
| 538 | ||
| 539 | * ppc-opc.c (DCBT_EO): New define. | |
| 540 | (powerpc_opcodes) <lbarx>: Enable for POWER8 and later. | |
| 541 | <lharx>: Likewise. | |
| 542 | <stbcx.>: Likewise. | |
| 543 | <sthcx.>: Likewise. | |
| 544 | <waitrsv>: Do not enable for POWER7 and later. | |
| 545 | <waitimpl>: Likewise. | |
| 546 | <dcbt>: Default to the two operand form of the instruction for all | |
| 547 | "old" cpus. For "new" cpus, use the operand ordering that matches | |
| 548 | whether the cpu is server or embedded. | |
| 549 | <dcbtst>: Likewise. | |
| 550 | ||
| 3b78cfe1 AK |
551 | 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| 552 | ||
| 553 | * s390-opc.c: New instruction type VV0UU2. | |
| 554 | * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK, | |
| 555 | and WFC. | |
| 556 | ||
| 04d824a4 JB |
557 | 2015-04-23 Jan Beulich <jbeulich@suse.com> |
| 558 | ||
| 559 | * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ". | |
| 560 | * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq, | |
| 561 | vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY. | |
| 562 | (vfpclasspd, vfpclassps): Add %XZ. | |
| 563 | ||
| 09708981 L |
564 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
| 565 | ||
| 566 | * i386-dis.c (PREFIX_UD_SHIFT): Removed. | |
| 567 | (PREFIX_UD_REPZ): Likewise. | |
| 568 | (PREFIX_UD_REPNZ): Likewise. | |
| 569 | (PREFIX_UD_DATA): Likewise. | |
| 570 | (PREFIX_UD_ADDR): Likewise. | |
| 571 | (PREFIX_UD_LOCK): Likewise. | |
| 572 | ||
| 3888916d L |
573 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
| 574 | ||
| 575 | * i386-dis.c (prefix_requirement): Removed. | |
| 576 | (print_insn): Don't set prefix_requirement. Check | |
| 577 | dp->prefix_requirement instead of prefix_requirement. | |
| 578 | ||
| f24bcbaa L |
579 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
| 580 | ||
| 581 | PR binutils/17898 | |
| 582 | * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ... | |
| 583 | (PREFIX_MOD_0_0FC7_REG_6): This. | |
| 584 | (PREFIX_MOD_3_0FC7_REG_6): New. | |
| 585 | (PREFIX_MOD_3_0FC7_REG_7): Likewise. | |
| 586 | (prefix_table): Replace PREFIX_0FC7_REG_6 with | |
| 587 | PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and | |
| 588 | PREFIX_MOD_3_0FC7_REG_7. | |
| 589 | (mod_table): Replace PREFIX_0FC7_REG_6 with | |
| 590 | PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and | |
| 591 | PREFIX_MOD_3_0FC7_REG_7. | |
| 592 | ||
| 507bd325 L |
593 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
| 594 | ||
| 595 | * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed. | |
| 596 | (PREFIX_MANDATORY_REPNZ): Likewise. | |
| 597 | (PREFIX_MANDATORY_DATA): Likewise. | |
| 598 | (PREFIX_MANDATORY_ADDR): Likewise. | |
| 599 | (PREFIX_MANDATORY_LOCK): Likewise. | |
| 600 | (PREFIX_MANDATORY): Likewise. | |
| 601 | (PREFIX_UD_SHIFT): Set to 8 | |
| 602 | (PREFIX_UD_REPZ): Updated. | |
| 603 | (PREFIX_UD_REPNZ): Likewise. | |
| 604 | (PREFIX_UD_DATA): Likewise. | |
| 605 | (PREFIX_UD_ADDR): Likewise. | |
| 606 | (PREFIX_UD_LOCK): Likewise. | |
| 607 | (PREFIX_IGNORED_SHIFT): New. | |
| 608 | (PREFIX_IGNORED_REPZ): Likewise. | |
| 609 | (PREFIX_IGNORED_REPNZ): Likewise. | |
| 610 | (PREFIX_IGNORED_DATA): Likewise. | |
| 611 | (PREFIX_IGNORED_ADDR): Likewise. | |
| 612 | (PREFIX_IGNORED_LOCK): Likewise. | |
| 613 | (PREFIX_OPCODE): Likewise. | |
| 614 | (PREFIX_IGNORED): Likewise. | |
| 615 | (Bad_Opcode): Replace PREFIX_MANDATORY with 0. | |
| 616 | (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE. | |
| 617 | (three_byte_table): Likewise. | |
| 618 | (mod_table): Likewise. | |
| 619 | (mandatory_prefix): Renamed to ... | |
| 620 | (prefix_requirement): This. | |
| 621 | (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE. | |
| 622 | Update PREFIX_90 entry. | |
| 623 | (get_valid_dis386): Check prefix_requirement to see if a prefix | |
| 624 | should be ignored. | |
| 625 | (print_insn): Replace mandatory_prefix with prefix_requirement. | |
| 626 | ||
| f0fba320 RL |
627 | 2015-04-15 Renlin Li <renlin.li@arm.com> |
| 628 | ||
| 629 | * arm-dis.c (thumb32_opcodes): Define 'D' format control code, | |
| 630 | use it for ssat and ssat16. | |
| 631 | (print_insn_thumb32): Add handle case for 'D' control code. | |
| 632 | ||
| bf890a93 IT |
633 | 2015-04-06 Ilya Tocar <ilya.tocar@intel.com> |
| 634 | H.J. Lu <hongjiu.lu@intel.com> | |
| 635 | ||
| 636 | * i386-dis-evex.h (evex_table): Fill prefix_requirement field. | |
| 637 | * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ, | |
| 638 | PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK, | |
| 639 | PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA, | |
| 640 | PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define. | |
| 641 | (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX): | |
| 642 | Fill prefix_requirement field. | |
| 643 | (struct dis386): Add prefix_requirement field. | |
| 644 | (dis386): Fill prefix_requirement field. | |
| 645 | (dis386_twobyte): Ditto. | |
| 646 | (twobyte_has_mandatory_prefix_: Remove. | |
| 647 | (reg_table): Fill prefix_requirement field. | |
| 648 | (prefix_table): Ditto. | |
| 649 | (x86_64_table): Ditto. | |
| 650 | (three_byte_table): Ditto. | |
| 651 | (xop_table): Ditto. | |
| 652 | (vex_table): Ditto. | |
| 653 | (vex_len_table): Ditto. | |
| 654 | (vex_w_table): Ditto. | |
| 655 | (mod_table): Ditto. | |
| 656 | (bad_opcode): Ditto. | |
| 657 | (print_insn): Use prefix_requirement. | |
| 658 | (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4, | |
| 659 | FGRPde_3, FGRPdf_4): Fill prefix_requirement field. | |
| 660 | (float_reg): Ditto. | |
| 661 | ||
| 2f783c1f MF |
662 | 2015-03-30 Mike Frysinger <vapier@gentoo.org> |
| 663 | ||
| 664 | * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype. | |
| 665 | ||
| b9d94d62 L |
666 | 2015-03-29 H.J. Lu <hongjiu.lu@intel.com> |
| 667 | ||
| 668 | * Makefile.in: Regenerated. | |
| 669 | ||
| 27c49e9a AB |
670 | 2015-03-25 Anton Blanchard <anton@samba.org> |
| 671 | ||
| 672 | * ppc-dis.c (disassemble_init_powerpc): Only initialise | |
| 673 | powerpc_opcd_indices and vle_opcd_indices once. | |
| 674 | ||
| c4e676f1 AB |
675 | 2015-03-25 Anton Blanchard <anton@samba.org> |
| 676 | ||
| 677 | * ppc-opc.c (powerpc_opcodes): Add slbfee. | |
| 678 | ||
| 823d2571 TG |
679 | 2015-03-24 Terry Guo <terry.guo@arm.com> |
| 680 | ||
| 681 | * arm-dis.c (opcode32): Updated to use new arm feature struct. | |
| 682 | (opcode16): Likewise. | |
| 683 | (coprocessor_opcodes): Replace bit with feature struct. | |
| 684 | (neon_opcodes): Likewise. | |
| 685 | (arm_opcodes): Likewise. | |
| 686 | (thumb_opcodes): Likewise. | |
| 687 | (thumb32_opcodes): Likewise. | |
| 688 | (print_insn_coprocessor): Likewise. | |
| 689 | (print_insn_arm): Likewise. | |
| 690 | (select_arm_features): Follow new feature struct. | |
| 691 | ||
| 029f3522 GG |
692 | 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> |
| 693 | ||
| 694 | * i386-dis.c (rm_table): Add clzero. | |
| 695 | * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS. | |
| 696 | Add CPU_CLZERO_FLAGS. | |
| 697 | (cpu_flags): Add CpuCLZERO. | |
| 698 | * i386-opc.h: Add CpuCLZERO. | |
| 699 | * i386-opc.tbl: Add clzero. | |
| 700 | * i386-init.h: Re-generated. | |
| 701 | * i386-tbl.h: Re-generated. | |
| 702 | ||
| 6914869a AB |
703 | 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> |
| 704 | ||
| 705 | * mips-opc.c (decode_mips_operand): Fix constraint issues | |
| 706 | with u and y operands. | |
| 707 | ||
| 21e20815 AB |
708 | 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> |
| 709 | ||
| 710 | * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions. | |
| 711 | ||
| 6b1d7593 AK |
712 | 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| 713 | ||
| 714 | * s390-opc.c: Add new IBM z13 instructions. | |
| 715 | * s390-opc.txt: Likewise. | |
| 716 | ||
| c8f89a34 JW |
717 | 2015-03-10 Renlin Li <renlin.li@arm.com> |
| 718 | ||
| 719 | * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb, | |
| 720 | stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and | |
| 721 | related alias. | |
| 722 | * aarch64-asm-2.c: Regenerate. | |
| 723 | * aarch64-dis-2.c: Likewise. | |
| 724 | * aarch64-opc-2.c: Likewise. | |
| 725 | ||
| d8282f0e JW |
726 | 2015-03-03 Jiong Wang <jiong.wang@arm.com> |
| 727 | ||
| 728 | * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols. | |
| 729 | ||
| ac994365 OE |
730 | 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org> |
| 731 | ||
| 732 | * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of | |
| 733 | arch_sh_up. | |
| 734 | (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of | |
| 735 | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up. | |
| 736 | ||
| fd63f640 V |
737 | 2015-02-23 Vinay <Vinay.G@kpit.com> |
| 738 | ||
| 739 | * rl78-decode.opc (MOV): Added space between two operands for | |
| 740 | 'mov' instruction in index addressing mode. | |
| 741 | * rl78-decode.c: Regenerate. | |
| 742 | ||
| f63c1776 PA |
743 | 2015-02-19 Pedro Alves <palves@redhat.com> |
| 744 | ||
| 745 | * microblaze-dis.h [__cplusplus]: Wrap in extern "C". | |
| 746 | ||
| 07774fcc PA |
747 | 2015-02-10 Pedro Alves <palves@redhat.com> |
| 748 | Tom Tromey <tromey@redhat.com> | |
| 749 | ||
| 750 | * microblaze-opcm.h (or, and, xor): Rename to microblaze_or, | |
| 751 | microblaze_and, microblaze_xor. | |
| 752 | * microblaze-opc.h (opcodes): Adjust. | |
| 753 | ||
| 3f8107ab AM |
754 | 2015-01-28 James Bowman <james.bowman@ftdichip.com> |
| 755 | ||
| 756 | * Makefile.am: Add FT32 files. | |
| 757 | * configure.ac: Handle FT32. | |
| 758 | * disassemble.c (disassembler): Call print_insn_ft32. | |
| 759 | * ft32-dis.c: New file. | |
| 760 | * ft32-opc.c: New file. | |
| 761 | * Makefile.in: Regenerate. | |
| 762 | * configure: Regenerate. | |
| 763 | * po/POTFILES.in: Regenerate. | |
| 764 | ||
| e5fe4957 KLC |
765 | 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com> |
| 766 | ||
| 767 | * nds32-asm.c (keyword_sr): Add new system registers. | |
| 768 | ||
| 1e2e8c52 AK |
769 | 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| 770 | ||
| 771 | * s390-dis.c (s390_extract_operand): Support vector register | |
| 772 | operands. | |
| 773 | (s390_print_insn_with_opcode): Support new operands types and add | |
| 774 | new handling of optional operands. | |
| 775 | * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove | |
| 776 | and include opcode/s390.h instead. | |
| 777 | (struct op_struct): New field `flags'. | |
| 778 | (insertOpcode, insertExpandedMnemonic): New parameter `flags'. | |
| 779 | (dumpTable): Dump flags. | |
| 780 | (main): Parse flags from the s390-opc.txt file. Add z13 as cpu | |
| 781 | string. | |
| 782 | * s390-opc.c: Add new operands types, instruction formats, and | |
| 783 | instruction masks. | |
| 784 | (s390_opformats): Add new formats for .insn. | |
| 785 | * s390-opc.txt: Add new instructions. | |
| 786 | ||
| b90efa5b | 787 | 2015-01-01 Alan Modra <amodra@gmail.com> |
| bffb6004 | 788 | |
| b90efa5b | 789 | Update year range in copyright notice of all files. |
| bffb6004 | 790 | |
| b90efa5b | 791 | For older changes see ChangeLog-2014 |
| 252b5132 | 792 | \f |
| b90efa5b | 793 | Copyright (C) 2015 Free Software Foundation, Inc. |
| 752937aa NC |
794 | |
| 795 | Copying and distribution of this file, with or without modification, | |
| 796 | are permitted in any medium without royalty provided the copyright | |
| 797 | notice and this notice are preserved. | |
| 798 | ||
| 252b5132 | 799 | Local Variables: |
| 2f6d2f85 NC |
800 | mode: change-log |
| 801 | left-margin: 8 | |
| 802 | fill-column: 74 | |
| 252b5132 RH |
803 | version-control: never |
| 804 | End: |