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x86: don't abort() upon DATA16 prefix on (E)VEX encoded insn
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e951d5ca
JB		 12018-07-31 Jan Beulich <jbeulich@suse.com>
2
3 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
4 (cpu_flags): Drop CpuVREX.
5 * i386-opc.h (CpuVREX): Delete.
6 (union i386_cpu_flags): Remove cpuvrex.
7 * i386-init.h, i386-tbl.h: Re-generate.
8
eb41b248
JW		 92018-07-30 Jim Wilson <jimw@sifive.com>
10
11 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
12 fields.
13 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
14
b8891f8d
AJ		 152018-07-30 Andrew Jenner <andrew@codesourcery.com>
16
17 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
18 * Makefile.in: Regenerated.
19 * configure.ac: Add C-SKY.
20 * configure: Regenerated.
21 * csky-dis.c: New file.
22 * csky-opc.h: New file.
23 * disassemble.c (ARCH_csky): Define.
24 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
25 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
26
16065af1
AM		 272018-07-27 Alan Modra <amodra@gmail.com>
28
29 * ppc-opc.c (insert_sprbat): Correct function parameter and
30 return type.
31 (extract_sprbat): Likewise, variable too.
32
fa758a70
AC		 332018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
34 Alan Modra <amodra@gmail.com>
35
36 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
37 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
38 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
39 support disjointed BAT.
40 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
41 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
42 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
43
4a1b91ea
L		 442018-07-25 H.J. Lu <hongjiu.lu@intel.com>
45 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
46
47 * i386-gen.c (adjust_broadcast_modifier): New function.
48 (process_i386_opcode_modifier): Add an argument for operands.
49 Adjust the Broadcast value based on operands.
50 (output_i386_opcode): Pass operand_types to
51 process_i386_opcode_modifier.
52 (process_i386_opcodes): Pass NULL as operands to
53 process_i386_opcode_modifier.
54 * i386-opc.h (BYTE_BROADCAST): New.
55 (WORD_BROADCAST): Likewise.
56 (DWORD_BROADCAST): Likewise.
57 (QWORD_BROADCAST): Likewise.
58 (i386_opcode_modifier): Expand broadcast to 3 bits.
59 * i386-tbl.h: Regenerated.
60
67ce483b
AM		 612018-07-24 Alan Modra <amodra@gmail.com>
62
63 PR 23430
64 * or1k-desc.h: Regenerate.
65
4174bfff
JB		 662018-07-24 Jan Beulich <jbeulich@suse.com>
67
68 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
69 vcvtusi2ss, and vcvtusi2sd.
70 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
71 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
72 * i386-tbl.h: Re-generate.
73
04e65276
CZ		 742018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
75
76 * arc-opc.c (extract_w6): Fix extending the sign.
77
47e6f81c
CZ		 782018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
79
80 * arc-tbl.h (vewt): Allow it for ARC EM family.
81
bb71536f
AM		 822018-07-23 Alan Modra <amodra@gmail.com>
83
84 PR 23419
85 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
86 opcode variants for mtspr/mfspr encodings.
87
8095d2f7
CX		 882018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
89 Maciej W. Rozycki <macro@mips.com>
90
91 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
92 loongson3a descriptors.
93 (parse_mips_ase_option): Handle -M loongson-mmi option.
94 (print_mips_disassembler_options): Document -M loongson-mmi.
95 * mips-opc.c (LMMI): New macro.
96 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
97 instructions.
98
5f32791e
JB		 992018-07-19 Jan Beulich <jbeulich@suse.com>
100
101 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
102 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
103 IgnoreSize and [XYZ]MMword where applicable.
104 * i386-tbl.h: Re-generate.
105
625cbd7a
JB		 1062018-07-19 Jan Beulich <jbeulich@suse.com>
107
108 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
109 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
110 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
111 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
112 * i386-tbl.h: Re-generate.
113
86b15c32
JB		 1142018-07-19 Jan Beulich <jbeulich@suse.com>
115
116 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
117 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
118 VPCLMULQDQ templates into their respective AVX512VL counterparts
119 where possible, using Disp8ShiftVL and CheckRegSize instead of
120 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
121 * i386-tbl.h: Re-generate.
122
cf769ed5
JB		 1232018-07-19 Jan Beulich <jbeulich@suse.com>
124
125 * i386-opc.tbl: Fold AVX512DQ templates into their respective
126 AVX512VL counterparts where possible, using Disp8ShiftVL and
127 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
128 IgnoreSize) as appropriate.
129 * i386-tbl.h: Re-generate.
130
8282b7ad
JB		 1312018-07-19 Jan Beulich <jbeulich@suse.com>
132
133 * i386-opc.tbl: Fold AVX512BW templates into their respective
134 AVX512VL counterparts where possible, using Disp8ShiftVL and
135 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
136 IgnoreSize) as appropriate.
137 * i386-tbl.h: Re-generate.
138
755908cc
JB		 1392018-07-19 Jan Beulich <jbeulich@suse.com>
140
141 * i386-opc.tbl: Fold AVX512CD templates into their respective
142 AVX512VL counterparts where possible, using Disp8ShiftVL and
143 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
144 IgnoreSize) as appropriate.
145 * i386-tbl.h: Re-generate.
146
7091c612
JB		 1472018-07-19 Jan Beulich <jbeulich@suse.com>
148
149 * i386-opc.h (DISP8_SHIFT_VL): New.
150 * i386-opc.tbl (Disp8ShiftVL): Define.
151 (various): Fold AVX512VL templates into their respective
152 AVX512F counterparts where possible, using Disp8ShiftVL and
153 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
154 IgnoreSize) as appropriate.
155 * i386-tbl.h: Re-generate.
156
c30be56e
JB		 1572018-07-19 Jan Beulich <jbeulich@suse.com>
158
159 * Makefile.am: Change dependencies and rule for
160 $(srcdir)/i386-init.h.
161 * Makefile.in: Re-generate.
162 * i386-gen.c (process_i386_opcodes): New local variable
163 "marker". Drop opening of input file. Recognize marker and line
164 number directives.
165 * i386-opc.tbl (OPCODE_I386_H): Define.
166 (i386-opc.h): Include it.
167 (None): Undefine.
168
11a322db
L		 1692018-07-18 H.J. Lu <hongjiu.lu@intel.com>
170
171 PR gas/23418
172 * i386-opc.h (Byte): Update comments.
173 (Word): Likewise.
174 (Dword): Likewise.
175 (Fword): Likewise.
176 (Qword): Likewise.
177 (Tbyte): Likewise.
178 (Xmmword): Likewise.
179 (Ymmword): Likewise.
180 (Zmmword): Likewise.
181 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
182 vcvttps2uqq.
183 * i386-tbl.h: Regenerated.
184
cde3679e
NC		 1852018-07-12 Sudakshina Das <sudi.das@arm.com>
186
187 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
188 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
189 * aarch64-asm-2.c: Regenerate.
190 * aarch64-dis-2.c: Regenerate.
191 * aarch64-opc-2.c: Regenerate.
192
45a28947
TC		 1932018-07-12 Tamar Christina <tamar.christina@arm.com>
194
195 PR binutils/23192
196 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
197 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
198 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
199 sqdmulh, sqrdmulh): Use Em16.
200
c597cc3d
SD		 2012018-07-11 Sudakshina Das <sudi.das@arm.com>
202
203 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
204 csdb together with them.
205 (thumb32_opcodes): Likewise.
206
a79eaed6
JB		 2072018-07-11 Jan Beulich <jbeulich@suse.com>
208
209 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
210 requiring 32-bit registers as operands 2 and 3. Improve
211 comments.
212 (mwait, mwaitx): Fold templates. Improve comments.
213 OPERAND_TYPE_INOUTPORTREG.
214 * i386-tbl.h: Re-generate.
215
2fb5be8d
JB		 2162018-07-11 Jan Beulich <jbeulich@suse.com>
217
218 * i386-gen.c (operand_type_init): Remove
219 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
220 OPERAND_TYPE_INOUTPORTREG.
221 * i386-init.h: Re-generate.
222
7f5cad30
JB		 2232018-07-11 Jan Beulich <jbeulich@suse.com>
224
225 * i386-opc.tbl (wrssd, wrussd): Add Dword.
226 (wrssq, wrussq): Add Qword.
227 * i386-tbl.h: Re-generate.
228
f0a85b07
JB		 2292018-07-11 Jan Beulich <jbeulich@suse.com>
230
231 * i386-opc.h: Rename OTMax to OTNum.
232 (OTNumOfUints): Adjust calculation.
233 (OTUnused): Directly alias to OTNum.
234
9dcb0ba4
MR		 2352018-07-09 Maciej W. Rozycki <macro@mips.com>
236
237 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
238 `reg_xys'.
239 (lea_reg_xys): Likewise.
240 (print_insn_loop_primitive): Rename `reg' local variable to
241 `reg_dxy'.
242
f311ba7e
TC		 2432018-07-06 Tamar Christina <tamar.christina@arm.com>
244
245 PR binutils/23242
246 * aarch64-tbl.h (ldarh): Fix disassembly mask.
247
cba05feb
TC		 2482018-07-06 Tamar Christina <tamar.christina@arm.com>
249
250 PR binutils/23369
251 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
252 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
253
471b9d15
MR		 2542018-07-02 Maciej W. Rozycki <macro@mips.com>
255
256 PR tdep/8282
257 * mips-dis.c (mips_option_arg_t): New enumeration.
258 (mips_options): New variable.
259 (disassembler_options_mips): New function.
260 (print_mips_disassembler_options): Reimplement in terms of
261 `disassembler_options_mips'.
262 * arm-dis.c (disassembler_options_arm): Adapt to using the
263 `disasm_options_and_args_t' structure.
264 * ppc-dis.c (disassembler_options_powerpc): Likewise.
265 * s390-dis.c (disassembler_options_s390): Likewise.
266
c0c468d5
TP		 2672018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
268
269 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
270 expected result.
271 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
272 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
273 * testsuite/ld-arm/tls-longplt.d: Likewise.
274
369c9167
TC		 2752018-06-29 Tamar Christina <tamar.christina@arm.com>
276
277 PR binutils/23192
278 * aarch64-asm-2.c: Regenerate.
279 * aarch64-dis-2.c: Likewise.
280 * aarch64-opc-2.c: Likewise.
281 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
282 * aarch64-opc.c (operand_general_constraint_met_p,
283 aarch64_print_operand): Likewise.
284 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
285 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
286 fmlal2, fmlsl2.
287 (AARCH64_OPERANDS): Add Em2.
288
30aa1306
NC		 2892018-06-26 Nick Clifton <nickc@redhat.com>
290
291 * po/uk.po: Updated Ukranian translation.
292 * po/de.po: Updated German translation.
293 * po/pt_BR.po: Updated Brazilian Portuguese translation.
294
eca4b721
NC		 2952018-06-26 Nick Clifton <nickc@redhat.com>
296
297 * nfp-dis.c: Fix spelling mistake.
298
71300e2c
NC		 2992018-06-24 Nick Clifton <nickc@redhat.com>
300
301 * configure: Regenerate.
302 * po/opcodes.pot: Regenerate.
303
719d8288
NC		 3042018-06-24 Nick Clifton <nickc@redhat.com>
305
306 2.31 branch created.
307
514cd3a0
TC		 3082018-06-19 Tamar Christina <tamar.christina@arm.com>
309
310 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
311 * aarch64-asm-2.c: Regenerate.
312 * aarch64-dis-2.c: Likewise.
313
385e4d0f
MR		 3142018-06-21 Maciej W. Rozycki <macro@mips.com>
315
316 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
317 `-M ginv' option description.
318
160d1b3d
SH		 3192018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
320
321 PR gas/23305
322 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
323 la and lla.
324
d0ac1c44
SM		 3252018-06-19 Simon Marchi <simon.marchi@ericsson.com>
326
327 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
328 * configure.ac: Remove AC_PREREQ.
329 * Makefile.in: Re-generate.
330 * aclocal.m4: Re-generate.
331 * configure: Re-generate.
332
6f20c942
FS		 3332018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
334
335 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
336 mips64r6 descriptors.
337 (parse_mips_ase_option): Handle -Mginv option.
338 (print_mips_disassembler_options): Document -Mginv.
339 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
340 (GINV): New macro.
341 (mips_opcodes): Define ginvi and ginvt.
342
730c3174
SE		 3432018-06-13 Scott Egerton <scott.egerton@imgtec.com>
344 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
345
346 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
347 * mips-opc.c (CRC, CRC64): New macros.
348 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
349 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
350 crc32cd for CRC64.
351
cb366992
EB		 3522018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
353
354 PR 20319
355 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
356 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
357
ce72cd46
AM		 3582018-06-06 Alan Modra <amodra@gmail.com>
359
360 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
361 setjmp. Move init for some other vars later too.
362
4b8e28c7
MF		 3632018-06-04 Max Filippov <jcmvbkbc@gmail.com>
364
365 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
366 (dis_private): Add new fields for property section tracking.
367 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
368 (xtensa_instruction_fits): New functions.
369 (fetch_data): Bump minimal fetch size to 4.
370 (print_insn_xtensa): Make struct dis_private static.
371 Load and prepare property table on section change.
372 Don't disassemble literals. Don't disassemble instructions that
373 cross property table boundaries.
374
55e99962
L		 3752018-06-01 H.J. Lu <hongjiu.lu@intel.com>
376
377 * configure: Regenerated.
378
733bd0ab
JB		 3792018-06-01 Jan Beulich <jbeulich@suse.com>
380
381 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
382 * i386-tbl.h: Re-generate.
383
dfd27d41
JB		 3842018-06-01 Jan Beulich <jbeulich@suse.com>
385
386 * i386-opc.tbl (sldt, str): Add NoRex64.
387 * i386-tbl.h: Re-generate.
388
64795710
JB		 3892018-06-01 Jan Beulich <jbeulich@suse.com>
390
391 * i386-opc.tbl (invpcid): Add Oword.
392 * i386-tbl.h: Re-generate.
393
030157d8
AM		 3942018-06-01 Alan Modra <amodra@gmail.com>
395
396 * sysdep.h (_bfd_error_handler): Don't declare.
397 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
398 * rl78-decode.opc: Likewise.
399 * msp430-decode.c: Regenerate.
400 * rl78-decode.c: Regenerate.
401
a9660a6f
AP		 4022018-05-30 Amit Pawar <Amit.Pawar@amd.com>
403
404 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
405 * i386-init.h : Regenerated.
406
277eb7f6
AM		 4072018-05-25 Alan Modra <amodra@gmail.com>
408
409 * Makefile.in: Regenerate.
410 * po/POTFILES.in: Regenerate.
411
98553ad3
PB		 4122018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
413
414 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
415 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
416 (insert_bab, extract_bab, insert_btab, extract_btab,
417 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
418 (BAT, BBA VBA RBS XB6S): Delete macros.
419 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
420 (BB, BD, RBX, XC6): Update for new macros.
421 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
422 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
423 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
424 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
425
7b4ae824
JD		 4262018-05-18 John Darrington <john@darrington.wattle.id.au>
427
428 * Makefile.am: Add support for s12z architecture.
429 * configure.ac: Likewise.
430 * disassemble.c: Likewise.
431 * disassemble.h: Likewise.
432 * Makefile.in: Regenerate.
433 * configure: Regenerate.
434 * s12z-dis.c: New file.
435 * s12z.h: New file.
436
29e0f0a1
AM		 4372018-05-18 Alan Modra <amodra@gmail.com>
438
439 * nfp-dis.c: Don't #include libbfd.h.
440 (init_nfp3200_priv): Use bfd_get_section_contents.
441 (nit_nfp6000_mecsr_sec): Likewise.
442
809276d2
NC		 4432018-05-17 Nick Clifton <nickc@redhat.com>
444
445 * po/zh_CN.po: Updated simplified Chinese translation.
446
ff329288
TC		 4472018-05-16 Tamar Christina <tamar.christina@arm.com>
448
449 PR binutils/23109
450 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
451 * aarch64-dis-2.c: Regenerate.
452
f9830ec1
TC		 4532018-05-15 Tamar Christina <tamar.christina@arm.com>
454
455 PR binutils/21446
456 * aarch64-asm.c (opintl.h): Include.
457 (aarch64_ins_sysreg): Enforce read/write constraints.
458 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
459 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
460 (F_REG_READ, F_REG_WRITE): New.
461 * aarch64-opc.c (aarch64_print_operand): Generate notes for
462 AARCH64_OPND_SYSREG.
463 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
464 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
465 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
466 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
467 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
468 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
469 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
470 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
471 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
472 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
473 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
474 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
475 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
476 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
477 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
478 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
479 msr (F_SYS_WRITE), mrs (F_SYS_READ).
480
7d02540a
TC		 4812018-05-15 Tamar Christina <tamar.christina@arm.com>
482
483 PR binutils/21446
484 * aarch64-dis.c (no_notes: New.
485 (parse_aarch64_dis_option): Support notes.
486 (aarch64_decode_insn, print_operands): Likewise.
487 (print_aarch64_disassembler_options): Document notes.
488 * aarch64-opc.c (aarch64_print_operand): Support notes.
489
561a72d4
TC		 4902018-05-15 Tamar Christina <tamar.christina@arm.com>
491
492 PR binutils/21446
493 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
494 and take error struct.
495 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
496 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
497 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
498 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
499 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
500 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
501 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
502 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
503 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
504 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
505 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
506 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
507 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
508 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
509 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
510 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
511 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
512 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
513 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
514 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
515 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
516 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
517 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
518 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
519 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
520 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
521 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
522 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
523 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
524 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
525 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
526 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
527 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
528 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
529 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
530 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
531 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
532 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
533 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
534 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
535 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
536 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
537 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
538 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
539 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
540 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
541 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
542 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
543 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
544 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
545 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
546 (determine_disassembling_preference, aarch64_decode_insn,
547 print_insn_aarch64_word, print_insn_data): Take errors struct.
548 (print_insn_aarch64): Use errors.
549 * aarch64-asm-2.c: Regenerate.
550 * aarch64-dis-2.c: Regenerate.
551 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
552 boolean in aarch64_insert_operan.
553 (print_operand_extractor): Likewise.
554 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
555
1678bd35
FT		 5562018-05-15 Francois H. Theron <francois.theron@netronome.com>
557
558 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
559
06cfb1c8
L		 5602018-05-09 H.J. Lu <hongjiu.lu@intel.com>
561
562 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
563
84f9f8c3
AM		 5642018-05-09 Sebastian Rasmussen <sebras@gmail.com>
565
566 * cr16-opc.c (cr16_instruction): Comment typo fix.
567 * hppa-dis.c (print_insn_hppa): Likewise.
568
e6f372ba
JW		 5692018-05-08 Jim Wilson <jimw@sifive.com>
570
571 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
572 (match_c_slli64, match_srxi_as_c_srxi): New.
573 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
574 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
575 <c.slli, c.srli, c.srai>: Use match_s_slli.
576 <c.slli64, c.srli64, c.srai64>: New.
577
f413a913
AM		 5782018-05-08 Alan Modra <amodra@gmail.com>
579
580 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
581 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
582 partition opcode space for index lookup.
583
a87a6478
PB		 5842018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
585
586 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
587 <insn_length>: ...with this. Update usage.
588 Remove duplicate call to *info->memory_error_func.
589
c0a30a9f
L		 5902018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
591 H.J. Lu <hongjiu.lu@intel.com>
592
593 * i386-dis.c (Gva): New.
594 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
595 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
596 (prefix_table): New instructions (see prefix above).
597 (mod_table): New instructions (see prefix above).
598 (OP_G): Handle va_mode.
599 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
600 CPU_MOVDIR64B_FLAGS.
601 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
602 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
603 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
604 * i386-opc.tbl: Add movidir{i,64b}.
605 * i386-init.h: Regenerated.
606 * i386-tbl.h: Likewise.
607
75c0a438
L		 6082018-05-07 H.J. Lu <hongjiu.lu@intel.com>
609
610 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
611 AddrPrefixOpReg.
612 * i386-opc.h (AddrPrefixOp0): Renamed to ...
613 (AddrPrefixOpReg): This.
614 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
615 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
616
2ceb7719
PB		 6172018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
618
619 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
620 (vle_num_opcodes): Likewise.
621 (spe2_num_opcodes): Likewise.
622 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
623 initialization loop.
624 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
625 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
626 only once.
627
b3ac5c6c
TC		 6282018-05-01 Tamar Christina <tamar.christina@arm.com>
629
630 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
631
fe944acf
FT		 6322018-04-30 Francois H. Theron <francois.theron@netronome.com>
633
634 Makefile.am: Added nfp-dis.c.
635 configure.ac: Added bfd_nfp_arch.
636 disassemble.h: Added print_insn_nfp prototype.
637 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
638 nfp-dis.c: New, for NFP support.
639 po/POTFILES.in: Added nfp-dis.c to the list.
640 Makefile.in: Regenerate.
641 configure: Regenerate.
642
e2195274
JB		 6432018-04-26 Jan Beulich <jbeulich@suse.com>
644
645 * i386-opc.tbl: Fold various non-memory operand AVX512VL
646 templates into their base ones.
647 * i386-tlb.h: Re-generate.
648
59ef5df4
JB		 6492018-04-26 Jan Beulich <jbeulich@suse.com>
650
651 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
652 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
653 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
654 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
655 * i386-init.h: Re-generate.
656
6e041cf4
JB		 6572018-04-26 Jan Beulich <jbeulich@suse.com>
658
659 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
660 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
661 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
662 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
663 comment.
664 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
665 and CpuRegMask.
666 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
667 CpuRegMask: Delete.
668 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
669 cpuregzmm, and cpuregmask.
670 * i386-init.h: Re-generate.
671 * i386-tbl.h: Re-generate.
672
0e0eea78
JB		 6732018-04-26 Jan Beulich <jbeulich@suse.com>
674
675 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
676 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
677 * i386-init.h: Re-generate.
678
2f1bada2
JB		 6792018-04-26 Jan Beulich <jbeulich@suse.com>
680
681 * i386-gen.c (VexImmExt): Delete.
682 * i386-opc.h (VexImmExt, veximmext): Delete.
683 * i386-opc.tbl: Drop all VexImmExt uses.
684 * i386-tlb.h: Re-generate.
685
bacd1457
JB		 6862018-04-25 Jan Beulich <jbeulich@suse.com>
687
688 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
689 register-only forms.
690 * i386-tlb.h: Re-generate.
691
10bba94b
TC		 6922018-04-25 Tamar Christina <tamar.christina@arm.com>
693
694 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
695
c48935d7
IT		 6962018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
697
698 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
699 PREFIX_0F1C.
700 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
701 (cpu_flags): Add CpuCLDEMOTE.
702 * i386-init.h: Regenerate.
703 * i386-opc.h (enum): Add CpuCLDEMOTE,
704 (i386_cpu_flags): Add cpucldemote.
705 * i386-opc.tbl: Add cldemote.
706 * i386-tbl.h: Regenerate.
707
211dc24b
AM		 7082018-04-16 Alan Modra <amodra@gmail.com>
709
710 * Makefile.am: Remove sh5 and sh64 support.
711 * configure.ac: Likewise.
712 * disassemble.c: Likewise.
713 * disassemble.h: Likewise.
714 * sh-dis.c: Likewise.
715 * sh64-dis.c: Delete.
716 * sh64-opc.c: Delete.
717 * sh64-opc.h: Delete.
718 * Makefile.in: Regenerate.
719 * configure: Regenerate.
720 * po/POTFILES.in: Regenerate.
721
a9a4b302
AM		 7222018-04-16 Alan Modra <amodra@gmail.com>
723
724 * Makefile.am: Remove w65 support.
725 * configure.ac: Likewise.
726 * disassemble.c: Likewise.
727 * disassemble.h: Likewise.
728 * w65-dis.c: Delete.
729 * w65-opc.h: Delete.
730 * Makefile.in: Regenerate.
731 * configure: Regenerate.
732 * po/POTFILES.in: Regenerate.
733
04cb01fd
AM		 7342018-04-16 Alan Modra <amodra@gmail.com>
735
736 * configure.ac: Remove we32k support.
737 * configure: Regenerate.
738
c2bf1eec
AM		 7392018-04-16 Alan Modra <amodra@gmail.com>
740
741 * Makefile.am: Remove m88k support.
742 * configure.ac: Likewise.
743 * disassemble.c: Likewise.
744 * disassemble.h: Likewise.
745 * m88k-dis.c: Delete.
746 * Makefile.in: Regenerate.
747 * configure: Regenerate.
748 * po/POTFILES.in: Regenerate.
749
6793974d
AM		 7502018-04-16 Alan Modra <amodra@gmail.com>
751
752 * Makefile.am: Remove i370 support.
753 * configure.ac: Likewise.
754 * disassemble.c: Likewise.
755 * disassemble.h: Likewise.
756 * i370-dis.c: Delete.
757 * i370-opc.c: Delete.
758 * Makefile.in: Regenerate.
759 * configure: Regenerate.
760 * po/POTFILES.in: Regenerate.
761
e82aa794
AM		 7622018-04-16 Alan Modra <amodra@gmail.com>
763
764 * Makefile.am: Remove h8500 support.
765 * configure.ac: Likewise.
766 * disassemble.c: Likewise.
767 * disassemble.h: Likewise.
768 * h8500-dis.c: Delete.
769 * h8500-opc.h: Delete.
770 * Makefile.in: Regenerate.
771 * configure: Regenerate.
772 * po/POTFILES.in: Regenerate.
773
fceadf09
AM		 7742018-04-16 Alan Modra <amodra@gmail.com>
775
776 * configure.ac: Remove tahoe support.
777 * configure: Regenerate.
778
ae1d3843
L		 7792018-04-15 H.J. Lu <hongjiu.lu@intel.com>
780
781 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
782 umwait.
783 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
784 64-bit mode.
785 * i386-tbl.h: Regenerated.
786
de89d0a3
IT		 7872018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
788
789 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
790 PREFIX_MOD_1_0FAE_REG_6.
791 (va_mode): New.
792 (OP_E_register): Use va_mode.
793 * i386-dis-evex.h (prefix_table):
794 New instructions (see prefixes above).
795 * i386-gen.c (cpu_flag_init): Add WAITPKG.
796 (cpu_flags): Likewise.
797 * i386-opc.h (enum): Likewise.
798 (i386_cpu_flags): Likewise.
799 * i386-opc.tbl: Add umonitor, umwait, tpause.
800 * i386-init.h: Regenerate.
801 * i386-tbl.h: Likewise.
802
a8eb42a8
AM		 8032018-04-11 Alan Modra <amodra@gmail.com>
804
805 * opcodes/i860-dis.c: Delete.
806 * opcodes/i960-dis.c: Delete.
807 * Makefile.am: Remove i860 and i960 support.
808 * configure.ac: Likewise.
809 * disassemble.c: Likewise.
810 * disassemble.h: Likewise.
811 * Makefile.in: Regenerate.
812 * configure: Regenerate.
813 * po/POTFILES.in: Regenerate.
814
caf0678c
L		 8152018-04-04 H.J. Lu <hongjiu.lu@intel.com>
816
817 PR binutils/23025
818 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
819 to 0.
820 (print_insn): Clear vex instead of vex.evex.
821
4fb0d2b9
NC		 8222018-04-04 Nick Clifton <nickc@redhat.com>
823
824 * po/es.po: Updated Spanish translation.
825
c39e5b26
JB		 8262018-03-28 Jan Beulich <jbeulich@suse.com>
827
828 * i386-gen.c (opcode_modifiers): Delete VecESize.
829 * i386-opc.h (VecESize): Delete.
830 (struct i386_opcode_modifier): Delete vecesize.
831 * i386-opc.tbl: Drop VecESize.
832 * i386-tlb.h: Re-generate.
833
8e6e0792
JB		 8342018-03-28 Jan Beulich <jbeulich@suse.com>
835
836 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
837 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
838 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
839 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
840 * i386-tlb.h: Re-generate.
841
9f123b91
JB		 8422018-03-28 Jan Beulich <jbeulich@suse.com>
843
844 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
845 Fold AVX512 forms
846 * i386-tlb.h: Re-generate.
847
9646c87b
JB		 8482018-03-28 Jan Beulich <jbeulich@suse.com>
849
850 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
851 (vex_len_table): Drop Y for vcvt*2si.
852 (putop): Replace plain 'Y' handling by abort().
853
c8d59609
NC		 8542018-03-28 Nick Clifton <nickc@redhat.com>
855
856 PR 22988
857 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
858 instructions with only a base address register.
859 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
860 handle AARHC64_OPND_SVE_ADDR_R.
861 (aarch64_print_operand): Likewise.
862 * aarch64-asm-2.c: Regenerate.
863 * aarch64_dis-2.c: Regenerate.
864 * aarch64-opc-2.c: Regenerate.
865
b8c169f3
JB		 8662018-03-22 Jan Beulich <jbeulich@suse.com>
867
868 * i386-opc.tbl: Drop VecESize from register only insn forms and
869 memory forms not allowing broadcast.
870 * i386-tlb.h: Re-generate.
871
96bc132a
JB		 8722018-03-22 Jan Beulich <jbeulich@suse.com>
873
874 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
875 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
876 sha256*): Drop Disp<N>.
877
9f79e886
JB		 8782018-03-22 Jan Beulich <jbeulich@suse.com>
879
880 * i386-dis.c (EbndS, bnd_swap_mode): New.
881 (prefix_table): Use EbndS.
882 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
883 * i386-opc.tbl (bndmov): Move misplaced Load.
884 * i386-tlb.h: Re-generate.
885
d6793fa1
JB		 8862018-03-22 Jan Beulich <jbeulich@suse.com>
887
888 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
889 templates allowing memory operands and folded ones for register
890 only flavors.
891 * i386-tlb.h: Re-generate.
892
f7768225
JB		 8932018-03-22 Jan Beulich <jbeulich@suse.com>
894
895 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
896 256-bit templates. Drop redundant leftover Disp<N>.
897 * i386-tlb.h: Re-generate.
898
0e35537d
JW		 8992018-03-14 Kito Cheng <kito.cheng@gmail.com>
900
901 * riscv-opc.c (riscv_insn_types): New.
902
b4a3689a
NC		 9032018-03-13 Nick Clifton <nickc@redhat.com>
904
905 * po/pt_BR.po: Updated Brazilian Portuguese translation.
906
d3d50934
L		 9072018-03-08 H.J. Lu <hongjiu.lu@intel.com>
908
909 * i386-opc.tbl: Add Optimize to clr.
910 * i386-tbl.h: Regenerated.
911
bd5dea88
L		 9122018-03-08 H.J. Lu <hongjiu.lu@intel.com>
913
914 * i386-gen.c (opcode_modifiers): Remove OldGcc.
915 * i386-opc.h (OldGcc): Removed.
916 (i386_opcode_modifier): Remove oldgcc.
917 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
918 instructions for old (<= 2.8.1) versions of gcc.
919 * i386-tbl.h: Regenerated.
920
e771e7c9
JB		 9212018-03-08 Jan Beulich <jbeulich@suse.com>
922
923 * i386-opc.h (EVEXDYN): New.
924 * i386-opc.tbl: Fold various AVX512VL templates.
925 * i386-tlb.h: Re-generate.
926
ed438a93
JB		 9272018-03-08 Jan Beulich <jbeulich@suse.com>
928
929 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
930 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
931 vpexpandd, vpexpandq): Fold AFX512VF templates.
932 * i386-tlb.h: Re-generate.
933
454172a9
JB		 9342018-03-08 Jan Beulich <jbeulich@suse.com>
935
936 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
937 Fold 128- and 256-bit VEX-encoded templates.
938 * i386-tlb.h: Re-generate.
939
36824150
JB		 9402018-03-08 Jan Beulich <jbeulich@suse.com>
941
942 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
943 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
944 vpexpandd, vpexpandq): Fold AVX512F templates.
945 * i386-tlb.h: Re-generate.
946
e7f5c0a9
JB		 9472018-03-08 Jan Beulich <jbeulich@suse.com>
948
949 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
950 64-bit templates. Drop Disp<N>.
951 * i386-tlb.h: Re-generate.
952
25a4277f
JB		 9532018-03-08 Jan Beulich <jbeulich@suse.com>
954
955 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
956 and 256-bit templates.
957 * i386-tlb.h: Re-generate.
958
d2224064
JB		 9592018-03-08 Jan Beulich <jbeulich@suse.com>
960
961 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
962 * i386-tlb.h: Re-generate.
963
1b193f0b
JB		 9642018-03-08 Jan Beulich <jbeulich@suse.com>
965
966 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
967 Drop NoAVX.
968 * i386-tlb.h: Re-generate.
969
f2f6a710
JB		 9702018-03-08 Jan Beulich <jbeulich@suse.com>
971
972 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
973 * i386-tlb.h: Re-generate.
974
38e314eb
JB		 9752018-03-08 Jan Beulich <jbeulich@suse.com>
976
977 * i386-gen.c (opcode_modifiers): Delete FloatD.
978 * i386-opc.h (FloatD): Delete.
979 (struct i386_opcode_modifier): Delete floatd.
980 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
981 FloatD by D.
982 * i386-tlb.h: Re-generate.
983
d53e6b98
JB		 9842018-03-08 Jan Beulich <jbeulich@suse.com>
985
986 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
987
2907c2f5
JB		 9882018-03-08 Jan Beulich <jbeulich@suse.com>
989
990 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
991 * i386-tlb.h: Re-generate.
992
73053c1f
JB		 9932018-03-08 Jan Beulich <jbeulich@suse.com>
994
995 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
996 forms.
997 * i386-tlb.h: Re-generate.
998
52fe4420
AM		 9992018-03-07 Alan Modra <amodra@gmail.com>
1000
1001 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1002 bfd_arch_rs6000.
1003 * disassemble.h (print_insn_rs6000): Delete.
1004 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1005 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1006 (print_insn_rs6000): Delete.
1007
a6743a54
AM		 10082018-03-03 Alan Modra <amodra@gmail.com>
1009
1010 * sysdep.h (opcodes_error_handler): Define.
1011 (_bfd_error_handler): Declare.
1012 * Makefile.am: Remove stray #.
1013 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1014 EDIT" comment.
1015 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1016 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1017 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1018 opcodes_error_handler to print errors. Standardize error messages.
1019 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1020 and include opintl.h.
1021 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1022 * i386-gen.c: Standardize error messages.
1023 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1024 * Makefile.in: Regenerate.
1025 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1026 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1027 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1028 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1029 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1030 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1031 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1032 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1033 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1034 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1035 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1036 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1037 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1038
8305403a
L		 10392018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1040
1041 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1042 vpsub[bwdq] instructions.
1043 * i386-tbl.h: Regenerated.
1044
e184813f
AM		 10452018-03-01 Alan Modra <amodra@gmail.com>
1046
1047 * configure.ac (ALL_LINGUAS): Sort.
1048 * configure: Regenerate.
1049
5b616bef
TP		 10502018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1051
1052 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1053 macro by assignements.
1054
b6f8c7c4
L		 10552018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1056
1057 PR gas/22871
1058 * i386-gen.c (opcode_modifiers): Add Optimize.
1059 * i386-opc.h (Optimize): New enum.
1060 (i386_opcode_modifier): Add optimize.
1061 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1062 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1063 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1064 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1065 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1066 vpxord and vpxorq.
1067 * i386-tbl.h: Regenerated.
1068
e95b887f
AM		 10692018-02-26 Alan Modra <amodra@gmail.com>
1070
1071 * crx-dis.c (getregliststring): Allocate a large enough buffer
1072 to silence false positive gcc8 warning.
1073
0bccfb29
JW		 10742018-02-22 Shea Levy <shea@shealevy.com>
1075
1076 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1077
6b6b6807
L		 10782018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1079
1080 * i386-opc.tbl: Add {rex},
1081 * i386-tbl.h: Regenerated.
1082
75f31665
MR		 10832018-02-20 Maciej W. Rozycki <macro@mips.com>
1084
1085 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1086 (mips16_opcodes): Replace `M' with `m' for "restore".
1087
e207bc53
TP		 10882018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1089
1090 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1091
87993319
MR		 10922018-02-13 Maciej W. Rozycki <macro@mips.com>
1093
1094 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1095 variable to `function_index'.
1096
68d20676
NC		 10972018-02-13 Nick Clifton <nickc@redhat.com>
1098
1099 PR 22823
1100 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1101 about truncation of printing.
1102
d2159fdc
HW		 11032018-02-12 Henry Wong <henry@stuffedcow.net>
1104
1105 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1106
f174ef9f
NC		 11072018-02-05 Nick Clifton <nickc@redhat.com>
1108
1109 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1110
be3a8dca
IT		 11112018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1112
1113 * i386-dis.c (enum): Add pconfig.
1114 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1115 (cpu_flags): Add CpuPCONFIG.
1116 * i386-opc.h (enum): Add CpuPCONFIG.
1117 (i386_cpu_flags): Add cpupconfig.
1118 * i386-opc.tbl: Add PCONFIG instruction.
1119 * i386-init.h: Regenerate.
1120 * i386-tbl.h: Likewise.
1121
3233d7d0
IT		 11222018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1123
1124 * i386-dis.c (enum): Add PREFIX_0F09.
1125 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1126 (cpu_flags): Add CpuWBNOINVD.
1127 * i386-opc.h (enum): Add CpuWBNOINVD.
1128 (i386_cpu_flags): Add cpuwbnoinvd.
1129 * i386-opc.tbl: Add WBNOINVD instruction.
1130 * i386-init.h: Regenerate.
1131 * i386-tbl.h: Likewise.
1132
e925c834
JW		 11332018-01-17 Jim Wilson <jimw@sifive.com>
1134
1135 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1136
d777820b
IT		 11372018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1138
1139 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1140 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1141 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1142 (cpu_flags): Add CpuIBT, CpuSHSTK.
1143 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1144 (i386_cpu_flags): Add cpuibt, cpushstk.
1145 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1146 * i386-init.h: Regenerate.
1147 * i386-tbl.h: Likewise.
1148
f6efed01
NC		 11492018-01-16 Nick Clifton <nickc@redhat.com>
1150
1151 * po/pt_BR.po: Updated Brazilian Portugese translation.
1152 * po/de.po: Updated German translation.
1153
2721d702
JW		 11542018-01-15 Jim Wilson <jimw@sifive.com>
1155
1156 * riscv-opc.c (match_c_nop): New.
1157 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1158
616dcb87
NC		 11592018-01-15 Nick Clifton <nickc@redhat.com>
1160
1161 * po/uk.po: Updated Ukranian translation.
1162
3957a496
NC		 11632018-01-13 Nick Clifton <nickc@redhat.com>
1164
1165 * po/opcodes.pot: Regenerated.
1166
769c7ea5
NC		 11672018-01-13 Nick Clifton <nickc@redhat.com>
1168
1169 * configure: Regenerate.
1170
faf766e3
NC		 11712018-01-13 Nick Clifton <nickc@redhat.com>
1172
1173 2.30 branch created.
1174
888a89da
IT		 11752018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1176
1177 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1178 * i386-tbl.h: Regenerate.
1179
cbda583a
JB		 11802018-01-10 Jan Beulich <jbeulich@suse.com>
1181
1182 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1183 * i386-tbl.h: Re-generate.
1184
c9e92278
JB		 11852018-01-10 Jan Beulich <jbeulich@suse.com>
1186
1187 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1188 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1189 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1190 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1191 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1192 Disp8MemShift of AVX512VL forms.
1193 * i386-tbl.h: Re-generate.
1194
35fd2b2b
JW		 11952018-01-09 Jim Wilson <jimw@sifive.com>
1196
1197 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1198 then the hi_addr value is zero.
1199
91d8b670
JG		 12002018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1201
1202 * arm-dis.c (arm_opcodes): Add csdb.
1203 (thumb32_opcodes): Add csdb.
1204
be2e7d95
JG		 12052018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1206
1207 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1208 * aarch64-asm-2.c: Regenerate.
1209 * aarch64-dis-2.c: Regenerate.
1210 * aarch64-opc-2.c: Regenerate.
1211
704a705d
L		 12122018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1213
1214 PR gas/22681
1215 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1216 Remove AVX512 vmovd with 64-bit operands.
1217 * i386-tbl.h: Regenerated.
1218
35eeb78f
JW		 12192018-01-05 Jim Wilson <jimw@sifive.com>
1220
1221 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1222 jalr.
1223
219d1afa
AM		 12242018-01-03 Alan Modra <amodra@gmail.com>
1225
1226 Update year range in copyright notice of all files.
1227
1508bbf5
JB		 12282018-01-02 Jan Beulich <jbeulich@suse.com>
1229
1230 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1231 and OPERAND_TYPE_REGZMM entries.
1232
1e563868 1233For older changes see ChangeLog-2017
3499769a 1234\f
1e563868 1235Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1236
1237Copying and distribution of this file, with or without modification,
1238are permitted in any medium without royalty provided the copyright
1239notice and this notice are preserved.
1240
1241Local Variables:
1242mode: change-log
1243left-margin: 8
1244fill-column: 74
1245version-control: never
1246End:
GDB Binutils - Deliverables
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