[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (insert_ls): Test for invalid LS operands.
	(insert_esync): New function.
	(LS, WC): Use insert_ls.
	(ESYNC): Use insert_esync.

2015-06-22  Nick Clifton  <nickc@redhat.com>

	* dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
	requested region lies beyond it.
	* bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
	looking for 32-bit insns.
	* mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
	data.
	* sh-dis.c (print_insn_sh): Likewise.
	* tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
	blocks of instructions.
	* vax-dis.c (print_insn_vax): Check that the requested address
	does not clash with the stop_vma.

2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>

        * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
	* ppc-opc.c (FXM4): Add non-zero optional value.
	(TBR): Likewise.
	(SXL): Likewise.
	(insert_fxm): Handle new default operand value.
	(extract_fxm): Likewise.
	(insert_tbr): Likewise.
	(extract_tbr): Likewise.

2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>

	* arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".

2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* arm-dis.c (print_insn_coprocessor): Avoid negative shift.

2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c: Add comment accidentally removed by old commit.
	(MTMSRD_L): Delete.

2015-06-04  Nick Clifton  <nickc@redhat.com>

	PR 18474
	* msp430-dis.c (msp430_nooperands): Fix check for emulated insns.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* arm-dis.c (arm_opcodes): Add "setpan".
	(thumb_opcodes): Add "setpan".

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* arm-dis.c (select_arm_features): Rework to avoid used of redefined
	macros.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-tbl.h (aarch64_feature_rdma): New.
	(RDMA): New.
	(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-tbl.h (aarch64_feature_lor): New.
	(LOR): New.
	(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
	"stllrb", "stllrh".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (F_ARCHEXT): New.
	(aarch64_sys_regs): Add "pan".
	(aarch64_sys_reg_supported_p): New.
	(aarch64_pstatefields): Add "pan".
	(aarch64_pstatefield_supported_p): New.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-tbl.h: Regenerate.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (print_insn): Swap rounding mode specifier and
	general purpose register in Intel mode.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	* i386-tbl.h: Regenerate.

2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	* i386-init.h: Regenerated.

2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (IH) New define.
	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	<tlbie>: Add RS operand for POWER7.
	<slbia>: Add IH operand for POWER6.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
	direct branch.
	(jmp): Likewise.
	* i386-tbl.h: Regenerated.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.ac: Support bfd_iamcu_arch.
	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	CPU_IAMCU_COMPAT_FLAGS.
	(cpu_flags): Add CpuIAMCU.
	* i386-opc.h (CpuIAMCU): New.
	(i386_cpu_flags): Add cpuiamcu.
	* configure: Regenerated.
	* i386-init.h: Likewise.
	* i386-tbl.h: Likewise.

2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c (X86_64_E8): New.
	(X86_64_E9): Likewise.
	Update comments on 'T', 'U', 'V'.  Add comments for '^'.
	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	(mod_table): Replace {T|} with ^ on Jcall/Jmp.
	(putop): Handle '^'.
	(OP_J): Ignore the operand size prefix in 64-bit.  Don't check
	REX_W.

2015-04-30  DJ Delorie  <dj@redhat.com>

	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

2015-04-29  Nick Clifton  <nickc@redhat.com>

	* po/fr.po: Updated French translation.

2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (DCBT_EO): New define.
	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	<lharx>: Likewise.
	<stbcx.>: Likewise.
	<sthcx.>: Likewise.
	<waitrsv>: Do not enable for POWER7 and later.
	<waitimpl>: Likewise.
	<dcbt>: Default to the two operand form of the instruction for all
	"old" cpus.  For "new" cpus, use the operand ordering that matches
	whether the cpu is server or embedded.
	<dcbtst>: Likewise.

2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: New instruction type VV0UU2.
	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	and WFC.

2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	(vfpclasspd, vfpclassps): Add %XZ.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	(PREFIX_UD_REPZ): Likewise.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_requirement): Removed.
	(print_insn): Don't set prefix_requirement.  Check
	dp->prefix_requirement instead of prefix_requirement.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/17898
	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	(PREFIX_MOD_0_0FC7_REG_6): This.
	(PREFIX_MOD_3_0FC7_REG_6): New.
	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.
	(mod_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	(PREFIX_MANDATORY_REPNZ): Likewise.
	(PREFIX_MANDATORY_DATA): Likewise.
	(PREFIX_MANDATORY_ADDR): Likewise.
	(PREFIX_MANDATORY_LOCK): Likewise.
	(PREFIX_MANDATORY): Likewise.
	(PREFIX_UD_SHIFT): Set to 8
	(PREFIX_UD_REPZ): Updated.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.
	(PREFIX_IGNORED_SHIFT): New.
	(PREFIX_IGNORED_REPZ): Likewise.
	(PREFIX_IGNORED_REPNZ): Likewise.
	(PREFIX_IGNORED_DATA): Likewise.
	(PREFIX_IGNORED_ADDR): Likewise.
	(PREFIX_IGNORED_LOCK): Likewise.
	(PREFIX_OPCODE): Likewise.
	(PREFIX_IGNORED): Likewise.
	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	(three_byte_table): Likewise.
	(mod_table): Likewise.
	(mandatory_prefix): Renamed to ...
	(prefix_requirement): This.
	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	Update PREFIX_90 entry.
	(get_valid_dis386): Check prefix_requirement to see if a prefix
	should be ignored.
	(print_insn): Replace mandatory_prefix with prefix_requirement.

2015-04-15  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	use it for ssat and ssat16.
	(print_insn_thumb32): Add handle case for 'D' control code.

2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
	    H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	Fill prefix_requirement field.
	(struct dis386): Add prefix_requirement field.
	(dis386): Fill prefix_requirement field.
	(dis386_twobyte): Ditto.
	(twobyte_has_mandatory_prefix_: Remove.
	(reg_table): Fill prefix_requirement field.
	(prefix_table): Ditto.
	(x86_64_table): Ditto.
	(three_byte_table): Ditto.
	(xop_table): Ditto.
	(vex_table): Ditto.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(mod_table): Ditto.
	(bad_opcode): Ditto.
	(print_insn): Use prefix_requirement.
	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	(float_reg): Ditto.

2015-03-30  Mike Frysinger  <vapier@gentoo.org>

	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.

2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.in: Regenerated.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	powerpc_opcd_indices and vle_opcd_indices once.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-opc.c (powerpc_opcodes): Add slbfee.

2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	(opcode16): Likewise.
	(coprocessor_opcodes): Replace bit with feature struct.
	(neon_opcodes): Likewise.
	(arm_opcodes): Likewise.
	(thumb_opcodes): Likewise.
	(thumb32_opcodes): Likewise.
	(print_insn_coprocessor): Likewise.
	(print_insn_arm): Likewise.
	(select_arm_features): Follow new feature struct.

2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>

	* i386-dis.c (rm_table): Add clzero.
	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	Add CPU_CLZERO_FLAGS.
	(cpu_flags): Add CpuCLZERO.
	* i386-opc.h: Add CpuCLZERO.
	* i386-opc.tbl: Add clzero.
	* i386-init.h: Re-generated.
	* i386-tbl.h: Re-generated.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (decode_mips_operand): Fix constraint issues
	with u and y operands.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.

2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Add new IBM z13 instructions.
	* s390-opc.txt: Likewise.

2015-03-10  Renlin Li  <renlin.li@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	related alias.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

2015-03-03  Jiong Wang  <jiong.wang@arm.com>

	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.

2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>

	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	arch_sh_up.
	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.

2015-02-23  Vinay  <Vinay.G@kpit.com>

	* rl78-decode.opc (MOV): Added space between two operands for
	'mov' instruction in index addressing mode.
	* rl78-decode.c: Regenerate.

2015-02-19  Pedro Alves  <palves@redhat.com>

	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".

2015-02-10  Pedro Alves  <palves@redhat.com>
	    Tom Tromey  <tromey@redhat.com>

	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	microblaze_and, microblaze_xor.
	* microblaze-opc.h (opcodes): Adjust.

2015-01-28  James Bowman  <james.bowman@ftdichip.com>

	* Makefile.am: Add FT32 files.
	* configure.ac: Handle FT32.
	* disassemble.c (disassembler): Call print_insn_ft32.
	* ft32-dis.c: New file.
	* ft32-opc.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.

2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>

	* nds32-asm.c (keyword_sr): Add new system registers.

2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-dis.c (s390_extract_operand): Support vector register
	operands.
	(s390_print_insn_with_opcode): Support new operands types and add
	new handling of optional operands.
	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	and include opcode/s390.h instead.
	(struct op_struct): New field `flags'.
	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	(dumpTable): Dump flags.
	(main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
	string.
	* s390-opc.c: Add new operands types, instruction formats, and
	instruction masks.
	(s390_opformats): Add new formats for .insn.
	* s390-opc.txt: Add new instructions.

2015-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2014
\f
Copyright (C) 2015 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
7b934113 PB	1	2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
	2
	3	* ppc-opc.c (insert_ls): Test for invalid LS operands.
	4	(insert_esync): New function.
	5	(LS, WC): Use insert_ls.
	6	(ESYNC): Use insert_esync.
	7
bdc4de1b NC	8	2015-06-22 Nick Clifton <nickc@redhat.com>
	9
	10	* dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
	11	requested region lies beyond it.
	12	* bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
	13	looking for 32-bit insns.
	14	* mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
	15	data.
	16	* sh-dis.c (print_insn_sh): Likewise.
	17	* tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
	18	blocks of instructions.
	19	* vax-dis.c (print_insn_vax): Check that the requested address
	20	does not clash with the stop_vma.
	21
11a0cf2e PB	22	2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
	23
	24	* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
	25	* ppc-opc.c (FXM4): Add non-zero optional value.
	26	(TBR): Likewise.
	27	(SXL): Likewise.
	28	(insert_fxm): Handle new default operand value.
	29	(extract_fxm): Likewise.
	30	(insert_tbr): Likewise.
	31	(extract_tbr): Likewise.
	32
bdfa8b95 MW	33	2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
	34
	35	* arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
	36
24b4cf66 SN	37	2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
	38
	39	* arm-dis.c (print_insn_coprocessor): Avoid negative shift.
	40
99a2c561 PB	41	2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
	42
	43	* ppc-opc.c: Add comment accidentally removed by old commit.
	44	(MTMSRD_L): Delete.
	45
13be46a2 NC	46	2015-06-04 Nick Clifton <nickc@redhat.com>
	47
	48	PR 18474
	49	* msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
	50
ddfded2f MW	51	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	52
	53	* arm-dis.c (arm_opcodes): Add "setpan".
	54	(thumb_opcodes): Add "setpan".
	55
1af1dd51 MW	56	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	57
	58	* arm-dis.c (select_arm_features): Rework to avoid used of redefined
	59	macros.
	60
9e1f0fa7 MW	61	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	62
	63	* aarch64-tbl.h (aarch64_feature_rdma): New.
	64	(RDMA): New.
	65	(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
	66	* aarch64-asm-2.c: Regenerate.
	67	* aarch64-dis-2.c: Regenerate.
	68	* aarch64-opc-2.c: Regenerate.
	69
290806fd MW	70	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	71
	72	* aarch64-tbl.h (aarch64_feature_lor): New.
	73	(LOR): New.
	74	(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
	75	"stllrb", "stllrh".
	76	* aarch64-asm-2.c: Regenerate.
	77	* aarch64-dis-2.c: Regenerate.
	78	* aarch64-opc-2.c: Regenerate.
	79
f21cce2c MW	80	2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
	81
	82	* aarch64-opc.c (F_ARCHEXT): New.
	83	(aarch64_sys_regs): Add "pan".
	84	(aarch64_sys_reg_supported_p): New.
	85	(aarch64_pstatefields): Add "pan".
	86	(aarch64_pstatefield_supported_p): New.
	87
d194d186 JB	88	2015-06-01 Jan Beulich <jbeulich@suse.com>
	89
	90	* i386-tbl.h: Regenerate.
	91
3a8547d2 JB	92	2015-06-01 Jan Beulich <jbeulich@suse.com>
	93
	94	* i386-dis.c (print_insn): Swap rounding mode specifier and
	95	general purpose register in Intel mode.
	96
015c54d5 JB	97	2015-06-01 Jan Beulich <jbeulich@suse.com>
	98
	99	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	100	* i386-tbl.h: Regenerate.
	101
071f0063 L	102	2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
	103
	104	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	105	* i386-init.h: Regenerated.
	106
5db04b09 L	107	2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
	108
	109	PR binutis/18386
	110	* i386-dis.c: Add comments for '@'.
	111	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	112	(enum x86_64_isa): New.
	113	(isa64): Likewise.
	114	(print_i386_disassembler_options): Add amd64 and intel64.
	115	(print_insn): Handle amd64 and intel64.
	116	(putop): Handle '@'.
	117	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	118	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	119	* i386-opc.h (AMD64): New.
	120	(CpuIntel64): Likewise.
	121	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	122	* i386-opc.tbl: Add direct call/jmp with Disp16\|Disp32 for AMD64.
	123	Mark direct call/jmp without Disp16\|Disp32 as Intel64.
	124	* i386-init.h: Regenerated.
	125	* i386-tbl.h: Likewise.
	126
4bc0608a PB	127	2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
	128
	129	* ppc-opc.c (IH) New define.
	130	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	131	<tlbie>: Add RS operand for POWER7.
	132	<slbia>: Add IH operand for POWER6.
	133
70cead07 L	134	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	135
	136	* opcodes/i386-opc.tbl (call): Remove Disp16\|Disp32 from 64-bit
	137	direct branch.
	138	(jmp): Likewise.
	139	* i386-tbl.h: Regenerated.
	140
7b6d09fb L	141	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	142
	143	* configure.ac: Support bfd_iamcu_arch.
	144	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	145	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	146	CPU_IAMCU_COMPAT_FLAGS.
	147	(cpu_flags): Add CpuIAMCU.
	148	* i386-opc.h (CpuIAMCU): New.
	149	(i386_cpu_flags): Add cpuiamcu.
	150	* configure: Regenerated.
	151	* i386-init.h: Likewise.
	152	* i386-tbl.h: Likewise.
	153
31955f99 L	154	2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
	155
	156	PR binutis/18386
	157	* i386-dis.c (X86_64_E8): New.
	158	(X86_64_E9): Likewise.
	159	Update comments on 'T', 'U', 'V'. Add comments for '^'.
	160	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	161	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	162	(mod_table): Replace {T\|} with ^ on Jcall/Jmp.
	163	(putop): Handle '^'.
	164	(OP_J): Ignore the operand size prefix in 64-bit. Don't check
	165	REX_W.
	166
0952813b DD	167	2015-04-30 DJ Delorie <dj@redhat.com>
	168
	169	* disassemble.c (disassembler): Choose suitable disassembler based
	170	on E_ABI.
	171	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
	172	it to decode mul/div insns.
	173	* rl78-decode.c: Regenerate.
	174	* rl78-dis.c (print_insn_rl78): Rename to...
	175	(print_insn_rl78_common): ...this, take ISA parameter.
	176	(print_insn_rl78): New.
	177	(print_insn_rl78_g10): New.
	178	(print_insn_rl78_g13): New.
	179	(print_insn_rl78_g14): New.
	180	(rl78_get_disassembler): New.
	181
f9d3ecaa NC	182	2015-04-29 Nick Clifton <nickc@redhat.com>
	183
	184	* po/fr.po: Updated French translation.
	185
4fff86c5 PB	186	2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
	187
	188	* ppc-opc.c (DCBT_EO): New define.
	189	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	190	<lharx>: Likewise.
	191	<stbcx.>: Likewise.
	192	<sthcx.>: Likewise.
	193	<waitrsv>: Do not enable for POWER7 and later.
	194	<waitimpl>: Likewise.
	195	<dcbt>: Default to the two operand form of the instruction for all
	196	"old" cpus. For "new" cpus, use the operand ordering that matches
	197	whether the cpu is server or embedded.
	198	<dcbtst>: Likewise.
	199
3b78cfe1 AK	200	2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	201
	202	* s390-opc.c: New instruction type VV0UU2.
	203	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	204	and WFC.
	205
04d824a4 JB	206	2015-04-23 Jan Beulich <jbeulich@suse.com>
	207
	208	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	209	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	210	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	211	(vfpclasspd, vfpclassps): Add %XZ.
	212
09708981 L	213	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	214
	215	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	216	(PREFIX_UD_REPZ): Likewise.
	217	(PREFIX_UD_REPNZ): Likewise.
	218	(PREFIX_UD_DATA): Likewise.
	219	(PREFIX_UD_ADDR): Likewise.
	220	(PREFIX_UD_LOCK): Likewise.
	221
3888916d L	222	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	223
	224	* i386-dis.c (prefix_requirement): Removed.
	225	(print_insn): Don't set prefix_requirement. Check
	226	dp->prefix_requirement instead of prefix_requirement.
	227
f24bcbaa L	228	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	229
	230	PR binutils/17898
	231	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	232	(PREFIX_MOD_0_0FC7_REG_6): This.
	233	(PREFIX_MOD_3_0FC7_REG_6): New.
	234	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	235	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	236	PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
	237	PREFIX_MOD_3_0FC7_REG_7.
	238	(mod_table): Replace PREFIX_0FC7_REG_6 with
	239	PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
	240	PREFIX_MOD_3_0FC7_REG_7.
	241
507bd325 L	242	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	243
	244	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	245	(PREFIX_MANDATORY_REPNZ): Likewise.
	246	(PREFIX_MANDATORY_DATA): Likewise.
	247	(PREFIX_MANDATORY_ADDR): Likewise.
	248	(PREFIX_MANDATORY_LOCK): Likewise.
	249	(PREFIX_MANDATORY): Likewise.
	250	(PREFIX_UD_SHIFT): Set to 8
	251	(PREFIX_UD_REPZ): Updated.
	252	(PREFIX_UD_REPNZ): Likewise.
	253	(PREFIX_UD_DATA): Likewise.
	254	(PREFIX_UD_ADDR): Likewise.
	255	(PREFIX_UD_LOCK): Likewise.
	256	(PREFIX_IGNORED_SHIFT): New.
	257	(PREFIX_IGNORED_REPZ): Likewise.
	258	(PREFIX_IGNORED_REPNZ): Likewise.
	259	(PREFIX_IGNORED_DATA): Likewise.
	260	(PREFIX_IGNORED_ADDR): Likewise.
	261	(PREFIX_IGNORED_LOCK): Likewise.
	262	(PREFIX_OPCODE): Likewise.
	263	(PREFIX_IGNORED): Likewise.
	264	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	265	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	266	(three_byte_table): Likewise.
	267	(mod_table): Likewise.
	268	(mandatory_prefix): Renamed to ...
	269	(prefix_requirement): This.
	270	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	271	Update PREFIX_90 entry.
	272	(get_valid_dis386): Check prefix_requirement to see if a prefix
	273	should be ignored.
	274	(print_insn): Replace mandatory_prefix with prefix_requirement.
	275
f0fba320 RL	276	2015-04-15 Renlin Li <renlin.li@arm.com>
	277
	278	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	279	use it for ssat and ssat16.
	280	(print_insn_thumb32): Add handle case for 'D' control code.
	281
bf890a93 IT	282	2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
	283	H.J. Lu <hongjiu.lu@intel.com>
	284
	285	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	286	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	287	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	288	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	289	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	290	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	291	Fill prefix_requirement field.
	292	(struct dis386): Add prefix_requirement field.
	293	(dis386): Fill prefix_requirement field.
	294	(dis386_twobyte): Ditto.
	295	(twobyte_has_mandatory_prefix_: Remove.
	296	(reg_table): Fill prefix_requirement field.
	297	(prefix_table): Ditto.
	298	(x86_64_table): Ditto.
	299	(three_byte_table): Ditto.
	300	(xop_table): Ditto.
	301	(vex_table): Ditto.
	302	(vex_len_table): Ditto.
	303	(vex_w_table): Ditto.
	304	(mod_table): Ditto.
	305	(bad_opcode): Ditto.
	306	(print_insn): Use prefix_requirement.
	307	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	308	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	309	(float_reg): Ditto.
	310
2f783c1f MF	311	2015-03-30 Mike Frysinger <vapier@gentoo.org>
	312
	313	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
	314
b9d94d62 L	315	2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
	316
	317	* Makefile.in: Regenerated.
	318
27c49e9a AB	319	2015-03-25 Anton Blanchard <anton@samba.org>
	320
	321	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	322	powerpc_opcd_indices and vle_opcd_indices once.
	323
c4e676f1 AB	324	2015-03-25 Anton Blanchard <anton@samba.org>
	325
	326	* ppc-opc.c (powerpc_opcodes): Add slbfee.
	327
823d2571 TG	328	2015-03-24 Terry Guo <terry.guo@arm.com>
	329
	330	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	331	(opcode16): Likewise.
	332	(coprocessor_opcodes): Replace bit with feature struct.
	333	(neon_opcodes): Likewise.
	334	(arm_opcodes): Likewise.
	335	(thumb_opcodes): Likewise.
	336	(thumb32_opcodes): Likewise.
	337	(print_insn_coprocessor): Likewise.
	338	(print_insn_arm): Likewise.
	339	(select_arm_features): Follow new feature struct.
	340
029f3522 GG	341	2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
	342
	343	* i386-dis.c (rm_table): Add clzero.
	344	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	345	Add CPU_CLZERO_FLAGS.
	346	(cpu_flags): Add CpuCLZERO.
	347	* i386-opc.h: Add CpuCLZERO.
	348	* i386-opc.tbl: Add clzero.
	349	* i386-init.h: Re-generated.
	350	* i386-tbl.h: Re-generated.
	351
6914869a AB	352	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	353
	354	* mips-opc.c (decode_mips_operand): Fix constraint issues
	355	with u and y operands.
	356
21e20815 AB	357	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	358
	359	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
	360
6b1d7593 AK	361	2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	362
	363	* s390-opc.c: Add new IBM z13 instructions.
	364	* s390-opc.txt: Likewise.
	365
c8f89a34 JW	366	2015-03-10 Renlin Li <renlin.li@arm.com>
	367
	368	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	369	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	370	related alias.
	371	* aarch64-asm-2.c: Regenerate.
	372	* aarch64-dis-2.c: Likewise.
	373	* aarch64-opc-2.c: Likewise.
	374
d8282f0e JW	375	2015-03-03 Jiong Wang <jiong.wang@arm.com>
	376
	377	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
	378
ac994365 OE	379	2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
	380
	381	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	382	arch_sh_up.
	383	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	384	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
	385
fd63f640 V	386	2015-02-23 Vinay <Vinay.G@kpit.com>
	387
	388	* rl78-decode.opc (MOV): Added space between two operands for
	389	'mov' instruction in index addressing mode.
	390	* rl78-decode.c: Regenerate.
	391
f63c1776 PA	392	2015-02-19 Pedro Alves <palves@redhat.com>
	393
	394	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
	395
07774fcc PA	396	2015-02-10 Pedro Alves <palves@redhat.com>
	397	Tom Tromey <tromey@redhat.com>
	398
	399	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	400	microblaze_and, microblaze_xor.
	401	* microblaze-opc.h (opcodes): Adjust.
	402
3f8107ab AM	403	2015-01-28 James Bowman <james.bowman@ftdichip.com>
	404
	405	* Makefile.am: Add FT32 files.
	406	* configure.ac: Handle FT32.
	407	* disassemble.c (disassembler): Call print_insn_ft32.
	408	* ft32-dis.c: New file.
	409	* ft32-opc.c: New file.
	410	* Makefile.in: Regenerate.
	411	* configure: Regenerate.
	412	* po/POTFILES.in: Regenerate.
	413
e5fe4957 KLC	414	2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
	415
	416	* nds32-asm.c (keyword_sr): Add new system registers.
	417
1e2e8c52 AK	418	2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	419
	420	* s390-dis.c (s390_extract_operand): Support vector register
	421	operands.
	422	(s390_print_insn_with_opcode): Support new operands types and add
	423	new handling of optional operands.
	424	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	425	and include opcode/s390.h instead.
	426	(struct op_struct): New field `flags'.
	427	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	428	(dumpTable): Dump flags.
	429	(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
	430	string.
	431	* s390-opc.c: Add new operands types, instruction formats, and
	432	instruction masks.
	433	(s390_opformats): Add new formats for .insn.
	434	* s390-opc.txt: Add new instructions.
	435
b90efa5b	436	2015-01-01 Alan Modra <amodra@gmail.com>
bffb6004	437
b90efa5b	438	Update year range in copyright notice of all files.
bffb6004	439
b90efa5b	440	For older changes see ChangeLog-2014
252b5132	441	\f
b90efa5b	442	Copyright (C) 2015 Free Software Foundation, Inc.
752937aa NC	443
	444	Copying and distribution of this file, with or without modification,
	445	are permitted in any medium without royalty provided the copyright
	446	notice and this notice are preserved.
	447
252b5132	448	Local Variables:
2f6d2f85 NC	449	mode: change-log
	450	left-margin: 8
	451	fill-column: 74
252b5132 RH	452	version-control: never
252b5132 RH	453	End: