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X86: Merge AVX512F vmovq
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7efeed17
L		 12016-11-09 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-opc.tbl: Merge AVX512F vmovq.
4
1f334aeb
L		 52016-11-08 H.J. Lu <hongjiu.lu@intel.com>
6
7 PR binutils/20701
8 * i386-dis.c (THREE_BYTE_0F7A): Removed.
9 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
10 (three_byte_table): Remove THREE_BYTE_0F7A.
11
48c97fa1
L		 122016-11-07 H.J. Lu <hongjiu.lu@intel.com>
13
14 PR binutils/20775
15 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
16 (FGRPd9_4): Replace 1 with 2.
17 (FGRPd9_5): Replace 2 with 3.
18 (FGRPd9_6): Replace 3 with 4.
19 (FGRPd9_7): Replace 4 with 5.
20 (FGRPda_5): Replace 5 with 6.
21 (FGRPdb_4): Replace 6 with 7.
22 (FGRPde_3): Replace 7 with 8.
23 (FGRPdf_4): Replace 8 with 9.
24 (fgrps): Add an entry for Bad_Opcode.
25
b437d035
AB		 262016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
27
28 * arc-opc.c (arc_flag_operands): Add F_DI14.
29 (arc_flag_classes): Add C_DI14.
30 * arc-nps400-tbl.h: Add new exc instructions.
31
5a736821
GM		 322016-11-03 Graham Markall <graham.markall@embecosm.com>
33
34 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
35 major opcode 0xa.
36 * arc-nps-400-tbl.h: Add dcmac instruction.
37 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
38 (insert_nps_rbdouble_64): Added.
39 (extract_nps_rbdouble_64): Added.
40 (insert_nps_proto_size): Added.
41 (extract_nps_proto_size): Added.
42
bdfe53e3
AB		 432016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
44
45 * arc-dis.c (struct arc_operand_iterator): Remove all fields
46 relating to long instruction processing, add new limm field.
47 (OPCODE): Rename to...
48 (OPCODE_32BIT_INSN): ...this.
49 (OPCODE_AC): Delete.
50 (skip_this_opcode): Handle different instruction lengths, update
51 macro name.
52 (special_flag_p): Update parameter type.
53 (find_format_from_table): Update for more instruction lengths.
54 (find_format_long_instructions): Delete.
55 (find_format): Update for more instruction lengths.
56 (arc_insn_length): Likewise.
57 (extract_operand_value): Update for more instruction lengths.
58 (operand_iterator_next): Remove code relating to long
59 instructions.
60 (arc_opcode_to_insn_type): New function.
61 (print_insn_arc):Update for more instructions lengths.
62 * arc-ext.c (extInstruction_t): Change argument type.
63 * arc-ext.h (extInstruction_t): Change argument type.
64 * arc-fxi.h: Change type unsigned to unsigned long long
65 extensively throughout.
66 * arc-nps400-tbl.h: Add long instructions taken from
67 arc_long_opcodes table in arc-opc.c.
68 * arc-opc.c: Update parameter types on insert/extract handlers.
69 (arc_long_opcodes): Delete.
70 (arc_num_long_opcodes): Delete.
71 (arc_opcode_len): Update for more instruction lengths.
72
90f61cce
GM		 732016-11-03 Graham Markall <graham.markall@embecosm.com>
74
75 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
76
06fe285f
GM		 772016-11-03 Graham Markall <graham.markall@embecosm.com>
78
79 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
80 with arc_opcode_len.
81 (find_format_long_instructions): Likewise.
82 * arc-opc.c (arc_opcode_len): New function.
83
ecf64ec6
AB		 842016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
85
86 * arc-nps400-tbl.h: Fix some instruction masks.
87
d039fef3
L		 882016-11-03 H.J. Lu <hongjiu.lu@intel.com>
89
90 * i386-dis.c (REG_82): Removed.
91 (X86_64_82_REG_0): Likewise.
92 (X86_64_82_REG_1): Likewise.
93 (X86_64_82_REG_2): Likewise.
94 (X86_64_82_REG_3): Likewise.
95 (X86_64_82_REG_4): Likewise.
96 (X86_64_82_REG_5): Likewise.
97 (X86_64_82_REG_6): Likewise.
98 (X86_64_82_REG_7): Likewise.
99 (X86_64_82): New.
100 (dis386): Use X86_64_82 instead of REG_82.
101 (reg_table): Remove REG_82.
102 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
103 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
104 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
105 X86_64_82_REG_7.
106
8b89fe14
L		 1072016-11-03 H.J. Lu <hongjiu.lu@intel.com>
108
109 PR binutils/20754
110 * i386-dis.c (REG_82): New.
111 (X86_64_82_REG_0): Likewise.
112 (X86_64_82_REG_1): Likewise.
113 (X86_64_82_REG_2): Likewise.
114 (X86_64_82_REG_3): Likewise.
115 (X86_64_82_REG_4): Likewise.
116 (X86_64_82_REG_5): Likewise.
117 (X86_64_82_REG_6): Likewise.
118 (X86_64_82_REG_7): Likewise.
119 (dis386): Use REG_82.
120 (reg_table): Add REG_82.
121 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
122 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
123 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
124
7148c369
L		 1252016-11-03 H.J. Lu <hongjiu.lu@intel.com>
126
127 * i386-dis.c (REG_82): Renamed to ...
128 (REG_83): This.
129 (dis386): Updated.
130 (reg_table): Likewise.
131
47acf0bd
IT		 1322016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
133
134 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
135 * i386-dis-evex.h (evex_table): Updated.
136 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
137 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
138 (cpu_flags): Add CpuAVX512_4VNNIW.
139 * i386-opc.h (enum): (AVX512_4VNNIW): New.
140 (i386_cpu_flags): Add cpuavx512_4vnniw.
141 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
142 * i386-init.h: Regenerate.
143 * i386-tbl.h: Ditto.
144
920d2ddc
IT		 1452016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
146
147 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
148 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
149 * i386-dis-evex.h (evex_table): Updated.
150 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
151 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
152 (cpu_flags): Add CpuAVX512_4FMAPS.
153 (opcode_modifiers): Add ImplicitQuadGroup modifier.
154 * i386-opc.h (AVX512_4FMAP): New.
155 (i386_cpu_flags): Add cpuavx512_4fmaps.
156 (ImplicitQuadGroup): New.
157 (i386_opcode_modifier): Add implicitquadgroup.
158 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
159 * i386-init.h: Regenerate.
160 * i386-tbl.h: Ditto.
161
e23eba97
NC		 1622016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
163 Andrew Waterman <andrew@sifive.com>
164
165 Add support for RISC-V architecture.
166 * configure.ac: Add entry for bfd_riscv_arch.
167 * configure: Regenerate.
168 * disassemble.c (disassembler): Add support for riscv.
169 (disassembler_usage): Likewise.
170 * riscv-dis.c: New file.
171 * riscv-opc.c: New file.
172
b5cefcca
L		 1732016-10-21 H.J. Lu <hongjiu.lu@intel.com>
174
175 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
176 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
177 (rm_table): Update the RM_0FAE_REG_7 entry.
178 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
179 (cpu_flags): Remove CpuPCOMMIT.
180 * i386-opc.h (CpuPCOMMIT): Removed.
181 (i386_cpu_flags): Remove cpupcommit.
182 * i386-opc.tbl: Remove pcommit.
183 * i386-init.h: Regenerated.
184 * i386-tbl.h: Likewise.
185
9889cbb1
L		 1862016-10-20 H.J. Lu <hongjiu.lu@intel.com>
187
188 PR binutis/20705
189 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
190 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
191 32-bit mode. Don't check vex.register_specifier in 32-bit
192 mode.
193 (OP_VEX): Check for invalid mask registers.
194
28596323
L		 1952016-10-18 H.J. Lu <hongjiu.lu@intel.com>
196
197 PR binutis/20699
198 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
199 sizeflag.
200
da8d7d66
L		 2012016-10-18 H.J. Lu <hongjiu.lu@intel.com>
202
203 PR binutis/20704
204 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
205
eaf02703
MR		 2062016-10-18 Maciej W. Rozycki <macro@imgtec.com>
207
208 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
209 local variable to `index_regno'.
210
decf5bd1
CM		 2112016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
212
213 * arc-tbl.h: Removed any "inv.+" instructions from the table.
214
e5b06ef0
CZ		 2152016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
216
217 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
218 usage on ISA basis.
219
93562a34
JW		 2202016-10-11 Jiong Wang <jiong.wang@arm.com>
221
222 PR target/20666
223 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
224
362c0c4d
JW		 2252016-10-07 Jiong Wang <jiong.wang@arm.com>
226
227 PR target/20667
228 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
229 available.
230
1047201f
AM		 2312016-10-07 Alan Modra <amodra@gmail.com>
232
233 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
234
1a0670f3
AM		 2352016-10-06 Alan Modra <amodra@gmail.com>
236
237 * aarch64-opc.c: Spell fall through comments consistently.
238 * i386-dis.c: Likewise.
239 * aarch64-dis.c: Add missing fall through comments.
240 * aarch64-opc.c: Likewise.
241 * arc-dis.c: Likewise.
242 * arm-dis.c: Likewise.
243 * i386-dis.c: Likewise.
244 * m68k-dis.c: Likewise.
245 * mep-asm.c: Likewise.
246 * ns32k-dis.c: Likewise.
247 * sh-dis.c: Likewise.
248 * tic4x-dis.c: Likewise.
249 * tic6x-dis.c: Likewise.
250 * vax-dis.c: Likewise.
251
2b804145
AM		 2522016-10-06 Alan Modra <amodra@gmail.com>
253
254 * arc-ext.c (create_map): Add missing break.
255 * msp430-decode.opc (encode_as): Likewise.
256 * msp430-decode.c: Regenerate.
257
616ec358
AM		 2582016-10-06 Alan Modra <amodra@gmail.com>
259
260 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
261 * crx-dis.c (print_insn_crx): Likewise.
262
72da393d
L		 2632016-09-30 H.J. Lu <hongjiu.lu@intel.com>
264
265 PR binutils/20657
266 * i386-dis.c (putop): Don't assign alt twice.
267
744ce302
JW		 2682016-09-29 Jiong Wang <jiong.wang@arm.com>
269
270 PR target/20553
271 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
272
a5721ba2
AM		 2732016-09-29 Alan Modra <amodra@gmail.com>
274
275 * ppc-opc.c (L): Make compulsory.
276 (LOPT): New, optional form of L.
277 (HTM_R): Define as LOPT.
278 (L0, L1): Delete.
279 (L32OPT): New, optional for 32-bit L.
280 (L2OPT): New, 2-bit L for dcbf.
281 (SVC_LEC): Update.
282 (L2): Define.
283 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
284 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
285 <dcbf>: Use L2OPT.
286 <tlbiel, tlbie>: Use LOPT.
287 <wclr, wclrall>: Use L2.
288
c5da1932
VZ		 2892016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
290
291 * Makefile.in: Regenerate.
292 * configure: Likewise.
293
2b848ebd
CZ		 2942016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
295
296 * arc-ext-tbl.h (EXTINSN2OPF): Define.
297 (EXTINSN2OP): Use EXTINSN2OPF.
298 (bspeekm, bspop, modapp): New extension instructions.
299 * arc-opc.c (F_DNZ_ND): Define.
300 (F_DNZ_D): Likewise.
301 (F_SIZEB1): Changed.
302 (C_DNZ_D): Define.
303 (C_HARD): Changed.
304 * arc-tbl.h (dbnz): New instruction.
305 (prealloc): Allow it for ARC EM.
306 (xbfu): Likewise.
307
ad43e107
RS		 3082016-09-21 Richard Sandiford <richard.sandiford@arm.com>
309
310 * aarch64-opc.c (print_immediate_offset_address): Print spaces
311 after commas in addresses.
312 (aarch64_print_operand): Likewise.
313
ab3b8fcf
RS		 3142016-09-21 Richard Sandiford <richard.sandiford@arm.com>
315
316 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
317 rather than "should be" or "expected to be" in error messages.
318
bb7eff52
RS		 3192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
320
321 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
322 (print_mnemonic_name): ...here.
323 (print_comment): New function.
324 (print_aarch64_insn): Call it.
325 * aarch64-opc.c (aarch64_conds): Add SVE names.
326 (aarch64_print_operand): Print alternative condition names in
327 a comment.
328
c0890d26
RS		 3292016-09-21 Richard Sandiford <richard.sandiford@arm.com>
330
331 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
332 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
333 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
334 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
335 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
336 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
337 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
338 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
339 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
340 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
341 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
342 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
343 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
344 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
345 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
346 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
347 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
348 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
349 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
350 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
351 (OP_SVE_XWU, OP_SVE_XXU): New macros.
352 (aarch64_feature_sve): New variable.
353 (SVE): New macro.
354 (_SVE_INSN): Likewise.
355 (aarch64_opcode_table): Add SVE instructions.
356 * aarch64-opc.h (extract_fields): Declare.
357 * aarch64-opc-2.c: Regenerate.
358 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
359 * aarch64-asm-2.c: Regenerate.
360 * aarch64-dis.c (extract_fields): Make global.
361 (do_misc_decoding): Handle the new SVE aarch64_ops.
362 * aarch64-dis-2.c: Regenerate.
363
116b6019
RS		 3642016-09-21 Richard Sandiford <richard.sandiford@arm.com>
365
366 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
367 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
368 aarch64_field_kinds.
369 * aarch64-opc.c (fields): Add corresponding entries.
370 * aarch64-asm.c (aarch64_get_variant): New function.
371 (aarch64_encode_variant_using_iclass): Likewise.
372 (aarch64_opcode_encode): Call it.
373 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
374 (aarch64_opcode_decode): Call it.
375
047cd301
RS		 3762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
377
378 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
379 and FP register operands.
380 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
381 (FLD_SVE_Vn): New aarch64_field_kinds.
382 * aarch64-opc.c (fields): Add corresponding entries.
383 (aarch64_print_operand): Handle the new SVE core and FP register
384 operands.
385 * aarch64-opc-2.c: Regenerate.
386 * aarch64-asm-2.c: Likewise.
387 * aarch64-dis-2.c: Likewise.
388
165d4950
RS		 3892016-09-21 Richard Sandiford <richard.sandiford@arm.com>
390
391 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
392 immediate operands.
393 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
394 * aarch64-opc.c (fields): Add corresponding entry.
395 (operand_general_constraint_met_p): Handle the new SVE FP immediate
396 operands.
397 (aarch64_print_operand): Likewise.
398 * aarch64-opc-2.c: Regenerate.
399 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
400 (ins_sve_float_zero_one): New inserters.
401 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
402 (aarch64_ins_sve_float_half_two): Likewise.
403 (aarch64_ins_sve_float_zero_one): Likewise.
404 * aarch64-asm-2.c: Regenerate.
405 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
406 (ext_sve_float_zero_one): New extractors.
407 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
408 (aarch64_ext_sve_float_half_two): Likewise.
409 (aarch64_ext_sve_float_zero_one): Likewise.
410 * aarch64-dis-2.c: Regenerate.
411
e950b345
RS		 4122016-09-21 Richard Sandiford <richard.sandiford@arm.com>
413
414 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
415 integer immediate operands.
416 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
417 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
418 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
419 * aarch64-opc.c (fields): Add corresponding entries.
420 (operand_general_constraint_met_p): Handle the new SVE integer
421 immediate operands.
422 (aarch64_print_operand): Likewise.
423 (aarch64_sve_dupm_mov_immediate_p): New function.
424 * aarch64-opc-2.c: Regenerate.
425 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
426 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
427 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
428 (aarch64_ins_limm): ...here.
429 (aarch64_ins_inv_limm): New function.
430 (aarch64_ins_sve_aimm): Likewise.
431 (aarch64_ins_sve_asimm): Likewise.
432 (aarch64_ins_sve_limm_mov): Likewise.
433 (aarch64_ins_sve_shlimm): Likewise.
434 (aarch64_ins_sve_shrimm): Likewise.
435 * aarch64-asm-2.c: Regenerate.
436 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
437 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
438 * aarch64-dis.c (decode_limm): New function, split out from...
439 (aarch64_ext_limm): ...here.
440 (aarch64_ext_inv_limm): New function.
441 (decode_sve_aimm): Likewise.
442 (aarch64_ext_sve_aimm): Likewise.
443 (aarch64_ext_sve_asimm): Likewise.
444 (aarch64_ext_sve_limm_mov): Likewise.
445 (aarch64_top_bit): Likewise.
446 (aarch64_ext_sve_shlimm): Likewise.
447 (aarch64_ext_sve_shrimm): Likewise.
448 * aarch64-dis-2.c: Regenerate.
449
98907a70
RS		 4502016-09-21 Richard Sandiford <richard.sandiford@arm.com>
451
452 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
453 operands.
454 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
455 the AARCH64_MOD_MUL_VL entry.
456 (value_aligned_p): Cope with non-power-of-two alignments.
457 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
458 (print_immediate_offset_address): Likewise.
459 (aarch64_print_operand): Likewise.
460 * aarch64-opc-2.c: Regenerate.
461 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
462 (ins_sve_addr_ri_s9xvl): New inserters.
463 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
464 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
465 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
466 * aarch64-asm-2.c: Regenerate.
467 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
468 (ext_sve_addr_ri_s9xvl): New extractors.
469 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
470 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
471 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
472 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
473 * aarch64-dis-2.c: Regenerate.
474
4df068de
RS		 4752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
476
477 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
478 address operands.
479 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
480 (FLD_SVE_xs_22): New aarch64_field_kinds.
481 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
482 (get_operand_specific_data): New function.
483 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
484 FLD_SVE_xs_14 and FLD_SVE_xs_22.
485 (operand_general_constraint_met_p): Handle the new SVE address
486 operands.
487 (sve_reg): New array.
488 (get_addr_sve_reg_name): New function.
489 (aarch64_print_operand): Handle the new SVE address operands.
490 * aarch64-opc-2.c: Regenerate.
491 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
492 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
493 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
494 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
495 (aarch64_ins_sve_addr_rr_lsl): Likewise.
496 (aarch64_ins_sve_addr_rz_xtw): Likewise.
497 (aarch64_ins_sve_addr_zi_u5): Likewise.
498 (aarch64_ins_sve_addr_zz): Likewise.
499 (aarch64_ins_sve_addr_zz_lsl): Likewise.
500 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
501 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
502 * aarch64-asm-2.c: Regenerate.
503 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
504 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
505 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
506 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
507 (aarch64_ext_sve_addr_ri_u6): Likewise.
508 (aarch64_ext_sve_addr_rr_lsl): Likewise.
509 (aarch64_ext_sve_addr_rz_xtw): Likewise.
510 (aarch64_ext_sve_addr_zi_u5): Likewise.
511 (aarch64_ext_sve_addr_zz): Likewise.
512 (aarch64_ext_sve_addr_zz_lsl): Likewise.
513 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
514 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
515 * aarch64-dis-2.c: Regenerate.
516
2442d846
RS		 5172016-09-21 Richard Sandiford <richard.sandiford@arm.com>
518
519 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
520 AARCH64_OPND_SVE_PATTERN_SCALED.
521 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
522 * aarch64-opc.c (fields): Add a corresponding entry.
523 (set_multiplier_out_of_range_error): New function.
524 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
525 (operand_general_constraint_met_p): Handle
526 AARCH64_OPND_SVE_PATTERN_SCALED.
527 (print_register_offset_address): Use PRIi64 to print the
528 shift amount.
529 (aarch64_print_operand): Likewise. Handle
530 AARCH64_OPND_SVE_PATTERN_SCALED.
531 * aarch64-opc-2.c: Regenerate.
532 * aarch64-asm.h (ins_sve_scale): New inserter.
533 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
534 * aarch64-asm-2.c: Regenerate.
535 * aarch64-dis.h (ext_sve_scale): New inserter.
536 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
537 * aarch64-dis-2.c: Regenerate.
538
245d2e3f
RS		 5392016-09-21 Richard Sandiford <richard.sandiford@arm.com>
540
541 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
542 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
543 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
544 (FLD_SVE_prfop): Likewise.
545 * aarch64-opc.c: Include libiberty.h.
546 (aarch64_sve_pattern_array): New variable.
547 (aarch64_sve_prfop_array): Likewise.
548 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
549 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
550 AARCH64_OPND_SVE_PRFOP.
551 * aarch64-asm-2.c: Regenerate.
552 * aarch64-dis-2.c: Likewise.
553 * aarch64-opc-2.c: Likewise.
554
d50c751e
RS		 5552016-09-21 Richard Sandiford <richard.sandiford@arm.com>
556
557 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
558 AARCH64_OPND_QLF_P_[ZM].
559 (aarch64_print_operand): Print /z and /m where appropriate.
560
f11ad6bc
RS		 5612016-09-21 Richard Sandiford <richard.sandiford@arm.com>
562
563 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
564 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
565 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
566 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
567 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
568 * aarch64-opc.c (fields): Add corresponding entries here.
569 (operand_general_constraint_met_p): Check that SVE register lists
570 have the correct length. Check the ranges of SVE index registers.
571 Check for cases where p8-p15 are used in 3-bit predicate fields.
572 (aarch64_print_operand): Handle the new SVE operands.
573 * aarch64-opc-2.c: Regenerate.
574 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
575 * aarch64-asm.c (aarch64_ins_sve_index): New function.
576 (aarch64_ins_sve_reglist): Likewise.
577 * aarch64-asm-2.c: Regenerate.
578 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
579 * aarch64-dis.c (aarch64_ext_sve_index): New function.
580 (aarch64_ext_sve_reglist): Likewise.
581 * aarch64-dis-2.c: Regenerate.
582
0c608d6b
RS		 5832016-09-21 Richard Sandiford <richard.sandiford@arm.com>
584
585 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
586 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
587 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
588 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
589 tied operands.
590
01dbfe4c
RS		 5912016-09-21 Richard Sandiford <richard.sandiford@arm.com>
592
593 * aarch64-opc.c (get_offset_int_reg_name): New function.
594 (print_immediate_offset_address): Likewise.
595 (print_register_offset_address): Take the base and offset
596 registers as parameters.
597 (aarch64_print_operand): Update caller accordingly. Use
598 print_immediate_offset_address.
599
72e9f319
RS		 6002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
601
602 * aarch64-opc.c (BANK): New macro.
603 (R32, R64): Take a register number as argument
604 (int_reg): Use BANK.
605
8a7f0c1b
RS		 6062016-09-21 Richard Sandiford <richard.sandiford@arm.com>
607
608 * aarch64-opc.c (print_register_list): Add a prefix parameter.
609 (aarch64_print_operand): Update accordingly.
610
aa2aa4c6
RS		 6112016-09-21 Richard Sandiford <richard.sandiford@arm.com>
612
613 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
614 for FPIMM.
615 * aarch64-asm.h (ins_fpimm): New inserter.
616 * aarch64-asm.c (aarch64_ins_fpimm): New function.
617 * aarch64-asm-2.c: Regenerate.
618 * aarch64-dis.h (ext_fpimm): New extractor.
619 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
620 (aarch64_ext_fpimm): New function.
621 * aarch64-dis-2.c: Regenerate.
622
b5464a68
RS		 6232016-09-21 Richard Sandiford <richard.sandiford@arm.com>
624
625 * aarch64-asm.c: Include libiberty.h.
626 (insert_fields): New function.
627 (aarch64_ins_imm): Use it.
628 * aarch64-dis.c (extract_fields): New function.
629 (aarch64_ext_imm): Use it.
630
42408347
RS		 6312016-09-21 Richard Sandiford <richard.sandiford@arm.com>
632
633 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
634 with an esize parameter.
635 (operand_general_constraint_met_p): Update accordingly.
636 Fix misindented code.
637 * aarch64-asm.c (aarch64_ins_limm): Update call to
638 aarch64_logical_immediate_p.
639
4989adac
RS		 6402016-09-21 Richard Sandiford <richard.sandiford@arm.com>
641
642 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
643
bd11d5d8
RS		 6442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
645
646 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
647
f807f43d
CZ		 6482016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
649
650 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
651
fd486b63
PB		 6522016-09-14 Peter Bergner <bergner@vnet.ibm.com>
653
654 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
655 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
656 xor3>: Delete mnemonics.
657 <cp_abort>: Rename mnemonic from ...
658 <cpabort>: ...to this.
659 <setb>: Change to a X form instruction.
660 <sync>: Change to 1 operand form.
661 <copy>: Delete mnemonic.
662 <copy_first>: Rename mnemonic from ...
663 <copy>: ...to this.
664 <paste, paste.>: Delete mnemonics.
665 <paste_last>: Rename mnemonic from ...
666 <paste.>: ...to this.
667
dce08442
AK		 6682016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
669
670 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
671
952c3f51
AK		 6722016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
673
674 * s390-mkopc.c (main): Support alternate arch strings.
675
8b71537b
PS		 6762016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
677
678 * s390-opc.txt: Fix kmctr instruction type.
679
5b64d091
L		 6802016-09-07 H.J. Lu <hongjiu.lu@intel.com>
681
682 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
683 * i386-init.h: Regenerated.
684
7763838e
CM		 6852016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
686
687 * opcodes/arc-dis.c (print_insn_arc): Changed.
688
1b8b6532
JM		 6892016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
690
691 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
692 camellia_fl.
693
1a336194
TP		 6942016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
695
696 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
697 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
698 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
699
6b40c462
L		 7002016-08-24 H.J. Lu <hongjiu.lu@intel.com>
701
702 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
703 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
704 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
705 PREFIX_MOD_3_0FAE_REG_4.
706 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
707 PREFIX_MOD_3_0FAE_REG_4.
708 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
709 (cpu_flags): Add CpuPTWRITE.
710 * i386-opc.h (CpuPTWRITE): New.
711 (i386_cpu_flags): Add cpuptwrite.
712 * i386-opc.tbl: Add ptwrite instruction.
713 * i386-init.h: Regenerated.
714 * i386-tbl.h: Likewise.
715
ab548d2d
AK		 7162016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
717
718 * arc-dis.h: Wrap around in extern "C".
719
344bde0a
RS		 7202016-08-23 Richard Sandiford <richard.sandiford@arm.com>
721
722 * aarch64-tbl.h (V8_2_INSN): New macro.
723 (aarch64_opcode_table): Use it.
724
5ce912d8
RS		 7252016-08-23 Richard Sandiford <richard.sandiford@arm.com>
726
727 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
728 CORE_INSN, __FP_INSN and SIMD_INSN.
729
9d30b0bd
RS		 7302016-08-23 Richard Sandiford <richard.sandiford@arm.com>
731
732 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
733 (aarch64_opcode_table): Update uses accordingly.
734
dfdaec14
AJ		 7352016-07-25 Andrew Jenner <andrew@codesourcery.com>
736 Kwok Cheung Yeung <kcy@codesourcery.com>
737
738 opcodes/
739 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
740 'e_cmplwi' to 'e_cmpli' instead.
741 (OPVUPRT, OPVUPRT_MASK): Define.
742 (powerpc_opcodes): Add E200Z4 insns.
743 (vle_opcodes): Add context save/restore insns.
744
7bd374a4
MR		 7452016-07-27 Maciej W. Rozycki <macro@imgtec.com>
746
747 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
748 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
749 "j".
750
db18dbab
GM		 7512016-07-27 Graham Markall <graham.markall@embecosm.com>
752
753 * arc-nps400-tbl.h: Change block comments to GNU format.
754 * arc-dis.c: Add new globals addrtypenames,
755 addrtypenames_max, and addtypeunknown.
756 (get_addrtype): New function.
757 (print_insn_arc): Print colons and address types when
758 required.
759 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
760 define insert and extract functions for all address types.
761 (arc_operands): Add operands for colon and all address
762 types.
763 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
764 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
765 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
766 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
767 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
768 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
769
fecd57f9
L		 7702016-07-21 H.J. Lu <hongjiu.lu@intel.com>
771
772 * configure: Regenerated.
773
37fd5ef3
CZ		 7742016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
775
776 * arc-dis.c (skipclass): New structure.
777 (decodelist): New variable.
778 (is_compatible_p): New function.
779 (new_element): Likewise.
780 (skip_class_p): Likewise.
781 (find_format_from_table): Use skip_class_p function.
782 (find_format): Decode first the extension instructions.
783 (print_insn_arc): Select either ARCEM or ARCHS based on elf
784 e_flags.
785 (parse_option): New function.
786 (parse_disassembler_options): Likewise.
787 (print_arc_disassembler_options): Likewise.
788 (print_insn_arc): Use parse_disassembler_options function. Proper
789 select ARCv2 cpu variant.
790 * disassemble.c (disassembler_usage): Add ARC disassembler
791 options.
792
92281a5b
MR		 7932016-07-13 Maciej W. Rozycki <macro@imgtec.com>
794
795 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
796 annotation from the "nal" entry and reorder it beyond "bltzal".
797
6e7ced37
JM		 7982016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
799
800 * sparc-opc.c (ldtxa): New macro.
801 (sparc_opcodes): Use the macro defined above to add entries for
802 the LDTXA instructions.
803 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
804 instruction.
805
2f831b9a 8062016-07-07 James Bowman <james.bowman@ftdichip.com>
807
808 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
809 and "jmpc".
810
c07315e0
JB		 8112016-07-01 Jan Beulich <jbeulich@suse.com>
812
813 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
814 (movzb): Adjust to cover all permitted suffixes.
815 (movzw): New.
816 * i386-tbl.h: Re-generate.
817
9243100a
JB		 8182016-07-01 Jan Beulich <jbeulich@suse.com>
819
820 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
821 (lgdt): Remove Tbyte from non-64-bit variant.
822 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
823 xsaves64, xsavec64): Remove Disp16.
824 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
825 Remove Disp32S from non-64-bit variants. Remove Disp16 from
826 64-bit variants.
827 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
828 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
829 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
830 64-bit variants.
831 * i386-tbl.h: Re-generate.
832
8325cc63
JB		 8332016-07-01 Jan Beulich <jbeulich@suse.com>
834
835 * i386-opc.tbl (xlat): Remove RepPrefixOk.
836 * i386-tbl.h: Re-generate.
837
838441e4
YQ		 8382016-06-30 Yao Qi <yao.qi@linaro.org>
839
840 * arm-dis.c (print_insn): Fix typo in comment.
841
dab26bf4
RS		 8422016-06-28 Richard Sandiford <richard.sandiford@arm.com>
843
844 * aarch64-opc.c (operand_general_constraint_met_p): Check the
845 range of ldst_elemlist operands.
846 (print_register_list): Use PRIi64 to print the index.
847 (aarch64_print_operand): Likewise.
848
5703197e
TS		 8492016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
850
851 * mcore-opc.h: Remove sentinal.
852 * mcore-dis.c (print_insn_mcore): Adjust.
853
ce440d63
GM		 8542016-06-23 Graham Markall <graham.markall@embecosm.com>
855
856 * arc-opc.c: Correct description of availability of NPS400
857 features.
858
6fd3a02d
PB		 8592016-06-22 Peter Bergner <bergner@vnet.ibm.com>
860
861 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
862 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
863 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
864 xor3>: New mnemonics.
865 <setb>: Change to a VX form instruction.
866 (insert_sh6): Add support for rldixor.
867 (extract_sh6): Likewise.
868
6b477896
TS		 8692016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
870
871 * arc-ext.h: Wrap in extern C.
872
bdd582db
GM		 8732016-06-21 Graham Markall <graham.markall@embecosm.com>
874
875 * arc-dis.c (arc_insn_length): Add comment on instruction length.
876 Use same method for determining instruction length on ARC700 and
877 NPS-400.
878 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
879 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
880 with the NPS400 subclass.
881 * arc-opc.c: Likewise.
882
96074adc
JM		 8832016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
884
885 * sparc-opc.c (rdasr): New macro.
886 (wrasr): Likewise.
887 (rdpr): Likewise.
888 (wrpr): Likewise.
889 (rdhpr): Likewise.
890 (wrhpr): Likewise.
891 (sparc_opcodes): Use the macros above to fix and expand the
892 definition of read/write instructions from/to
893 asr/privileged/hyperprivileged instructions.
894 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
895 %hva_mask_nz. Prefer softint_set and softint_clear over
896 set_softint and clear_softint.
897 (print_insn_sparc): Support %ver in Rd.
898
7a10c22f
JM		 8992016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
900
901 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
902 architecture according to the hardware capabilities they require.
903
4f26fb3a
JM		 9042016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
905
906 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
907 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
908 bfd_mach_sparc_v9{c,d,e,v,m}.
909 * sparc-opc.c (MASK_V9C): Define.
910 (MASK_V9D): Likewise.
911 (MASK_V9E): Likewise.
912 (MASK_V9V): Likewise.
913 (MASK_V9M): Likewise.
914 (v6): Add MASK_V9{C,D,E,V,M}.
915 (v6notlet): Likewise.
916 (v7): Likewise.
917 (v8): Likewise.
918 (v9): Likewise.
919 (v9andleon): Likewise.
920 (v9a): Likewise.
921 (v9b): Likewise.
922 (v9c): Define.
923 (v9d): Likewise.
924 (v9e): Likewise.
925 (v9v): Likewise.
926 (v9m): Likewise.
927 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
928
3ee6e4fb
NC		 9292016-06-15 Nick Clifton <nickc@redhat.com>
930
931 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
932 constants to match expected behaviour.
933 (nds32_parse_opcode): Likewise. Also for whitespace.
934
02f3be19
AB		 9352016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
936
937 * arc-opc.c (extract_rhv1): Extract value from insn.
938
6f9f37ed 9392016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 940
941 * arc-nps400-tbl.h: Add ldbit instruction.
942 * arc-opc.c: Add flag classes required for ldbit.
943
6f9f37ed 9442016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 945
946 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
947 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
948 support the above instructions.
949
6f9f37ed 9502016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 951
952 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
953 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
954 csma, cbba, zncv, and hofs.
955 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
956 support the above instructions.
957
9582016-06-06 Graham Markall <graham.markall@embecosm.com>
959
960 * arc-nps400-tbl.h: Add andab and orab instructions.
961
9622016-06-06 Graham Markall <graham.markall@embecosm.com>
963
964 * arc-nps400-tbl.h: Add addl-like instructions.
965
9662016-06-06 Graham Markall <graham.markall@embecosm.com>
967
968 * arc-nps400-tbl.h: Add mxb and imxb instructions.
969
9702016-06-06 Graham Markall <graham.markall@embecosm.com>
971
972 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
973 instructions.
974
b2cc3f6f
AK		 9752016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
976
977 * s390-dis.c (option_use_insn_len_bits_p): New file scope
978 variable.
979 (init_disasm): Handle new command line option "insnlength".
980 (print_s390_disassembler_options): Mention new option in help
981 output.
982 (print_insn_s390): Use the encoded insn length when dumping
983 unknown instructions.
984
1857fe72
DC		 9852016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
986
987 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
988 to the address and set as symbol address for LDS/ STS immediate operands.
989
14b57c7c
AM		 9902016-06-07 Alan Modra <amodra@gmail.com>
991
992 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
993 cpu for "vle" to e500.
994 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
995 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
996 (PPCNONE): Delete, substitute throughout.
997 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
998 except for major opcode 4 and 31.
999 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1000
4d1464f2
MW		 10012016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1002
1003 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1004 ARM_EXT_RAS in relevant entries.
1005
026122a6
PB		 10062016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1007
1008 PR binutils/20196
1009 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1010 opcodes for E6500.
1011
07f5af7d
L		 10122016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1013
1014 PR binutis/18386
1015 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1016 (indir_v_mode): New.
1017 Add comments for '&'.
1018 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1019 (putop): Handle '&'.
1020 (intel_operand_size): Handle indir_v_mode.
1021 (OP_E_register): Likewise.
1022 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1023 64-bit indirect call/jmp for AMD64.
1024 * i386-tbl.h: Regenerated
1025
4eb6f892
AB		 10262016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1027
1028 * arc-dis.c (struct arc_operand_iterator): New structure.
1029 (find_format_from_table): All the old content from find_format,
1030 with some minor adjustments, and parameter renaming.
1031 (find_format_long_instructions): New function.
1032 (find_format): Rewritten.
1033 (arc_insn_length): Add LSB parameter.
1034 (extract_operand_value): New function.
1035 (operand_iterator_next): New function.
1036 (print_insn_arc): Use new functions to find opcode, and iterator
1037 over operands.
1038 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1039 (extract_nps_3bit_dst_short): New function.
1040 (insert_nps_3bit_src2_short): New function.
1041 (extract_nps_3bit_src2_short): New function.
1042 (insert_nps_bitop1_size): New function.
1043 (extract_nps_bitop1_size): New function.
1044 (insert_nps_bitop2_size): New function.
1045 (extract_nps_bitop2_size): New function.
1046 (insert_nps_bitop_mod4_msb): New function.
1047 (extract_nps_bitop_mod4_msb): New function.
1048 (insert_nps_bitop_mod4_lsb): New function.
1049 (extract_nps_bitop_mod4_lsb): New function.
1050 (insert_nps_bitop_dst_pos3_pos4): New function.
1051 (extract_nps_bitop_dst_pos3_pos4): New function.
1052 (insert_nps_bitop_ins_ext): New function.
1053 (extract_nps_bitop_ins_ext): New function.
1054 (arc_operands): Add new operands.
1055 (arc_long_opcodes): New global array.
1056 (arc_num_long_opcodes): New global.
1057 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1058
1fe0971e
TS		 10592016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1060
1061 * nds32-asm.h: Add extern "C".
1062 * sh-opc.h: Likewise.
1063
315f180f
GM		 10642016-06-01 Graham Markall <graham.markall@embecosm.com>
1065
1066 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1067 0,b,limm to the rflt instruction.
1068
a2b5fccc
TS		 10692016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1070
1071 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1072 constant.
1073
0cbd0046
L		 10742016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1075
1076 PR gas/20145
1077 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1078 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1079 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1080 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1081 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1082 * i386-init.h: Regenerated.
1083
1848e567
L		 10842016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1085
1086 PR gas/20145
1087 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1088 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1089 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1090 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1091 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1092 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1093 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1094 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1095 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1096 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1097 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1098 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1099 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1100 CpuRegMask for AVX512.
1101 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1102 and CpuRegMask.
1103 (set_bitfield_from_cpu_flag_init): New function.
1104 (set_bitfield): Remove const on f. Call
1105 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1106 * i386-opc.h (CpuRegMMX): New.
1107 (CpuRegXMM): Likewise.
1108 (CpuRegYMM): Likewise.
1109 (CpuRegZMM): Likewise.
1110 (CpuRegMask): Likewise.
1111 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1112 and cpuregmask.
1113 * i386-init.h: Regenerated.
1114 * i386-tbl.h: Likewise.
1115
e92bae62
L		 11162016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1117
1118 PR gas/20154
1119 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1120 (opcode_modifiers): Add AMD64 and Intel64.
1121 (main): Properly verify CpuMax.
1122 * i386-opc.h (CpuAMD64): Removed.
1123 (CpuIntel64): Likewise.
1124 (CpuMax): Set to CpuNo64.
1125 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1126 (AMD64): New.
1127 (Intel64): Likewise.
1128 (i386_opcode_modifier): Add amd64 and intel64.
1129 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1130 on call and jmp.
1131 * i386-init.h: Regenerated.
1132 * i386-tbl.h: Likewise.
1133
e89c5eaa
L		 11342016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1135
1136 PR gas/20154
1137 * i386-gen.c (main): Fail if CpuMax is incorrect.
1138 * i386-opc.h (CpuMax): Set to CpuIntel64.
1139 * i386-tbl.h: Regenerated.
1140
77d66e7b
NC		 11412016-05-27 Nick Clifton <nickc@redhat.com>
1142
1143 PR target/20150
1144 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1145 (msp430dis_opcode_unsigned): New function.
1146 (msp430dis_opcode_signed): New function.
1147 (msp430_singleoperand): Use the new opcode reading functions.
1148 Only disassenmble bytes if they were successfully read.
1149 (msp430_doubleoperand): Likewise.
1150 (msp430_branchinstr): Likewise.
1151 (msp430x_callx_instr): Likewise.
1152 (print_insn_msp430): Check that it is safe to read bytes before
1153 attempting disassembly. Use the new opcode reading functions.
1154
19dfcc89
PB		 11552016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1156
1157 * ppc-opc.c (CY): New define. Document it.
1158 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1159
f3ad7637
L		 11602016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1161
1162 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1163 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1164 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1165 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1166 CPU_ANY_AVX_FLAGS.
1167 * i386-init.h: Regenerated.
1168
f1360d58
L		 11692016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1170
1171 PR gas/20141
1172 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1173 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1174 * i386-init.h: Regenerated.
1175
293f5f65
L		 11762016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1177
1178 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1179 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1180 * i386-init.h: Regenerated.
1181
d9eca1df
CZ		 11822016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1183
1184 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1185 information.
1186 (print_insn_arc): Set insn_type information.
1187 * arc-opc.c (C_CC): Add F_CLASS_COND.
1188 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1189 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1190 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1191 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1192 (brne, brne_s, jeq_s, jne_s): Likewise.
1193
87789e08
CZ		 11942016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1195
1196 * arc-tbl.h (neg): New instruction variant.
1197
c810e0b8
CZ		 11982016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1199
1200 * arc-dis.c (find_format, find_format, get_auxreg)
1201 (print_insn_arc): Changed.
1202 * arc-ext.h (INSERT_XOP): Likewise.
1203
3d207518
TS		 12042016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1205
1206 * tic54x-dis.c (sprint_mmr): Adjust.
1207 * tic54x-opc.c: Likewise.
1208
514e58b7
AM		 12092016-05-19 Alan Modra <amodra@gmail.com>
1210
1211 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1212
e43de63c
AM		 12132016-05-19 Alan Modra <amodra@gmail.com>
1214
1215 * ppc-opc.c: Formatting.
1216 (NSISIGNOPT): Define.
1217 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1218
1401d2fe
MR		 12192016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1220
1221 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1222 replacing references to `micromips_ase' throughout.
1223 (_print_insn_mips): Don't use file-level microMIPS annotation to
1224 determine the disassembly mode with the symbol table.
1225
1178da44
PB		 12262016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1227
1228 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1229
8f4f9071
MF		 12302016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1231
1232 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1233 mips64r6.
1234 * mips-opc.c (D34): New macro.
1235 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1236
8bc52696
AF		 12372016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1238
1239 * i386-dis.c (prefix_table): Add RDPID instruction.
1240 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1241 (cpu_flags): Add RDPID bitfield.
1242 * i386-opc.h (enum): Add RDPID element.
1243 (i386_cpu_flags): Add RDPID field.
1244 * i386-opc.tbl: Add RDPID instruction.
1245 * i386-init.h: Regenerate.
1246 * i386-tbl.h: Regenerate.
1247
39d911fc
TP		 12482016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1249
1250 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1251 branch type of a symbol.
1252 (print_insn): Likewise.
1253
16a1fa25
TP		 12542016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1255
1256 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1257 Mainline Security Extensions instructions.
1258 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1259 Extensions instructions.
1260 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1261 instructions.
1262 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1263 special registers.
1264
d751b79e
JM		 12652016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1266
1267 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1268
945e0f82
CZ		 12692016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1270
1271 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1272 (arcExtMap_genOpcode): Likewise.
1273 * arc-opc.c (arg_32bit_rc): Define new variable.
1274 (arg_32bit_u6): Likewise.
1275 (arg_32bit_limm): Likewise.
1276
20f55f38
SN		 12772016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1278
1279 * aarch64-gen.c (VERIFIER): Define.
1280 * aarch64-opc.c (VERIFIER): Define.
1281 (verify_ldpsw): Use static linkage.
1282 * aarch64-opc.h (verify_ldpsw): Remove.
1283 * aarch64-tbl.h: Use VERIFIER for verifiers.
1284
4bd13cde
NC		 12852016-04-28 Nick Clifton <nickc@redhat.com>
1286
1287 PR target/19722
1288 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1289 * aarch64-opc.c (verify_ldpsw): New function.
1290 * aarch64-opc.h (verify_ldpsw): New prototype.
1291 * aarch64-tbl.h: Add initialiser for verifier field.
1292 (LDPSW): Set verifier to verify_ldpsw.
1293
c0f92bf9
L		 12942016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1295
1296 PR binutils/19983
1297 PR binutils/19984
1298 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1299 smaller than address size.
1300
e6c7cdec
TS		 13012016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1302
1303 * alpha-dis.c: Regenerate.
1304 * crx-dis.c: Likewise.
1305 * disassemble.c: Likewise.
1306 * epiphany-opc.c: Likewise.
1307 * fr30-opc.c: Likewise.
1308 * frv-opc.c: Likewise.
1309 * ip2k-opc.c: Likewise.
1310 * iq2000-opc.c: Likewise.
1311 * lm32-opc.c: Likewise.
1312 * lm32-opinst.c: Likewise.
1313 * m32c-opc.c: Likewise.
1314 * m32r-opc.c: Likewise.
1315 * m32r-opinst.c: Likewise.
1316 * mep-opc.c: Likewise.
1317 * mt-opc.c: Likewise.
1318 * or1k-opc.c: Likewise.
1319 * or1k-opinst.c: Likewise.
1320 * tic80-opc.c: Likewise.
1321 * xc16x-opc.c: Likewise.
1322 * xstormy16-opc.c: Likewise.
1323
537aefaf
AB		 13242016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1325
1326 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1327 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1328 calcsd, and calcxd instructions.
1329 * arc-opc.c (insert_nps_bitop_size): Delete.
1330 (extract_nps_bitop_size): Delete.
1331 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1332 (extract_nps_qcmp_m3): Define.
1333 (extract_nps_qcmp_m2): Define.
1334 (extract_nps_qcmp_m1): Define.
1335 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1336 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1337 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1338 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1339 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1340 NPS_QCMP_M3.
1341
c8f785f2
AB		 13422016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1343
1344 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1345
6fd8e7c2
L		 13462016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1347
1348 * Makefile.in: Regenerated with automake 1.11.6.
1349 * aclocal.m4: Likewise.
1350
4b0c052e
AB		 13512016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1352
1353 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1354 instructions.
1355 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1356 (extract_nps_cmem_uimm16): New function.
1357 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1358
cb040366
AB		 13592016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1360
1361 * arc-dis.c (arc_insn_length): New function.
1362 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1363 (find_format): Change insnLen parameter to unsigned.
1364
accc0180
NC		 13652016-04-13 Nick Clifton <nickc@redhat.com>
1366
1367 PR target/19937
1368 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1369 the LD.B and LD.BU instructions.
1370
f36e33da
CZ		 13712016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1372
1373 * arc-dis.c (find_format): Check for extension flags.
1374 (print_flags): New function.
1375 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1376 .extAuxRegister.
1377 * arc-ext.c (arcExtMap_coreRegName): Use
1378 LAST_EXTENSION_CORE_REGISTER.
1379 (arcExtMap_coreReadWrite): Likewise.
1380 (dump_ARC_extmap): Update printing.
1381 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1382 (arc_aux_regs): Add cpu field.
1383 * arc-regs.h: Add cpu field, lower case name aux registers.
1384
1c2e355e
CZ		 13852016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1386
1387 * arc-tbl.h: Add rtsc, sleep with no arguments.
1388
b99747ae
CZ		 13892016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1390
1391 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1392 Initialize.
1393 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1394 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1395 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1396 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1397 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1398 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1399 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1400 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1401 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1402 (arc_opcode arc_opcodes): Null terminate the array.
1403 (arc_num_opcodes): Remove.
1404 * arc-ext.h (INSERT_XOP): Define.
1405 (extInstruction_t): Likewise.
1406 (arcExtMap_instName): Delete.
1407 (arcExtMap_insn): New function.
1408 (arcExtMap_genOpcode): Likewise.
1409 * arc-ext.c (ExtInstruction): Remove.
1410 (create_map): Zero initialize instruction fields.
1411 (arcExtMap_instName): Remove.
1412 (arcExtMap_insn): New function.
1413 (dump_ARC_extmap): More info while debuging.
1414 (arcExtMap_genOpcode): New function.
1415 * arc-dis.c (find_format): New function.
1416 (print_insn_arc): Use find_format.
1417 (arc_get_disassembler): Enable dump_ARC_extmap only when
1418 debugging.
1419
92708cec
MR		 14202016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1421
1422 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1423 instruction bits out.
1424
a42a4f84
AB		 14252016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1426
1427 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1428 * arc-opc.c (arc_flag_operands): Add new flags.
1429 (arc_flag_classes): Add new classes.
1430
1328504b
AB		 14312016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1432
1433 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1434
820f03ff
AB		 14352016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1436
1437 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1438 encode1, rflt, crc16, and crc32 instructions.
1439 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1440 (arc_flag_classes): Add C_NPS_R.
1441 (insert_nps_bitop_size_2b): New function.
1442 (extract_nps_bitop_size_2b): Likewise.
1443 (insert_nps_bitop_uimm8): Likewise.
1444 (extract_nps_bitop_uimm8): Likewise.
1445 (arc_operands): Add new operand entries.
1446
8ddf6b2a
CZ		 14472016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1448
b99747ae
CZ		 1449 * arc-regs.h: Add a new subclass field. Add double assist
1450 accumulator register values.
1451 * arc-tbl.h: Use DPA subclass to mark the double assist
1452 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1453 * arc-opc.c (RSP): Define instead of SP.
1454 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1455
589a7d88
JW		 14562016-04-05 Jiong Wang <jiong.wang@arm.com>
1457
1458 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1459
0a191de9 14602016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1461
1462 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1463 NPS_R_SRC1.
1464
0a106562
AB		 14652016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1466
1467 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1468 issues. No functional changes.
1469
bd05ac5f
CZ		 14702016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1471
b99747ae
CZ		 1472 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1473 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1474 (RTT): Remove duplicate.
1475 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1476 (PCT_CONFIG*): Remove.
1477 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1478
9885948f
CZ		 14792016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1480
b99747ae 1481 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1482
f2dd8838
CZ		 14832016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1484
b99747ae
CZ		 1485 * arc-tbl.h (invld07): Remove.
1486 * arc-ext-tbl.h: New file.
1487 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1488 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1489
0d2f91fe
JK		 14902016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1491
1492 Fix -Wstack-usage warnings.
1493 * aarch64-dis.c (print_operands): Substitute size.
1494 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1495
a6b71f42
JM		 14962016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1497
1498 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1499 to get a proper diagnostic when an invalid ASR register is used.
1500
9780e045
NC		 15012016-03-22 Nick Clifton <nickc@redhat.com>
1502
1503 * configure: Regenerate.
1504
e23e8ebe
AB		 15052016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1506
1507 * arc-nps400-tbl.h: New file.
1508 * arc-opc.c: Add top level comment.
1509 (insert_nps_3bit_dst): New function.
1510 (extract_nps_3bit_dst): New function.
1511 (insert_nps_3bit_src2): New function.
1512 (extract_nps_3bit_src2): New function.
1513 (insert_nps_bitop_size): New function.
1514 (extract_nps_bitop_size): New function.
1515 (arc_flag_operands): Add nps400 entries.
1516 (arc_flag_classes): Add nps400 entries.
1517 (arc_operands): Add nps400 entries.
1518 (arc_opcodes): Add nps400 include.
1519
1ae8ab47
AB		 15202016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1521
1522 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1523 the new class enum values.
1524
8699fc3e
AB		 15252016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1526
1527 * arc-dis.c (print_insn_arc): Handle nps400.
1528
24740d83
AB		 15292016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1530
1531 * arc-opc.c (BASE): Delete.
1532
8678914f
NC		 15332016-03-18 Nick Clifton <nickc@redhat.com>
1534
1535 PR target/19721
1536 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1537 of MOV insn that aliases an ORR insn.
1538
cc933301
JW		 15392016-03-16 Jiong Wang <jiong.wang@arm.com>
1540
1541 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1542
f86f5863
TS		 15432016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1544
1545 * mcore-opc.h: Add const qualifiers.
1546 * microblaze-opc.h (struct op_code_struct): Likewise.
1547 * sh-opc.h: Likewise.
1548 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1549 (tic4x_print_op): Likewise.
1550
62de1c63
AM		 15512016-03-02 Alan Modra <amodra@gmail.com>
1552
d11698cd 1553 * or1k-desc.h: Regenerate.
62de1c63 1554 * fr30-ibld.c: Regenerate.
c697cf0b 1555 * rl78-decode.c: Regenerate.
62de1c63 1556
020efce5
NC		 15572016-03-01 Nick Clifton <nickc@redhat.com>
1558
1559 PR target/19747
1560 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1561
b0c11777
RL		 15622016-02-24 Renlin Li <renlin.li@arm.com>
1563
1564 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1565 (print_insn_coprocessor): Support fp16 instructions.
1566
3e309328
RL		 15672016-02-24 Renlin Li <renlin.li@arm.com>
1568
1569 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1570 vminnm, vrint(mpna).
1571
8afc7bea
RL		 15722016-02-24 Renlin Li <renlin.li@arm.com>
1573
1574 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1575 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1576
4fd7268a
L		 15772016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1578
1579 * i386-dis.c (print_insn): Parenthesize expression to prevent
1580 truncated addresses.
1581 (OP_J): Likewise.
1582
4670103e
CZ		 15832016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1584 Janek van Oirschot <jvanoirs@synopsys.com>
1585
b99747ae
CZ		 1586 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1587 variable.
4670103e 1588
c1d9289f
NC		 15892016-02-04 Nick Clifton <nickc@redhat.com>
1590
1591 PR target/19561
1592 * msp430-dis.c (print_insn_msp430): Add a special case for
1593 decoding an RRC instruction with the ZC bit set in the extension
1594 word.
1595
a143b004
AB		 15962016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1597
1598 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1599 * epiphany-ibld.c: Regenerate.
1600 * fr30-ibld.c: Regenerate.
1601 * frv-ibld.c: Regenerate.
1602 * ip2k-ibld.c: Regenerate.
1603 * iq2000-ibld.c: Regenerate.
1604 * lm32-ibld.c: Regenerate.
1605 * m32c-ibld.c: Regenerate.
1606 * m32r-ibld.c: Regenerate.
1607 * mep-ibld.c: Regenerate.
1608 * mt-ibld.c: Regenerate.
1609 * or1k-ibld.c: Regenerate.
1610 * xc16x-ibld.c: Regenerate.
1611 * xstormy16-ibld.c: Regenerate.
1612
b89807c6
AB		 16132016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1614
1615 * epiphany-dis.c: Regenerated from latest cpu files.
1616
d8c823c8
MM		 16172016-02-01 Michael McConville <mmcco@mykolab.com>
1618
1619 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1620 test bit.
1621
5bc5ae88
RL		 16222016-01-25 Renlin Li <renlin.li@arm.com>
1623
1624 * arm-dis.c (mapping_symbol_for_insn): New function.
1625 (find_ifthen_state): Call mapping_symbol_for_insn().
1626
0bff6e2d
MW		 16272016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1628
1629 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1630 of MSR UAO immediate operand.
1631
100b4f2e
MR		 16322016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1633
1634 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1635 instruction support.
1636
5c14705f
AM		 16372016-01-17 Alan Modra <amodra@gmail.com>
1638
1639 * configure: Regenerate.
1640
4d82fe66
NC		 16412016-01-14 Nick Clifton <nickc@redhat.com>
1642
1643 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1644 instructions that can support stack pointer operations.
1645 * rl78-decode.c: Regenerate.
1646 * rl78-dis.c: Fix display of stack pointer in MOVW based
1647 instructions.
1648
651657fa
MW		 16492016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1650
1651 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1652 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1653 erxtatus_el1 and erxaddr_el1.
1654
105bde57
MW		 16552016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1656
1657 * arm-dis.c (arm_opcodes): Add "esb".
1658 (thumb_opcodes): Likewise.
1659
afa8d405
PB		 16602016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1661
1662 * ppc-opc.c <xscmpnedp>: Delete.
1663 <xvcmpnedp>: Likewise.
1664 <xvcmpnedp.>: Likewise.
1665 <xvcmpnesp>: Likewise.
1666 <xvcmpnesp.>: Likewise.
1667
83c3256e
AS		 16682016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1669
1670 PR gas/13050
1671 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1672 addition to ISA_A.
1673
6f2750fe
AM		 16742016-01-01 Alan Modra <amodra@gmail.com>
1675
1676 Update year range in copyright notice of all files.
1677
3499769a
AM		 1678For older changes see ChangeLog-2015
1679\f
1680Copyright (C) 2016 Free Software Foundation, Inc.
1681
1682Copying and distribution of this file, with or without modification,
1683are permitted in any medium without royalty provided the copyright
1684notice and this notice are preserved.
1685
1686Local Variables:
1687mode: change-log
1688left-margin: 8
1689fill-column: 74
1690version-control: never
1691End:
GDB Binutils - Deliverables
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