[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2008-04-10  Andreas Krebbel  <krebbel1@de.ibm.com>

	* s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
	of local variables used for mnemonic parsing: prefix, suffix and
	number.

2008-04-10  Andreas Krebbel  <krebbel1@de.ibm.com>

	* s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
	extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
	(s390_crb_extensions): New extensions table.
	(insertExpandedMnemonic): Handle '$' tag.
	* s390-opc.txt: Remove conditional jump variants which can now
	be expanded automatically.
	Replace '*' tag with '$' in the compare and branch instructions.

2008-04-07  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_VEX_38XX): Add a tab.
	(PREFIX_VEX_3AXX): Likewis.

2008-04-07  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove 4 extra blank lines.

2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	* i386-opc.tbl: Likewise.

	* i386-opc.h (CpuCLMUL): Renamed to ...
	(CpuPCLMUL): This.
	(CpuFMA): Updated.
	(i386_cpu_flags): Replace cpuclmul with cpupclmul.

	* i386-init.h: Regenerated.

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_register): New.
	(OP_E_memory): Likewise.
	(OP_VEX): Likewise.
	(OP_EX_Vex): Likewise.
	(OP_EX_VexW): Likewise.
	(OP_XMM_Vex): Likewise.
	(OP_XMM_VexW): Likewise.
	(OP_REG_VexI4): Likewise.
	(PCLMUL_Fixup): Likewise.
	(VEXI4_Fixup): Likewise.
	(VZERO_Fixup): Likewise.
	(VCMP_Fixup): Likewise.
	(VPERMIL2_Fixup): Likewise.
	(rex_original): Likewise.
	(rex_ignored): Likewise.
	(Mxmm): Likewise.
	(XMM): Likewise.
	(EXxmm): Likewise.
	(EXxmmq): Likewise.
	(EXymmq): Likewise.
	(Vex): Likewise.
	(Vex128): Likewise.
	(Vex256): Likewise.
	(VexI4): Likewise.
	(EXdVex): Likewise.
	(EXqVex): Likewise.
	(EXVexW): Likewise.
	(EXdVexW): Likewise.
	(EXqVexW): Likewise.
	(XMVex): Likewise.
	(XMVexW): Likewise.
	(XMVexI4): Likewise.
	(PCLMUL): Likewise.
	(VZERO): Likewise.
	(VCMP): Likewise.
	(VPERMIL2): Likewise.
	(xmm_mode): Likewise.
	(xmmq_mode): Likewise.
	(ymmq_mode): Likewise.
	(vex_mode): Likewise.
	(vex128_mode): Likewise.
	(vex256_mode): Likewise.
	(USE_VEX_C4_TABLE): Likewise.
	(USE_VEX_C5_TABLE): Likewise.
	(USE_VEX_LEN_TABLE): Likewise.
	(VEX_C4_TABLE): Likewise.
	(VEX_C5_TABLE): Likewise.
	(VEX_LEN_TABLE): Likewise.
	(REG_VEX_XX): Likewise.
	(MOD_VEX_XXX): Likewise.
	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	(PREFIX_0F3A44): Likewise.
	(PREFIX_0F3ADF): Likewise.
	(PREFIX_VEX_XXX): Likewise.
	(VEX_OF): Likewise.
	(VEX_OF38): Likewise.
	(VEX_OF3A): Likewise.
	(VEX_LEN_XXX): Likewise.
	(vex): Likewise.
	(need_vex): Likewise.
	(need_vex_reg): Likewise.
	(vex_i4_done): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(OP_REG_VexI4): Likewise.
	(vex_cmp_op): Likewise.
	(pclmul_op): Likewise.
	(vpermil2_op): Likewise.
	(m_mode): Updated.
	(es_reg): Likewise.
	(PREFIX_0F38F0): Likewise.
	(PREFIX_0F3A60): Likewise.
	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
	and PREFIX_VEX_XXX entries.
	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
	PREFIX_0F3ADF.
	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
	Add MOD_VEX_XXX entries.
	(ckprefix): Initialize rex_original and rex_ignored.  Store the
	REX byte in rex_original.
	(get_valid_dis386): Handle the implicit prefix in VEX prefix
	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
	calling get_valid_dis386.  Use rex_original and rex_ignored when
	printing out REX.
	(putop): Handle "XY".
	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
	ymmq_mode.
	(OP_E_extended): Updated to use OP_E_register and
	OP_E_memory.
	(OP_XMM): Handle VEX.
	(OP_EX): Likewise.
	(XMM_Fixup): Likewise.
	(CMP_Fixup): Use ARRAY_SIZE.

	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
	(operand_type_init): Add OPERAND_TYPE_REGYMM and
	OPERAND_TYPE_VEX_IMM4.
	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
	VexImmExt and SSE2AVX.
	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.

	* i386-opc.h (CpuAVX): New.
	(CpuAES): Likewise.
	(CpuCLMUL): Likewise.
	(CpuFMA): Likewise.
	(Vex): Likewise.
	(Vex256): Likewise.
	(VexNDS): Likewise.
	(VexNDD): Likewise.
	(VexW0): Likewise.
	(VexW1): Likewise.
	(Vex0F): Likewise.
	(Vex0F38): Likewise.
	(Vex0F3A): Likewise.
	(Vex3Sources): Likewise.
	(VexImmExt): Likewise.
	(SSE2AVX): Likewise.
	(RegYMM): Likewise.
	(Ymmword): Likewise.
	(Vex_Imm4): Likewise.
	(Implicit1stXmm0): Likewise.
	(CpuXsave): Updated.
	(CpuLM): Likewise.
	(ByteOkIntel): Likewise.
	(OldGcc): Likewise.
	(Control): Likewise.
	(Unspecified): Likewise.
	(OTMax): Likewise.
	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
	vex3sources, veximmext and sse2avx.
	(i386_operand_type): Add regymm, ymmword and vex_imm4.

	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.

	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-03-26  Bernd Schmidt  <bernd.schmidt@analog.com>

	From  Robin Getz  <robin.getz@analog.com>
	* bfin-dis.c (bu32): Typedef.
	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	(constant_formats[]): Add uimm32 and huimm16.
	(fmtconst_val): New.
	(uimm32): Define.
	(huimm32): Define.
	(imm16_val): Define.
	(luimm16_val): Define.
	(struct saved_state): Define.
	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	(get_allreg): New.
	(decode_LDIMMhalf_0): Print out the whole register value.

	From Jie Zhang  <jie.zhang@analog.com>
	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	multiply and multiply-accumulate to data register instruction.

	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	c_imm32, c_huimm32e): Define.
	(constant_formats): Add flags for printing decimal, leading spaces, and
	exact symbols.
	(comment, parallel): Add global flags in all disassembly.
	(fmtconst): Take advantage of new flags, and print default in hex.
	(fmtconst_val): Likewise.
	(decode_macfunc): Be consistant with spaces, tabs, comments,
	capitalization in disassembly, fix minor coding style issues.
	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	_print_insn_bfin, print_insn_bfin): Likewise.

2008-03-17  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

	* aclocal.m4: Regenerate.
	* configure: Likewise.
	* Makefile.in: Likewise.

2008-03-13  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2008-03-07  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c (powerpc_opcodes): Order and format.

2008-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	* i386-tbl.h: Regenerated.

2008-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	x86-64.
	* i386-tbl.h: Regenerated.

2008-02-21  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	and Fword for far indirect jmp. Allow Reg16 and Word for near
	indirect jmp on x86-64. Disallow Fword for lcall.
	* i386-tbl.h: Re-generate.

2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>

	* cr16-opc.c  (cr16_num_optab): Defined

2008-02-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c  (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	* i386-init.h: Regenerated.

2008-02-14  Nick Clifton  <nickc@redhat.com>

	PR binutils/5524
	* configure.in (SHARED_LIBADD): Select the correct host specific
	file extension for shared libraries.
	* configure: Regenerate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.h (RegFlat): New.
	* i386-reg.tbl (flat): Add.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (a_mode): New.
	(cond_jump_mode): Adjust.
	(Ma): Change to a_mode.
	(intel_operand_size): Handle a_mode.
	* i386-opc.tbl: Allow Dword and Qword for bound.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-gen.c (process_i386_registers): Process new fields.
	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	unsigned char. Add dw2_regnum and Dw2Inval.
	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	register names.
	* i386-tbl.h: Re-generate.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
	* i386-init.h: Updated.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flags): Add CpuXsave.

	* i386-opc.h (CpuXsave): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpuxsave.

	* i386-dis.c (MOD_0FAE_REG_4): New.
	(RM_0F01_REG_2): Likewise.
	(MOD_0FAE_REG_5): Updated.
	(RM_0F01_REG_3): Likewise.
	(reg_table): Use MOD_0FAE_REG_4.
	(mod_table): Use RM_0F01_REG_2.  Add MOD_0FAE_REG_4.  Updated
	for xrstor.
	(rm_table): Add RM_0F01_REG_2.

	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-02-11  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	* i386-tbl.h: Re-generate.

2008-02-04  H.J. Lu  <hongjiu.lu@intel.com>

	PR 5715
	* configure: Regenerated.

2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>

	* mips-dis.c: Update copyright.
	(mips_arch_choices): Add Octeon.
	* mips-opc.c: Update copyright.
	(IOCT): New macro.
	(mips_builtin_opcodes): Add Octeon instruction synciobdma.

2008-01-29  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c: Support optional L form mtmsr.

2008-01-24  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_extended): Handle r12 like rsp.

2008-01-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	* i386-init.h: Regenerated.

2008-01-23  Tristan Gingold  <gingold@adacore.com>

	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuMMX2): Removed.
	(CpuSSE): Updated.

	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	CPU_SMX_FLAGS.
	* i386-init.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Use Qword on movddup.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (Mx): New.
	(PREFIX_0FC3): Likewise.
	(PREFIX_0FC7_REG_6): Updated.
	(dis386_twobyte): Use PREFIX_0FC3.
	(prefix_table): Add PREFIX_0FC3.  Use Mq on movntq and movntsd.
	Use Mx on movntps, movntpd, movntdq and movntdqa.  Use Md on
	movntss.

2008-01-14  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	(operand_types): Add Mem.

	* i386-opc.h (IntelSyntax): New.
	* i386-opc.h (Mem): New.
	(Byte): Updated.
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Add intelsyntax.
	(i386_operand_type): Add mem.

	* i386-opc.tbl: Remove Reg16 from movnti.  Add sizes to more
	instructions.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-13  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (Byte): Fix a typo.

2008-01-12  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (operand_type_init): Add Dword to
	OPERAND_TYPE_ACC32.  Add Qword to OPERAND_TYPE_ACC64.
	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	Qword and Xmmword.
	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	Xmmword, Unspecified and Anysize.
	(set_bitfield): Make Mmword an alias of Qword.  Make Oword
	an alias of Xmmword.

	* i386-opc.h (CheckSize): Removed.
	(Byte): Updated.
	(Word): Likewise.
	(Dword): Likewise.
	(Qword): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(OTMax): Likewise.
	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	qword and xmmword.
	(Fword): New.
	(TBYTE): Likewise.
	(Unspecified): Likewise.
	(Anysize): Likewise.
	(i386_operand_type): Add byte, word, dword, fword, qword,
	tbyte xmmword, unspecified and anysize.

	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	Tbyte, Xmmword, Unspecified and Anysize.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-10  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	(REG_0F18): Updated.
	(reg_table): Updated.
	(dis386_twobyte): Updated.  Use "nopQ" on 0x19 to 0x1e.
	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (set_bitfield): Use fail () on error.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (lineno): New.
	(filename): Likewise.
	(set_bitfield): Report filename and line numer on error.
	(process_i386_opcodes): Set filename and update lineno.
	(process_i386_registers): Likewise.

2008-01-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	ATTSyntax.

	* i386-opc.h (IntelMnemonic): Renamed to ..
	(ATTSyntax): This
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	and intelsyntax.

	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax 
	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	* i386-tbl.h: Regenerated.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c: Update copyright to 2008.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	* i386-tbl.h: Regenerated.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	CpuSSE4_2_Or_ABM.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	(CpuSSE4_2_Or_ABM): Likewise.
	(CpuLM): Updated.
	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.

	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
	and CpuPadLock, respectively.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove No_xSuf.

	* i386-opc.h (No_xSuf): Removed.
	(CheckSize): Updated.

	* i386-tbl.h: Regenerated.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	CPU_SSE5_FLAGS.
	(cpu_flags): Add CpuSSE4_2_Or_ABM.

	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpusse4_2_or_abm.

	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	CpuABM|CpuSSE4_2 on popcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h: Update comments.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	Byte, Word, Dword, QWord and Xmmword.

	* i386-opc.h (No_xSuf): New.
	(CheckSize): Likewise.
	(Byte): Likewise.
	(Word): Likewise.
	(Dword): Likewise.
	(QWord): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	Dword, QWord and Xmmword.

	* i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
	used.
	* i386-tbl.h: Regenerated.

2008-01-02  Mark Kettenis  <kettenis@gnu.org>

	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	From Miod Vallat.

For older changes see ChangeLog-2007
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
7ff42648 AK	1	2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
	2
	3	* s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
	4	of local variables used for mnemonic parsing: prefix, suffix and
	5	number.
	6
45a5551e AK	7	2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
	8
	9	* s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
	10	extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
	11	(s390_crb_extensions): New extensions table.
	12	(insertExpandedMnemonic): Handle '$' tag.
	13	* s390-opc.txt: Remove conditional jump variants which can now
	14	be expanded automatically.
	15	Replace '*' tag with '$' in the compare and branch instructions.
	16
06c8514a L	17	2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
	18
	19	* i386-dis.c (PREFIX_VEX_38XX): Add a tab.
	20	(PREFIX_VEX_3AXX): Likewis.
	21
b122c285 L	22	2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
	23
	24	* i386-opc.tbl: Remove 4 extra blank lines.
	25
594ab6a3 L	26	2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
	27
	28	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	29	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	30	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	31	* i386-opc.tbl: Likewise.
	32
	33	* i386-opc.h (CpuCLMUL): Renamed to ...
	34	(CpuPCLMUL): This.
	35	(CpuFMA): Updated.
	36	(i386_cpu_flags): Replace cpuclmul with cpupclmul.
	37
	38	* i386-init.h: Regenerated.
	39
c0f3af97 L	40	2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
	41
	42	* i386-dis.c (OP_E_register): New.
	43	(OP_E_memory): Likewise.
	44	(OP_VEX): Likewise.
	45	(OP_EX_Vex): Likewise.
	46	(OP_EX_VexW): Likewise.
	47	(OP_XMM_Vex): Likewise.
	48	(OP_XMM_VexW): Likewise.
	49	(OP_REG_VexI4): Likewise.
	50	(PCLMUL_Fixup): Likewise.
	51	(VEXI4_Fixup): Likewise.
	52	(VZERO_Fixup): Likewise.
	53	(VCMP_Fixup): Likewise.
	54	(VPERMIL2_Fixup): Likewise.
	55	(rex_original): Likewise.
	56	(rex_ignored): Likewise.
	57	(Mxmm): Likewise.
	58	(XMM): Likewise.
	59	(EXxmm): Likewise.
	60	(EXxmmq): Likewise.
	61	(EXymmq): Likewise.
	62	(Vex): Likewise.
	63	(Vex128): Likewise.
	64	(Vex256): Likewise.
	65	(VexI4): Likewise.
	66	(EXdVex): Likewise.
	67	(EXqVex): Likewise.
	68	(EXVexW): Likewise.
	69	(EXdVexW): Likewise.
	70	(EXqVexW): Likewise.
	71	(XMVex): Likewise.
	72	(XMVexW): Likewise.
	73	(XMVexI4): Likewise.
	74	(PCLMUL): Likewise.
	75	(VZERO): Likewise.
	76	(VCMP): Likewise.
	77	(VPERMIL2): Likewise.
	78	(xmm_mode): Likewise.
	79	(xmmq_mode): Likewise.
	80	(ymmq_mode): Likewise.
	81	(vex_mode): Likewise.
	82	(vex128_mode): Likewise.
	83	(vex256_mode): Likewise.
	84	(USE_VEX_C4_TABLE): Likewise.
	85	(USE_VEX_C5_TABLE): Likewise.
	86	(USE_VEX_LEN_TABLE): Likewise.
	87	(VEX_C4_TABLE): Likewise.
	88	(VEX_C5_TABLE): Likewise.
	89	(VEX_LEN_TABLE): Likewise.
	90	(REG_VEX_XX): Likewise.
	91	(MOD_VEX_XXX): Likewise.
	92	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	93	(PREFIX_0F3A44): Likewise.
	94	(PREFIX_0F3ADF): Likewise.
	95	(PREFIX_VEX_XXX): Likewise.
	96	(VEX_OF): Likewise.
	97	(VEX_OF38): Likewise.
	98	(VEX_OF3A): Likewise.
	99	(VEX_LEN_XXX): Likewise.
	100	(vex): Likewise.
	101	(need_vex): Likewise.
	102	(need_vex_reg): Likewise.
	103	(vex_i4_done): Likewise.
104	(vex_table): Likewise.
105	(vex_len_table): Likewise.
106	(OP_REG_VexI4): Likewise.
107	(vex_cmp_op): Likewise.
108	(pclmul_op): Likewise.
109	(vpermil2_op): Likewise.
110	(m_mode): Updated.
111	(es_reg): Likewise.
112	(PREFIX_0F38F0): Likewise.
113	(PREFIX_0F3A60): Likewise.
114	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
115	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
116	and PREFIX_VEX_XXX entries.
117	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
118	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
119	PREFIX_0F3ADF.
120	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
121	Add MOD_VEX_XXX entries.
122	(ckprefix): Initialize rex_original and rex_ignored. Store the
123	REX byte in rex_original.
124	(get_valid_dis386): Handle the implicit prefix in VEX prefix
125	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
126	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
127	calling get_valid_dis386. Use rex_original and rex_ignored when
128	printing out REX.
129	(putop): Handle "XY".
130	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
131	ymmq_mode.
132	(OP_E_extended): Updated to use OP_E_register and
133	OP_E_memory.
134	(OP_XMM): Handle VEX.
135	(OP_EX): Likewise.
136	(XMM_Fixup): Likewise.
137	(CMP_Fixup): Use ARRAY_SIZE.
138
139	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
140	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
141	(operand_type_init): Add OPERAND_TYPE_REGYMM and
142	OPERAND_TYPE_VEX_IMM4.
143	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
144	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
145	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
146	VexImmExt and SSE2AVX.
147	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
148
149	* i386-opc.h (CpuAVX): New.
150	(CpuAES): Likewise.
151	(CpuCLMUL): Likewise.
152	(CpuFMA): Likewise.
153	(Vex): Likewise.
154	(Vex256): Likewise.
155	(VexNDS): Likewise.
156	(VexNDD): Likewise.
157	(VexW0): Likewise.
158	(VexW1): Likewise.
159	(Vex0F): Likewise.
160	(Vex0F38): Likewise.
161	(Vex0F3A): Likewise.
162	(Vex3Sources): Likewise.
163	(VexImmExt): Likewise.
164	(SSE2AVX): Likewise.
165	(RegYMM): Likewise.
166	(Ymmword): Likewise.
167	(Vex_Imm4): Likewise.
168	(Implicit1stXmm0): Likewise.
169	(CpuXsave): Updated.
170	(CpuLM): Likewise.
171	(ByteOkIntel): Likewise.
172	(OldGcc): Likewise.
173	(Control): Likewise.
174	(Unspecified): Likewise.
175	(OTMax): Likewise.
176	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
177	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
178	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
179	vex3sources, veximmext and sse2avx.
180	(i386_operand_type): Add regymm, ymmword and vex_imm4.
181
182	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
183
184	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
185
186	* i386-init.h: Regenerated.
187	* i386-tbl.h: Likewise.
188
b21c9cb4 BS	189	2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
	190
	191	From Robin Getz <robin.getz@analog.com>
	192	* bfin-dis.c (bu32): Typedef.
	193	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	194	(constant_formats[]): Add uimm32 and huimm16.
	195	(fmtconst_val): New.
	196	(uimm32): Define.
	197	(huimm32): Define.
	198	(imm16_val): Define.
	199	(luimm16_val): Define.
	200	(struct saved_state): Define.
	201	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	202	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	203	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	204	(get_allreg): New.
	205	(decode_LDIMMhalf_0): Print out the whole register value.
	206
ee171c8f BS	207	From Jie Zhang <jie.zhang@analog.com>
	208	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	209	multiply and multiply-accumulate to data register instruction.
	210
086134ec BS	211	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	212	c_imm32, c_huimm32e): Define.
	213	(constant_formats): Add flags for printing decimal, leading spaces, and
	214	exact symbols.
	215	(comment, parallel): Add global flags in all disassembly.
	216	(fmtconst): Take advantage of new flags, and print default in hex.
	217	(fmtconst_val): Likewise.
	218	(decode_macfunc): Be consistant with spaces, tabs, comments,
	219	capitalization in disassembly, fix minor coding style issues.
	220	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	221	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	222	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	223	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	224	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	225	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	226	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	227	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	228	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	229	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	230	_print_insn_bfin, print_insn_bfin): Likewise.
	231
58c85be7 RW	232	2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
	233
	234	* aclocal.m4: Regenerate.
	235	* configure: Likewise.
	236	* Makefile.in: Likewise.
	237
50e7d84b AM	238	2008-03-13 Alan Modra <amodra@bigpond.net.au>
	239
	240	* Makefile.am: Run "make dep-am".
	241	* Makefile.in: Regenerate.
	242	* configure: Regenerate.
	243
de866fcc AM	244	2008-03-07 Alan Modra <amodra@bigpond.net.au>
	245
	246	* ppc-opc.c (powerpc_opcodes): Order and format.
	247
28dbc079 L	248	2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
	249
	250	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	251	* i386-tbl.h: Regenerated.
	252
849830bd L	253	2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
	254
	255	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	256	x86-64.
	257	* i386-tbl.h: Regenerated.
	258
743ddb6b JB	259	2008-02-21 Jan Beulich <jbeulich@novell.com>
	260
	261	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	262	and Fword for far indirect jmp. Allow Reg16 and Word for near
	263	indirect jmp on x86-64. Disallow Fword for lcall.
	264	* i386-tbl.h: Re-generate.
	265
796d5313 NC	266	2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
	267
	268	* cr16-opc.c (cr16_num_optab): Defined
	269
65da13b5 L	270	2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
	271
	272	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	273	* i386-init.h: Regenerated.
	274
0e336180 NC	275	2008-02-14 Nick Clifton <nickc@redhat.com>
	276
	277	PR binutils/5524
	278	* configure.in (SHARED_LIBADD): Select the correct host specific
	279	file extension for shared libraries.
	280	* configure: Regenerate.
	281
b7240065 JB	282	2008-02-13 Jan Beulich <jbeulich@novell.com>
	283
	284	* i386-opc.h (RegFlat): New.
	285	* i386-reg.tbl (flat): Add.
	286	* i386-tbl.h: Re-generate.
	287
34b772a6 JB	288	2008-02-13 Jan Beulich <jbeulich@novell.com>
	289
	290	* i386-dis.c (a_mode): New.
	291	(cond_jump_mode): Adjust.
	292	(Ma): Change to a_mode.
	293	(intel_operand_size): Handle a_mode.
	294	* i386-opc.tbl: Allow Dword and Qword for bound.
	295	* i386-tbl.h: Re-generate.
	296
a60de03c JB	297	2008-02-13 Jan Beulich <jbeulich@novell.com>
	298
	299	* i386-gen.c (process_i386_registers): Process new fields.
	300	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	301	unsigned char. Add dw2_regnum and Dw2Inval.
	302	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	303	register names.
	304	* i386-tbl.h: Re-generate.
	305
f03fe4c1 L	306	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
f03fe4c1 L	307
4b6bc8eb	308	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1 L	309	* i386-init.h: Updated.
f03fe4c1 L	310
475a2301 L	311	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
	312
	313	* i386-gen.c (cpu_flags): Add CpuXsave.
	314
	315	* i386-opc.h (CpuXsave): New.
4b6bc8eb	316	(CpuLM): Updated.
475a2301 L	317	(i386_cpu_flags): Add cpuxsave.
	318
	319	* i386-dis.c (MOD_0FAE_REG_4): New.
	320	(RM_0F01_REG_2): Likewise.
	321	(MOD_0FAE_REG_5): Updated.
	322	(RM_0F01_REG_3): Likewise.
	323	(reg_table): Use MOD_0FAE_REG_4.
	324	(mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
	325	for xrstor.
	326	(rm_table): Add RM_0F01_REG_2.
	327
	328	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	329	* i386-init.h: Regenerated.
	330	* i386-tbl.h: Likewise.
	331
595785c6	332	2008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc	333
595785c6 JB	334	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	335	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	336	* i386-tbl.h: Re-generate.
	337
bb8541b9 L	338	2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
	339
	340	PR 5715
	341	* configure: Regenerated.
	342
57b592a3 AN	343	2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
	344
	345	* mips-dis.c: Update copyright.
	346	(mips_arch_choices): Add Octeon.
	347	* mips-opc.c: Update copyright.
	348	(IOCT): New macro.
	349	(mips_builtin_opcodes): Add Octeon instruction synciobdma.
	350
930bb4cf AM	351	2008-01-29 Alan Modra <amodra@bigpond.net.au>
	352
	353	* ppc-opc.c: Support optional L form mtmsr.
	354
82c18208 L	355	2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
	356
	357	* i386-dis.c (OP_E_extended): Handle r12 like rsp.
	358
599121aa L	359	2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
	360
	361	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	362	* i386-init.h: Regenerated.
	363
80098f51 TG	364	2008-01-23 Tristan Gingold <gingold@adacore.com>
	365
	366	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	367	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
	368
115c7c25 L	369	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	370
	371	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	372	(cpu_flags): Likewise.
	373
	374	* i386-opc.h (CpuMMX2): Removed.
	375	(CpuSSE): Updated.
	376
	377	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE\|Cpu3dnowA.
	378	* i386-init.h: Regenerated.
	379	* i386-tbl.h: Likewise.
	380
6305a203 L	381	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	382
	383	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	384	CPU_SMX_FLAGS.
	385	* i386-init.h: Regenerated.
	386
fd07a1c8 L	387	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	388
	389	* i386-opc.tbl: Use Qword on movddup.
	390	* i386-tbl.h: Regenerated.
	391
321fd21e L	392	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	393
	394	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	395	* i386-tbl.h: Regenerated.
	396
4ee52178 L	397	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	398
	399	* i386-dis.c (Mx): New.
	400	(PREFIX_0FC3): Likewise.
	401	(PREFIX_0FC7_REG_6): Updated.
	402	(dis386_twobyte): Use PREFIX_0FC3.
	403	(prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
	404	Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
	405	movntss.
	406
5c07affc L	407	2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
	408
	409	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	410	(operand_types): Add Mem.
	411
	412	* i386-opc.h (IntelSyntax): New.
	413	* i386-opc.h (Mem): New.
	414	(Byte): Updated.
	415	(Opcode_Modifier_Max): Updated.
	416	(i386_opcode_modifier): Add intelsyntax.
	417	(i386_operand_type): Add mem.
	418
	419	* i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
	420	instructions.
	421
	422	* i386-reg.tbl: Add size for accumulator.
	423
	424	* i386-init.h: Regenerated.
	425	* i386-tbl.h: Likewise.
	426
0d6a2f58 L	427	2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
	428
	429	* i386-opc.h (Byte): Fix a typo.
	430
7d5e4556 L	431	2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
	432
	433	PR gas/5534
	434	* i386-gen.c (operand_type_init): Add Dword to
	435	OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
	436	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	437	Qword and Xmmword.
	438	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	439	Xmmword, Unspecified and Anysize.
	440	(set_bitfield): Make Mmword an alias of Qword. Make Oword
	441	an alias of Xmmword.
	442
	443	* i386-opc.h (CheckSize): Removed.
	444	(Byte): Updated.
	445	(Word): Likewise.
	446	(Dword): Likewise.
	447	(Qword): Likewise.
	448	(Xmmword): Likewise.
	449	(FWait): Updated.
	450	(OTMax): Likewise.
	451	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	452	qword and xmmword.
	453	(Fword): New.
	454	(TBYTE): Likewise.
	455	(Unspecified): Likewise.
	456	(Anysize): Likewise.
	457	(i386_operand_type): Add byte, word, dword, fword, qword,
	458	tbyte xmmword, unspecified and anysize.
	459
	460	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	461	Tbyte, Xmmword, Unspecified and Anysize.
	462
	463	* i386-reg.tbl: Add size for accumulator.
	464
	465	* i386-init.h: Regenerated.
	466	* i386-tbl.h: Likewise.
	467
b5b1fc4f L	468	2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
	469
	470	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	471	(REG_0F18): Updated.
	472	(reg_table): Updated.
	473	(dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
	474	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
	475
50e8458f L	476	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	477
	478	* i386-gen.c (set_bitfield): Use fail () on error.
	479
3d4d5afa L	480	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	481
	482	* i386-gen.c (lineno): New.
	483	(filename): Likewise.
	484	(set_bitfield): Report filename and line numer on error.
	485	(process_i386_opcodes): Set filename and update lineno.
	486	(process_i386_registers): Likewise.
	487
e1d4d893 L	488	2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
	489
	490	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	491	ATTSyntax.
	492
	493	* i386-opc.h (IntelMnemonic): Renamed to ..
	494	(ATTSyntax): This
	495	(Opcode_Modifier_Max): Updated.
	496	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	497	and intelsyntax.
	498
	499	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
	500	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	501	* i386-tbl.h: Regenerated.
	502
6f143e4d L	503	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	504
	505	* i386-gen.c: Update copyright to 2008.
	506	* i386-opc.h: Likewise.
	507	* i386-opc.tbl: Likewise.
	508
	509	* i386-init.h: Regenerated.
	510	* i386-tbl.h: Likewise.
	511
c6add537 L	512	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	513
	514	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	515	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	516	* i386-tbl.h: Regenerated.
	517
3629bb00 L	518	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	519
	520	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	521	CpuSSE4_2_Or_ABM.
	522	(cpu_flags): Likewise.
	523
	524	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	525	(CpuSSE4_2_Or_ABM): Likewise.
	526	(CpuLM): Updated.
	527	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
	528
	529	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	530	Cpu686\|CpuPadLock with CpuSSE4_1\|CpuSSE5, CpuABM\|CpuSSE4_2
	531	and CpuPadLock, respectively.
	532	* i386-init.h: Regenerated.
	533	* i386-tbl.h: Likewise.
	534
24995bd6 L	535	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	536
	537	* i386-gen.c (opcode_modifiers): Remove No_xSuf.
	538
	539	* i386-opc.h (No_xSuf): Removed.
	540	(CheckSize): Updated.
	541
	542	* i386-tbl.h: Regenerated.
	543
e0329a22 L	544	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	545
	546	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	547	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	548	CPU_SSE5_FLAGS.
	549	(cpu_flags): Add CpuSSE4_2_Or_ABM.
	550
	551	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	552	(CpuLM): Updated.
	553	(i386_cpu_flags): Add cpusse4_2_or_abm.
	554
	555	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	556	CpuABM\|CpuSSE4_2 on popcnt.
	557	* i386-init.h: Regenerated.
	558	* i386-tbl.h: Likewise.
	559
f2a9c676 L	560	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	561
	562	* i386-opc.h: Update comments.
	563
d978b5be L	564	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	565
	566	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	567	* i386-opc.h: Likewise.
	568	* i386-opc.tbl: Likewise.
	569
582d5edd L	570	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	571
	572	PR gas/5534
	573	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	574	Byte, Word, Dword, QWord and Xmmword.
	575
	576	* i386-opc.h (No_xSuf): New.
	577	(CheckSize): Likewise.
	578	(Byte): Likewise.
	579	(Word): Likewise.
	580	(Dword): Likewise.
	581	(QWord): Likewise.
	582	(Xmmword): Likewise.
	583	(FWait): Updated.
	584	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	585	Dword, QWord and Xmmword.
	586
	587	* i386-opc.tbl: Add CheckSize\|QWord to movq if IgnoreSize is
	588	used.
	589	* i386-tbl.h: Regenerated.
	590
3fe15143 MK	591	2008-01-02 Mark Kettenis <kettenis@gnu.org>
	592
	593	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	594	From Miod Vallat.
	595
6c7ac64e	596	For older changes see ChangeLog-2007
252b5132 RH	597	\f
252b5132 RH	598	Local Variables:
2f6d2f85 NC	599	mode: change-log
	600	left-margin: 8
	601	fill-column: 74
252b5132 RH	602	version-control: never
252b5132 RH	603	End: