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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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6a819047
RS		 12013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
4 for operands that are hard-coded to $0.
5 * micromips-opc.c (micromips_opcodes): Likewise.
6
344c74a6
RS		 72013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
8
9 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
10 for the single-operand forms of JALR and JALR.HB.
11 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
12 and JALRS.HB.
13
41989114
RS		 142013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
15
16 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
17 instructions. Fix them to use WR_MACC instead of WR_CC and
18 add missing RD_MACCs.
19
6d075bce
RS		 202013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
21
22 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
23
4f6ffcd3
PB		 242013-07-29 Peter Bergner <bergner@vnet.ibm.com>
25
26 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
27
43234a1e
L		 282013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
29 Alexander Ivchenko <alexander.ivchenko@intel.com>
30 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
31 Sergey Lega <sergey.s.lega@intel.com>
32 Anna Tikhonova <anna.tikhonova@intel.com>
33 Ilya Tocar <ilya.tocar@intel.com>
34 Andrey Turetskiy <andrey.turetskiy@intel.com>
35 Ilya Verbin <ilya.verbin@intel.com>
36 Kirill Yukhin <kirill.yukhin@intel.com>
37 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
38
39 * i386-dis-evex.h: New.
40 * i386-dis.c (OP_Rounding): New.
41 (VPCMP_Fixup): New.
42 (OP_Mask): New.
43 (Rdq): New.
44 (XMxmmq): New.
45 (EXdScalarS): New.
46 (EXymm): New.
47 (EXEvexHalfBcstXmmq): New.
48 (EXxmm_mdq): New.
49 (EXEvexXGscat): New.
50 (EXEvexXNoBcst): New.
51 (VPCMP): New.
52 (EXxEVexR): New.
53 (EXxEVexS): New.
54 (XMask): New.
55 (MaskG): New.
56 (MaskE): New.
57 (MaskR): New.
58 (MaskVex): New.
59 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
60 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
61 evex_rounding_mode, evex_sae_mode, mask_mode.
62 (USE_EVEX_TABLE): New.
63 (EVEX_TABLE): New.
64 (EVEX enum): New.
65 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
66 REG_EVEX_0F38C7.
67 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
68 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
69 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
70 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
71 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
72 MOD_EVEX_0F38C7_REG_6.
73 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
74 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
75 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
76 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
77 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
78 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
79 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
80 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
81 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
82 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
83 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
84 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
85 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
86 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
87 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
88 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
89 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
90 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
91 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
92 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
93 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
94 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
95 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
96 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
97 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
98 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
99 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
100 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
101 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
102 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
103 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
104 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
105 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
106 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
107 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
108 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
109 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
110 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
111 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
112 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
113 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
114 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
115 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
116 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
117 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
118 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
119 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
120 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
121 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
122 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
123 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
124 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
125 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
126 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
127 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
128 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
129 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
130 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
131 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
132 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
133 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
134 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
135 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
136 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
137 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
138 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
139 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
140 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
141 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
142 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
143 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
144 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
145 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
146 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
147 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
148 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
149 PREFIX_EVEX_0F3A55.
150 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
151 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
152 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
153 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
154 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
155 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
156 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
157 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
158 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
159 VEX_W_0F3A32_P_2_LEN_0.
160 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
161 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
162 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
163 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
164 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
165 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
166 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
167 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
168 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
169 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
170 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
171 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
172 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
173 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
174 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
175 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
176 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
177 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
178 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
179 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
180 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
181 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
182 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
183 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
184 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
185 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
186 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
187 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
188 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
189 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
190 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
191 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
192 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
193 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
194 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
195 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
196 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
197 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
198 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
199 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
200 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
201 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
202 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
203 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
204 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
205 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
206 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
207 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
208 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
209 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
210 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
211 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
212 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
213 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
214 (struct vex): Add fields evex, r, v, mask_register_specifier,
215 zeroing, ll, b.
216 (intel_names_xmm): Add upper 16 registers.
217 (att_names_xmm): Ditto.
218 (intel_names_ymm): Ditto.
219 (att_names_ymm): Ditto.
220 (names_zmm): New.
221 (intel_names_zmm): Ditto.
222 (att_names_zmm): Ditto.
223 (names_mask): Ditto.
224 (intel_names_mask): Ditto.
225 (att_names_mask): Ditto.
226 (names_rounding): Ditto.
227 (names_broadcast): Ditto.
228 (x86_64_table): Add escape to evex-table.
229 (reg_table): Include reg_table evex-entries from
230 i386-dis-evex.h. Fix prefetchwt1 instruction.
231 (prefix_table): Add entries for new instructions.
232 (vex_table): Ditto.
233 (vex_len_table): Ditto.
234 (vex_w_table): Ditto.
235 (mod_table): Ditto.
236 (get_valid_dis386): Properly handle new instructions.
237 (print_insn): Handle zmm and mask registers, print mask operand.
238 (intel_operand_size): Support EVEX, new modes and sizes.
239 (OP_E_register): Handle new modes.
240 (OP_E_memory): Ditto.
241 (OP_G): Ditto.
242 (OP_XMM): Ditto.
243 (OP_EX): Ditto.
244 (OP_VEX): Ditto.
245 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
246 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
247 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
248 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
249 CpuAVX512PF and CpuVREX.
250 (operand_type_init): Add OPERAND_TYPE_REGZMM,
251 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
252 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
253 StaticRounding, SAE, Disp8MemShift, NoDefMask.
254 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
255 * i386-init.h: Regenerate.
256 * i386-opc.h (CpuAVX512F): New.
257 (CpuAVX512CD): New.
258 (CpuAVX512ER): New.
259 (CpuAVX512PF): New.
260 (CpuVREX): New.
261 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
262 cpuavx512pf and cpuvrex fields.
263 (VecSIB): Add VecSIB512.
264 (EVex): New.
265 (Masking): New.
266 (VecESize): New.
267 (Broadcast): New.
268 (StaticRounding): New.
269 (SAE): New.
270 (Disp8MemShift): New.
271 (NoDefMask): New.
272 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
273 staticrounding, sae, disp8memshift and nodefmask.
274 (RegZMM): New.
275 (Zmmword): Ditto.
276 (Vec_Disp8): Ditto.
277 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
278 fields.
279 (RegVRex): New.
280 * i386-opc.tbl: Add AVX512 instructions.
281 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
282 registers, mask registers.
283 * i386-tbl.h: Regenerate.
284
1d2db237
RS		 2852013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
286
287 PR gas/15220
288 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
289 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
290
a0046408
L		 2912013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
292
293 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
294 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
295 PREFIX_0F3ACC.
296 (prefix_table): Updated.
297 (three_byte_table): Likewise.
298 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
299 (cpu_flags): Add CpuSHA.
300 (i386_cpu_flags): Add cpusha.
301 * i386-init.h: Regenerate.
302 * i386-opc.h (CpuSHA): New.
303 (CpuUnused): Restored.
304 (i386_cpu_flags): Add cpusha.
305 * i386-opc.tbl: Add SHA instructions.
306 * i386-tbl.h: Regenerate.
307
7e8b059b
L		 3082013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
309 Kirill Yukhin <kirill.yukhin@intel.com>
310 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
311
312 * i386-dis.c (BND_Fixup): New.
313 (Ebnd): New.
314 (Ev_bnd): New.
315 (Gbnd): New.
316 (BND): New.
317 (v_bnd_mode): New.
318 (bnd_mode): New.
c623f86c
L		 319 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
320 MOD_0F1B_PREFIX_1.
321 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 322 (dis tables): Replace XX with BND for near branch and call
323 instructions.
324 (prefix_table): Add new entries.
325 (mod_table): Likewise.
326 (names_bnd): New.
327 (intel_names_bnd): New.
328 (att_names_bnd): New.
329 (BND_PREFIX): New.
330 (prefix_name): Handle BND_PREFIX.
331 (print_insn): Initialize names_bnd.
332 (intel_operand_size): Handle new modes.
333 (OP_E_register): Likewise.
334 (OP_E_memory): Likewise.
335 (OP_G): Likewise.
336 * i386-gen.c (cpu_flag_init): Add CpuMPX.
337 (cpu_flags): Add CpuMPX.
338 (operand_type_init): Add RegBND.
339 (opcode_modifiers): Add BNDPrefixOk.
340 (operand_types): Add RegBND.
341 * i386-init.h: Regenerate.
342 * i386-opc.h (CpuMPX): New.
343 (CpuUnused): Comment out.
344 (i386_cpu_flags): Add cpumpx.
345 (BNDPrefixOk): New.
346 (i386_opcode_modifier): Add bndprefixok.
347 (RegBND): New.
348 (i386_operand_type): Add regbnd.
349 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
350 Add MPX instructions and bnd prefix.
351 * i386-reg.tbl: Add bnd0-bnd3 registers.
352 * i386-tbl.h: Regenerate.
353
b56e23fb
RS		 3542013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
355
356 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
357 ATTRIBUTE_UNUSED.
358
e7ae278d
RS		 3592013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
360
361 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
362 special rules.
363 * Makefile.in: Regenerate.
364 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
365 all fields. Reformat.
366
c3c07478
RS		 3672013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
368
369 * mips16-opc.c: Include mips-formats.h.
370 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
371 static arrays.
372 (decode_mips16_operand): New function.
373 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
374 (print_insn_arg): Handle OP_ENTRY_EXIT list.
375 Abort for OP_SAVE_RESTORE_LIST.
376 (print_mips16_insn_arg): Change interface. Use mips_operand
377 structures. Delete GET_OP_S. Move GET_OP definition to...
378 (print_insn_mips16): ...here. Call init_print_arg_state.
379 Update the call to print_mips16_insn_arg.
380
ab902481
RS		 3812013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
382
383 * mips-formats.h: New file.
384 * mips-opc.c: Include mips-formats.h.
385 (reg_0_map): New static array.
386 (decode_mips_operand): New function.
387 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
388 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
389 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
390 (int_c_map): New static arrays.
391 (decode_micromips_operand): New function.
392 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
393 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
394 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
395 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
396 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
397 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
398 (micromips_imm_b_map, micromips_imm_c_map): Delete.
399 (print_reg): New function.
400 (mips_print_arg_state): New structure.
401 (init_print_arg_state, print_insn_arg): New functions.
402 (print_insn_args): Change interface and use mips_operand structures.
403 Delete GET_OP_S. Move GET_OP definition to...
404 (print_insn_mips): ...here. Update the call to print_insn_args.
405 (print_insn_micromips): Use print_insn_args.
406
cc537e56
RS		 4072013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
408
409 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
410 in macros.
411
7a5f87ce
RS		 4122013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
413
414 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
415 ADDA.S, MULA.S and SUBA.S.
416
41741fa4
L		 4172013-07-08 H.J. Lu <hongjiu.lu@intel.com>
418
419 PR gas/13572
420 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
421 * i386-tbl.h: Regenerated.
422
f2ae14a1
RS		 4232013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
424
425 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
426 and SD A(B) macros up.
427 * micromips-opc.c (micromips_opcodes): Likewise.
428
04c9d415
RS		 4292013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
430
431 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
432 instructions.
433
5c324c16
RS		 4342013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
435
436 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
437 MDMX-like instructions.
438 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
439 printing "Q" operands for INSN_5400 instructions.
440
23e69e47
RS		 4412013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
442
443 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
444 "+S" for "cins".
445 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
446 Combine cases.
447
27c5c572
RS		 4482013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
449
450 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
451 "jalx".
452 * mips16-opc.c (mips16_opcodes): Likewise.
453 * micromips-opc.c (micromips_opcodes): Likewise.
454 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
455 (print_insn_mips16): Handle "+i".
456 (print_insn_micromips): Likewise. Conditionally preserve the
457 ISA bit for "a" but not for "+i".
458
e76ff5ab
RS		 4592013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
460
461 * micromips-opc.c (WR_mhi): Rename to..
462 (WR_mh): ...this.
463 (micromips_opcodes): Update "movep" entry accordingly. Replace
464 "mh,mi" with "mh".
465 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
466 (micromips_to_32_reg_h_map1): ...this.
467 (micromips_to_32_reg_i_map): Rename to...
468 (micromips_to_32_reg_h_map2): ...this.
469 (print_micromips_insn): Remove "mi" case. Print both registers
470 in the pair for "mh".
471
fa7616a4
RS		 4722013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
473
474 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
475 * micromips-opc.c (micromips_opcodes): Likewise.
476 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
477 and "+T" handling. Check for a "0" suffix when deciding whether to
478 use coprocessor 0 names. In that case, also check for ",H" selectors.
479
fb798c50
AK		 4802013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
481
482 * s390-opc.c (J12_12, J24_24): New macros.
483 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
484 (MASK_MII_UPI): Rename to MASK_MII_UPP.
485 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
486
58ae08f2
AM		 4872013-07-04 Alan Modra <amodra@gmail.com>
488
489 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
490
b5e04c2b
NC		 4912013-06-26 Nick Clifton <nickc@redhat.com>
492
493 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
494 field when checking for type 2 nop.
495 * rx-decode.c: Regenerate.
496
833794fc
MR		 4972013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
498
499 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
500 and "movep" macros.
501
1bbce132
MR		 5022013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
503
504 * mips-dis.c (is_mips16_plt_tail): New function.
505 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
506 word.
507 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
508
34c911a4
NC		 5092013-06-21 DJ Delorie <dj@redhat.com>
510
511 * msp430-decode.opc: New.
512 * msp430-decode.c: New/generated.
513 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
514 (MAINTAINER_CLEANFILES): Likewise.
515 Add rule to build msp430-decode.c frommsp430decode.opc
516 using the opc2c program.
517 * Makefile.in: Regenerate.
518 * configure.in: Add msp430-decode.lo to msp430 architecture files.
519 * configure: Regenerate.
520
b9eead84
YZ		 5212013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
522
523 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
524 (SYMTAB_AVAILABLE): Removed.
525 (#include "elf/aarch64.h): Ditto.
526
7f3c4072
CM		 5272013-06-17 Catherine Moore <clm@codesourcery.com>
528 Maciej W. Rozycki <macro@codesourcery.com>
529 Chao-Ying Fu <fu@mips.com>
530
531 * micromips-opc.c (EVA): Define.
532 (TLBINV): Define.
533 (micromips_opcodes): Add EVA opcodes.
534 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
535 (print_insn_args): Handle EVA offsets.
536 (print_insn_micromips): Likewise.
537 * mips-opc.c (EVA): Define.
538 (TLBINV): Define.
539 (mips_builtin_opcodes): Add EVA opcodes.
540
de40ceb6
AM		 5412013-06-17 Alan Modra <amodra@gmail.com>
542
543 * Makefile.am (mips-opc.lo): Add rules to create automatic
544 dependency files. Pass archdefs.
545 (micromips-opc.lo, mips16-opc.lo): Likewise.
546 * Makefile.in: Regenerate.
547
3531d549
DD		 5482013-06-14 DJ Delorie <dj@redhat.com>
549
550 * rx-decode.opc (rx_decode_opcode): Bit operations on
551 registers are 32-bit operations, not 8-bit operations.
552 * rx-decode.c: Regenerate.
553
ba92f7fb
CF		 5542013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
555
556 * micromips-opc.c (IVIRT): New define.
557 (IVIRT64): New define.
558 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
559 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
560
561 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
562 dmtgc0 to print cp0 names.
563
9daf7bab
SL		 5642013-06-09 Sandra Loosemore <sandra@codesourcery.com>
565
566 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
567 argument.
568
d301a56b
RS		 5692013-06-08 Catherine Moore <clm@codesourcery.com>
570 Richard Sandiford <rdsandiford@googlemail.com>
571
572 * micromips-opc.c (D32, D33, MC): Update definitions.
573 (micromips_opcodes): Initialize ase field.
574 * mips-dis.c (mips_arch_choice): Add ase field.
575 (mips_arch_choices): Initialize ase field.
576 (set_default_mips_dis_options): Declare and setup mips_ase.
577 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
578 MT32, MC): Update definitions.
579 (mips_builtin_opcodes): Initialize ase field.
580
a3dcb6c5
RS		 5812013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
582
583 * s390-opc.txt (flogr): Require a register pair destination.
584
6cf1d90c
AK		 5852013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
586
587 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
588 instruction format.
589
c77c0862
RS		 5902013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
591
592 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
593
c0637f3a
PB		 5942013-05-20 Peter Bergner <bergner@vnet.ibm.com>
595
596 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
597 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
598 XLS_MASK, PPCVSX2): New defines.
599 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
600 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
601 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
602 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
603 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
604 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
605 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
606 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
607 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
608 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
609 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
610 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
611 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
612 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
613 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
614 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
615 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
616 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
617 <lxvx, stxvx>: New extended mnemonics.
618
4934fdaf
AM		 6192013-05-17 Alan Modra <amodra@gmail.com>
620
621 * ia64-raw.tbl: Replace non-ASCII char.
622 * ia64-waw.tbl: Likewise.
623 * ia64-asmtab.c: Regenerate.
624
6091d651
SE		 6252013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
626
627 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
628 * i386-init.h: Regenerated.
629
d2865ed3
YZ		 6302013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
631
632 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
633 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
634 check from [0, 255] to [-128, 255].
635
b015e599
AP		 6362013-05-09 Andrew Pinski <apinski@cavium.com>
637
638 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
639 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
640 (parse_mips_dis_option): Handle the virt option.
641 (print_insn_args): Handle "+J".
642 (print_mips_disassembler_options): Print out message about virt64.
643 * mips-opc.c (IVIRT): New define.
644 (IVIRT64): New define.
645 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
646 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
647 Move rfe to the bottom as it conflicts with tlbgp.
648
9f0682fe
AM		 6492013-05-09 Alan Modra <amodra@gmail.com>
650
651 * ppc-opc.c (extract_vlesi): Properly sign extend.
652 (extract_vlensi): Likewise. Comment reason for setting invalid.
653
13761a11
NC		 6542013-05-02 Nick Clifton <nickc@redhat.com>
655
656 * msp430-dis.c: Add support for MSP430X instructions.
657
e3031850
SL		 6582013-04-24 Sandra Loosemore <sandra@codesourcery.com>
659
660 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
661 to "eccinj".
662
17310e56
NC		 6632013-04-17 Wei-chen Wang <cole945@gmail.com>
664
665 PR binutils/15369
666 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
667 of CGEN_CPU_ENDIAN.
668 (hash_insns_list): Likewise.
669
731df338
JK		 6702013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
671
672 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
673 warning workaround.
674
5f77db52
JB		 6752013-04-08 Jan Beulich <jbeulich@suse.com>
676
677 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
678 * i386-tbl.h: Re-generate.
679
0afd1215
DM		 6802013-04-06 David S. Miller <davem@davemloft.net>
681
682 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
683 of an opcode, prefer the one with F_PREFERRED set.
684 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
685 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
686 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
687 mark existing mnenomics as aliases. Add "cc" suffix to edge
688 instructions generating condition codes, mark existing mnenomics
689 as aliases. Add "fp" prefix to VIS compare instructions, mark
690 existing mnenomics as aliases.
691
41702d50
NC		 6922013-04-03 Nick Clifton <nickc@redhat.com>
693
694 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
695 destination address by subtracting the operand from the current
696 address.
697 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
698 a positive value in the insn.
699 (extract_u16_loop): Do not negate the returned value.
700 (D16_LOOP): Add V850_INVERSE_PCREL flag.
701
702 (ceilf.sw): Remove duplicate entry.
703 (cvtf.hs): New entry.
704 (cvtf.sh): Likewise.
705 (fmaf.s): Likewise.
706 (fmsf.s): Likewise.
707 (fnmaf.s): Likewise.
708 (fnmsf.s): Likewise.
709 (maddf.s): Restrict to E3V5 architectures.
710 (msubf.s): Likewise.
711 (nmaddf.s): Likewise.
712 (nmsubf.s): Likewise.
713
55cf16e1
L		 7142013-03-27 H.J. Lu <hongjiu.lu@intel.com>
715
716 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
717 check address mode.
718 (print_insn): Pass sizeflag to get_sib.
719
51dcdd4d
NC		 7202013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
721
722 PR binutils/15068
723 * tic6x-dis.c: Add support for displaying 16-bit insns.
724
795b8e6b
NC		 7252013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
726
727 PR gas/15095
728 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
729 individual msb and lsb halves in src1 & src2 fields. Discard the
730 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
731 follow what Ti SDK does in that case as any value in the src1
732 field yields the same output with SDK disassembler.
733
314d60dd
ME		 7342013-03-12 Michael Eager <eager@eagercon.com>
735
795b8e6b 736 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 737
dad60f8e
SL		 7382013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
739
740 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
741
f5cb796a
SL		 7422013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
743
744 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
745
21fde85c
SL		 7462013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
747
748 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
749
dd5181d5
KT		 7502013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
751
752 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
753 (thumb32_opcodes): Likewise.
754 (print_insn_thumb32): Handle 'S' control char.
755
87a8d6cb
NC		 7562013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
757
758 * lm32-desc.c: Regenerate.
759
99dce992
L		 7602013-03-01 H.J. Lu <hongjiu.lu@intel.com>
761
762 * i386-reg.tbl (riz): Add RegRex64.
763 * i386-tbl.h: Regenerated.
764
e60bb1dd
YZ		 7652013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
766
767 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
768 (aarch64_feature_crc): New static.
769 (CRC): New macro.
770 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
771 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
772 * aarch64-asm-2.c: Re-generate.
773 * aarch64-dis-2.c: Ditto.
774 * aarch64-opc-2.c: Ditto.
775
c7570fcd
AM		 7762013-02-27 Alan Modra <amodra@gmail.com>
777
778 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
779 * rl78-decode.c: Regenerate.
780
151fa98f
NC		 7812013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
782
783 * rl78-decode.opc: Fix encoding of DIVWU insn.
784 * rl78-decode.c: Regenerate.
785
5c111e37
L		 7862013-02-19 H.J. Lu <hongjiu.lu@intel.com>
787
788 PR gas/15159
789 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
790
791 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
792 (cpu_flags): Add CpuSMAP.
793
794 * i386-opc.h (CpuSMAP): New.
795 (i386_cpu_flags): Add cpusmap.
796
797 * i386-opc.tbl: Add clac and stac.
798
799 * i386-init.h: Regenerated.
800 * i386-tbl.h: Likewise.
801
9d1df426
NC		 8022013-02-15 Markos Chandras <markos.chandras@imgtec.com>
803
804 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
805 which also makes the disassembler output be in little
806 endian like it should be.
807
a1ccaec9
YZ		 8082013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
809
810 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
811 fields to NULL.
812 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
813
ef068ef4 8142013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 815
816 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
817 section disassembled.
818
6fe6ded9
RE		 8192013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
820
821 * arm-dis.c: Update strht pattern.
822
0aa27725
RS		 8232013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
824
825 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
826 single-float. Disable ll, lld, sc and scd for EE. Disable the
827 trunc.w.s macro for EE.
828
36591ba1
SL		 8292013-02-06 Sandra Loosemore <sandra@codesourcery.com>
830 Andrew Jenner <andrew@codesourcery.com>
831
832 Based on patches from Altera Corporation.
833
834 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
835 nios2-opc.c.
836 * Makefile.in: Regenerated.
837 * configure.in: Add case for bfd_nios2_arch.
838 * configure: Regenerated.
839 * disassemble.c (ARCH_nios2): Define.
840 (disassembler): Add case for bfd_arch_nios2.
841 * nios2-dis.c: New file.
842 * nios2-opc.c: New file.
843
545093a4
AM		 8442013-02-04 Alan Modra <amodra@gmail.com>
845
846 * po/POTFILES.in: Regenerate.
847 * rl78-decode.c: Regenerate.
848 * rx-decode.c: Regenerate.
849
e30181a5
YZ		 8502013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
851
852 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
853 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
854 * aarch64-asm.c (convert_xtl_to_shll): New function.
855 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
856 calling convert_xtl_to_shll.
857 * aarch64-dis.c (convert_shll_to_xtl): New function.
858 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
859 calling convert_shll_to_xtl.
860 * aarch64-gen.c: Update copyright year.
861 * aarch64-asm-2.c: Re-generate.
862 * aarch64-dis-2.c: Re-generate.
863 * aarch64-opc-2.c: Re-generate.
864
78c8d46c
NC		 8652013-01-24 Nick Clifton <nickc@redhat.com>
866
867 * v850-dis.c: Add support for e3v5 architecture.
868 * v850-opc.c: Likewise.
869
f5555712
YZ		 8702013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
871
872 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
873 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
874 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 875 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 876 alignment check; change to call set_sft_amount_out_of_range_error
877 instead of set_imm_out_of_range_error.
878 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
879 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
880 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
881 SIMD_IMM_SFT.
882
2f81ff92
L		 8832013-01-16 H.J. Lu <hongjiu.lu@intel.com>
884
885 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
886
887 * i386-init.h: Regenerated.
888 * i386-tbl.h: Likewise.
889
dd42f060
NC		 8902013-01-15 Nick Clifton <nickc@redhat.com>
891
892 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
893 values.
894 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
895
a4533ed8
NC		 8962013-01-14 Will Newton <will.newton@imgtec.com>
897
898 * metag-dis.c (REG_WIDTH): Increase to 64.
899
5817ffd1
PB		 9002013-01-10 Peter Bergner <bergner@vnet.ibm.com>
901
902 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
903 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
904 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
905 (SH6): Update.
906 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
907 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
908 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
909 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
910
a3c62988
NC		 9112013-01-10 Will Newton <will.newton@imgtec.com>
912
913 * Makefile.am: Add Meta.
914 * configure.in: Add Meta.
915 * disassemble.c: Add Meta support.
916 * metag-dis.c: New file.
917 * Makefile.in: Regenerate.
918 * configure: Regenerate.
919
73335eae
NC		 9202013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
921
922 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
923 (match_opcode): Rename to cr16_match_opcode.
924
e407c74b
NC		 9252013-01-04 Juergen Urban <JuergenUrban@gmx.de>
926
927 * mips-dis.c: Add names for CP0 registers of r5900.
928 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
929 instructions sq and lq.
930 Add support for MIPS r5900 CPU.
931 Add support for 128 bit MMI (Multimedia Instructions).
932 Add support for EE instructions (Emotion Engine).
933 Disable unsupported floating point instructions (64 bit and
934 undefined compare operations).
935 Enable instructions of MIPS ISA IV which are supported by r5900.
936 Disable 64 bit co processor instructions.
937 Disable 64 bit multiplication and division instructions.
938 Disable instructions for co-processor 2 and 3, because these are
939 not supported (preparation for later VU0 support (Vector Unit)).
940 Disable cvt.w.s because this behaves like trunc.w.s and the
941 correct execution can't be ensured on r5900.
942 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
943 will confuse less developers and compilers.
944
a32c3ff8
NC		 9452013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
946
fb098a1e
YZ		 947 * aarch64-opc.c (aarch64_print_operand): Change to print
948 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
949 in comment.
950 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
951 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
952 OP_MOV_IMM_WIDE.
953
9542013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
955
956 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
957 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 958
62658407
L		 9592013-01-02 H.J. Lu <hongjiu.lu@intel.com>
960
961 * i386-gen.c (process_copyright): Update copyright year to 2013.
962
bab4becb 9632013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 964
bab4becb
NC		 965 * cr16-dis.c (match_opcode,make_instruction): Remove static
966 declaration.
967 (dwordU,wordU): Moved typedefs to opcode/cr16.h
968 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 969
bab4becb 970For older changes see ChangeLog-2012
252b5132 971\f
bab4becb 972Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 973
974Copying and distribution of this file, with or without modification,
975are permitted in any medium without royalty provided the copyright
976notice and this notice are preserved.
977
252b5132 978Local Variables:
2f6d2f85
NC		 979mode: change-log
980left-margin: 8
981fill-column: 74
252b5132
RH		 982version-control: never
983End:
GDB Binutils - Deliverables
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