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45181ed1
AC		 12005-01-24 Andrew Cagney <cagney@gnu.org>
2
3 * configure: Regenerate, ../gettext.m4 was updated.
4
9e836e3d
FF		 52005-01-21 Fred Fish <fnf@specifixinc.com>
6
7 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
8 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
9 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
10 * mips-dis.c: Ditto.
11
5e8cb021
AM		 122005-01-20 Alan Modra <amodra@bigpond.net.au>
13
14 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
15
986e18a5
FF		 162005-01-19 Fred Fish <fnf@specifixinc.com>
17
18 * mips-dis.c (no_aliases): New disassembly option flag.
19 (set_default_mips_dis_options): Init no_aliases to zero.
20 (parse_mips_dis_option): Handle no-aliases option.
21 (print_insn_mips): Ignore table entries that are aliases
22 if no_aliases is set.
23 (print_insn_mips16): Ditto.
24 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
25 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
26 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
27 * mips16-opc.c (mips16_opcodes): Ditto.
28
e38bc3b5
NC		 292005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
30
31 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
32 (inheritance diagram): Add missing edge.
33 (arch_sh1_up): Rename arch_sh_up to match external name to make life
34 easier for the testsuite.
35 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
36 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
37 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
38 arch_sh2a_or_sh4_up child.
39 (sh_table): Do renaming as above.
40 Correct comment for ldc.l for gas testsuite to read.
41 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
42 Correct comments for movy.w and movy.l for gas testsuite to read.
43 Correct comments for fmov.d and fmov.s for gas testsuite to read.
44
9df48ba9
L		 452005-01-12 H.J. Lu <hongjiu.lu@intel.com>
46
47 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
48
2033b4b9
L		 492005-01-12 H.J. Lu <hongjiu.lu@intel.com>
50
51 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
52
0bcb06d2
AS		 532005-01-10 Andreas Schwab <schwab@suse.de>
54
55 * disassemble.c (disassemble_init_for_target) <case
56 bfd_arch_ia64>: Set skip_zeroes to 16.
57 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
58
47add74d
TL		 592004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
60
61 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
62
246f4c05
SS		 632004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
64
65 * avr-dis.c: Prettyprint. Added printing of symbol names in all
66 memory references. Convert avr_operand() to C90 formatting.
67
0e1200e5
TL		 682004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
69
70 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
71
89a649f7
TL		 722004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
73
74 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
75 (no_op_insn): Initialize array with instructions that have no
76 operands.
77 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
78
6255809c
RE		 792004-11-29 Richard Earnshaw <rearnsha@arm.com>
80
81 * arm-dis.c: Correct top-level comment.
82
2fbad815
RE		 832004-11-27 Richard Earnshaw <rearnsha@arm.com>
84
85 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
86 architecuture defining the insn.
87 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 88 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
89 field.
2fbad815
RE		 90 Also include opcode/arm.h.
91 * Makefile.am (arm-dis.lo): Update dependency list.
92 * Makefile.in: Regenerate.
93
d81acc42
NC		 942004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
95
96 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
97 reflect the change to the short immediate syntax.
98
ca4f2377
AM		 992004-11-19 Alan Modra <amodra@bigpond.net.au>
100
5da8bf1b
AM		 101 * or32-opc.c (debug): Warning fix.
102 * po/POTFILES.in: Regenerate.
103
ca4f2377
AM		 104 * maxq-dis.c: Formatting.
105 (print_insn): Warning fix.
106
b7693d02
DJ		 1072004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
108
109 * arm-dis.c (WORD_ADDRESS): Define.
110 (print_insn): Use it. Correct big-endian end-of-section handling.
111
300dac7e
NC		 1122004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
113 Vineet Sharma <vineets@noida.hcltech.com>
114
115 * maxq-dis.c: New file.
116 * disassemble.c (ARCH_maxq): Define.
117 (disassembler): Add 'print_insn_maxq_little' for handling maxq
118 instructions..
119 * configure.in: Add case for bfd_maxq_arch.
120 * configure: Regenerate.
121 * Makefile.am: Add support for maxq-dis.c
122 * Makefile.in: Regenerate.
123 * aclocal.m4: Regenerate.
124
42048ee7
TL		 1252004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
126
127 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
128 mode.
129 * crx-dis.c: Likewise.
130
bd21e58e
HPN		 1312004-11-04 Hans-Peter Nilsson <hp@axis.com>
132
133 Generally, handle CRISv32.
134 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
135 (struct cris_disasm_data): New type.
136 (format_reg, format_hex, cris_constraint, print_flags)
137 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
138 callers changed.
139 (format_sup_reg, print_insn_crisv32_with_register_prefix)
140 (print_insn_crisv32_without_register_prefix)
141 (print_insn_crisv10_v32_with_register_prefix)
142 (print_insn_crisv10_v32_without_register_prefix)
143 (cris_parse_disassembler_options): New functions.
144 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
145 parameter. All callers changed.
146 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
147 failure.
148 (cris_constraint) <case 'Y', 'U'>: New cases.
149 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
150 for constraint 'n'.
151 (print_with_operands) <case 'Y'>: New case.
152 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
153 <case 'N', 'Y', 'Q'>: New cases.
154 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
155 (print_insn_cris_with_register_prefix)
156 (print_insn_cris_without_register_prefix): Call
157 cris_parse_disassembler_options.
158 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
159 for CRISv32 and the size of immediate operands. New v32-only
160 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
161 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
162 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
163 Change brp to be v3..v10.
164 (cris_support_regs): New vector.
165 (cris_opcodes): Update head comment. New format characters '[',
166 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
167 Add new opcodes for v32 and adjust existing opcodes to accommodate
168 differences to earlier variants.
169 (cris_cond15s): New vector.
170
9306ca4a
JB		 1712004-11-04 Jan Beulich <jbeulich@novell.com>
172
173 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
174 (indirEb): Remove.
175 (Mp): Use f_mode rather than none at all.
176 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
177 replaces what previously was x_mode; x_mode now means 128-bit SSE
178 operands.
179 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
180 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
181 pinsrw's second operand is Edqw.
182 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
183 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
184 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
185 mode when an operand size override is present or always suffixing.
186 More instructions will need to be added to this group.
187 (putop): Handle new macro chars 'C' (short/long suffix selector),
188 'I' (Intel mode override for following macro char), and 'J' (for
189 adding the 'l' prefix to far branches in AT&T mode). When an
190 alternative was specified in the template, honor macro character when
191 specified for Intel mode.
192 (OP_E): Handle new *_mode values. Correct pointer specifications for
193 memory operands. Consolidate output of index register.
194 (OP_G): Handle new *_mode values.
195 (OP_I): Handle const_1_mode.
196 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
197 respective opcode prefix bits have been consumed.
198 (OP_EM, OP_EX): Provide some default handling for generating pointer
199 specifications.
200
f39c96a9
TL		 2012004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
202
203 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
204 COP_INST macro.
205
812337be
TL		 2062004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
207
208 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
209 (getregliststring): Support HI/LO and user registers.
210 * crx-opc.c (crx_instruction): Update data structure according to the
211 rearrangement done in CRX opcode header file.
212 (crx_regtab): Likewise.
213 (crx_optab): Likewise.
214 (crx_instruction): Reorder load/stor instructions, remove unsupported
215 formats.
216 support new Co-Processor instruction 'cpi'.
217
4030fa5a
NC		 2182004-10-27 Nick Clifton <nickc@redhat.com>
219
220 * opcodes/iq2000-asm.c: Regenerate.
221 * opcodes/iq2000-desc.c: Regenerate.
222 * opcodes/iq2000-desc.h: Regenerate.
223 * opcodes/iq2000-dis.c: Regenerate.
224 * opcodes/iq2000-ibld.c: Regenerate.
225 * opcodes/iq2000-opc.c: Regenerate.
226 * opcodes/iq2000-opc.h: Regenerate.
227
fc3d45e8
TL		 2282004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
229
230 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
231 us4, us5 (respectively).
232 Remove unsupported 'popa' instruction.
233 Reverse operands order in store co-processor instructions.
234
3c55da70
AM		 2352004-10-15 Alan Modra <amodra@bigpond.net.au>
236
237 * Makefile.am: Run "make dep-am"
238 * Makefile.in: Regenerate.
239
7fa3d080
BW		 2402004-10-12 Bob Wilson <bob.wilson@acm.org>
241
242 * xtensa-dis.c: Use ISO C90 formatting.
243
e612bb4d
AM		 2442004-10-09 Alan Modra <amodra@bigpond.net.au>
245
246 * ppc-opc.c: Revert 2004-09-09 change.
247
43cd72b9
BW		 2482004-10-07 Bob Wilson <bob.wilson@acm.org>
249
250 * xtensa-dis.c (state_names): Delete.
251 (fetch_data): Use xtensa_isa_maxlength.
252 (print_xtensa_operand): Replace operand parameter with opcode/operand
253 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
254 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
255 instruction bundles. Use xmalloc instead of malloc.
256
bbac1f2a
NC		 2572004-10-07 David Gibson <david@gibson.dropbear.id.au>
258
259 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
260 initializers.
261
48c9f030
NC		 2622004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
263
264 * crx-opc.c (crx_instruction): Support Co-processor insns.
265 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
266 (getregliststring): Change function to use the above enum.
267 (print_arg): Handle CO-Processor insns.
268 (crx_cinvs): Add 'b' option to invalidate the branch-target
269 cache.
270
12c64a4e
AH		 2712004-10-06 Aldy Hernandez <aldyh@redhat.com>
272
273 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
274 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
275 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
276 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
277 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
278
14127cc4
NC		 2792004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
280
281 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
282 rather than add it.
283
0dd132b6
NC		 2842004-09-30 Paul Brook <paul@codesourcery.com>
285
286 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
287 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
288
3f85e526
L		 2892004-09-17 H.J. Lu <hongjiu.lu@intel.com>
290
291 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
292 (CONFIG_STATUS_DEPENDENCIES): New.
293 (Makefile): Removed.
294 (config.status): Likewise.
295 * Makefile.in: Regenerated.
296
8ae85421
AM		 2972004-09-17 Alan Modra <amodra@bigpond.net.au>
298
299 * Makefile.am: Run "make dep-am".
300 * Makefile.in: Regenerate.
301 * aclocal.m4: Regenerate.
302 * configure: Regenerate.
303 * po/POTFILES.in: Regenerate.
304 * po/opcodes.pot: Regenerate.
305
24443139
AS		 3062004-09-11 Andreas Schwab <schwab@suse.de>
307
308 * configure: Rebuild.
309
2a309db0
AM		 3102004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
311
312 * ppc-opc.c (L): Make this field not optional.
313
42851540
NC		 3142004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
315
316 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
317 Fix parameter to 'm[t|f]csr' insns.
318
979273e3
NN		 3192004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
320
321 * configure.in: Autoupdate to autoconf 2.59.
322 * aclocal.m4: Rebuild with aclocal 1.4p6.
323 * configure: Rebuild with autoconf 2.59.
324 * Makefile.in: Rebuild with automake 1.4p6 (picking up
325 bfd changes for autoconf 2.59 on the way).
326 * config.in: Rebuild with autoheader 2.59.
327
ac28a1cb
RS		 3282004-08-27 Richard Sandiford <rsandifo@redhat.com>
329
330 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
331
30d1c836
ML		 3322004-07-30 Michal Ludvig <mludvig@suse.cz>
333
334 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
335 (GRPPADLCK2): New define.
336 (twobyte_has_modrm): True for 0xA6.
337 (grps): GRPPADLCK2 for opcode 0xA6.
338
0b0ac059
AO		 3392004-07-29 Alexandre Oliva <aoliva@redhat.com>
340
341 Introduce SH2a support.
342 * sh-opc.h (arch_sh2a_base): Renumber.
343 (arch_sh2a_nofpu_base): Remove.
344 (arch_sh_base_mask): Adjust.
345 (arch_opann_mask): New.
346 (arch_sh2a, arch_sh2a_nofpu): Adjust.
347 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
348 (sh_table): Adjust whitespace.
349 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
350 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
351 instruction list throughout.
352 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
353 of arch_sh2a in instruction list throughout.
354 (arch_sh2e_up): Accomodate above changes.
355 (arch_sh2_up): Ditto.
356 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
357 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
358 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
359 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
360 * sh-opc.h (arch_sh2a_nofpu): New.
361 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
362 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
363 instruction.
364 2004-01-20 DJ Delorie <dj@redhat.com>
365 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
366 2003-12-29 DJ Delorie <dj@redhat.com>
367 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
368 sh_opcode_info, sh_table): Add sh2a support.
369 (arch_op32): New, to tag 32-bit opcodes.
370 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
371 2003-12-02 Michael Snyder <msnyder@redhat.com>
372 * sh-opc.h (arch_sh2a): Add.
373 * sh-dis.c (arch_sh2a): Handle.
374 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
375
670ec21d
NC		 3762004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
377
378 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
379
ed049af3
NC		 3802004-07-22 Nick Clifton <nickc@redhat.com>
381
382 PR/280
383 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
384 insns - this is done by objdump itself.
385 * h8500-dis.c (print_insn_h8500): Likewise.
386
20f0a1fc
NC		 3872004-07-21 Jan Beulich <jbeulich@novell.com>
388
389 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
390 regardless of address size prefix in effect.
391 (ptr_reg): Size or address registers does not depend on rex64, but
392 on the presence of an address size override.
393 (OP_MMX): Use rex.x only for xmm registers.
394 (OP_EM): Use rex.z only for xmm registers.
395
6f14957b
MR		 3962004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
397
398 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
399 move/branch operations to the bottom so that VR5400 multimedia
400 instructions take precedence in disassembly.
401
1586d91e
MR		 4022004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
403
404 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
405 ISA-specific "break" encoding.
406
982de27a
NC		 4072004-07-13 Elvis Chiang <elvisfb@gmail.com>
408
409 * arm-opc.h: Fix typo in comment.
410
4300ab10
AS		 4112004-07-11 Andreas Schwab <schwab@suse.de>
412
413 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
414
8577e690
AS		 4152004-07-09 Andreas Schwab <schwab@suse.de>
416
417 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
418
1fe1f39c
NC		 4192004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
420
421 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
422 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
423 (crx-dis.lo): New target.
424 (crx-opc.lo): Likewise.
425 * Makefile.in: Regenerate.
426 * configure.in: Handle bfd_crx_arch.
427 * configure: Regenerate.
428 * crx-dis.c: New file.
429 * crx-opc.c: New file.
430 * disassemble.c (ARCH_crx): Define.
431 (disassembler): Handle ARCH_crx.
432
7a33b495
JW		 4332004-06-29 James E Wilson <wilson@specifixinc.com>
434
435 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
436 * ia64-asmtab.c: Regnerate.
437
98e69875
AM		 4382004-06-28 Alan Modra <amodra@bigpond.net.au>
439
440 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
441 (extract_fxm): Don't test dialect.
442 (XFXFXM_MASK): Include the power4 bit.
443 (XFXM): Add p4 param.
444 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
445
a53b85e2
AO		 4462004-06-27 Alexandre Oliva <aoliva@redhat.com>
447
448 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
449 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
450
d0618d1c
AM		 4512004-06-26 Alan Modra <amodra@bigpond.net.au>
452
453 * ppc-opc.c (BH, XLBH_MASK): Define.
454 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
455
1d9f512f
AM		 4562004-06-24 Alan Modra <amodra@bigpond.net.au>
457
458 * i386-dis.c (x_mode): Comment.
459 (two_source_ops): File scope.
460 (float_mem): Correct fisttpll and fistpll.
461 (float_mem_mode): New table.
462 (dofloat): Use it.
463 (OP_E): Correct intel mode PTR output.
464 (ptr_reg): Use open_char and close_char.
465 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
466 operands. Set two_source_ops.
467
52886d70
AM		 4682004-06-15 Alan Modra <amodra@bigpond.net.au>
469
470 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
471 instead of _raw_size.
472
bad9ceea
JJ		 4732004-06-08 Jakub Jelinek <jakub@redhat.com>
474
475 * ia64-gen.c (in_iclass): Handle more postinc st
476 and ld variants.
477 * ia64-asmtab.c: Rebuilt.
478
0451f5df
MS		 4792004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
480
481 * s390-opc.txt: Correct architecture mask for some opcodes.
482 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
483 in the esa mode as well.
484
f6f9408f
JR		 4852004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
486
487 * sh-dis.c (target_arch): Make unsigned.
488 (print_insn_sh): Replace (most of) switch with a call to
489 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
490 * sh-opc.h: Redefine architecture flags values.
491 Add sh3-nommu architecture.
492 Reorganise <arch>_up macros so they make more visual sense.
493 (SH_MERGE_ARCH_SET): Define new macro.
494 (SH_VALID_BASE_ARCH_SET): Likewise.
495 (SH_VALID_MMU_ARCH_SET): Likewise.
496 (SH_VALID_CO_ARCH_SET): Likewise.
497 (SH_VALID_ARCH_SET): Likewise.
498 (SH_MERGE_ARCH_SET_VALID): Likewise.
499 (SH_ARCH_SET_HAS_FPU): Likewise.
500 (SH_ARCH_SET_HAS_DSP): Likewise.
501 (SH_ARCH_UNKNOWN_ARCH): Likewise.
502 (sh_get_arch_from_bfd_mach): Add prototype.
503 (sh_get_arch_up_from_bfd_mach): Likewise.
504 (sh_get_bfd_mach_from_arch_set): Likewise.
505 (sh_merge_bfd_arc): Likewise.
506
be8c092b
NC		 5072004-05-24 Peter Barada <peter@the-baradas.com>
508
509 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
510 into new match_insn_m68k function. Loop over canidate
511 matches and select first that completely matches.
512 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
513 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
514 to verify addressing for MAC/EMAC.
515 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
516 reigster halves since 'fpu' and 'spl' look misleading.
517 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
518 * m68k-opc.c: Rearragne mac/emac cases to use longest for
519 first, tighten up match masks.
520 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
521 'size' from special case code in print_insn_m68k to
522 determine decode size of insns.
523
a30e9cc4
AM		 5242004-05-19 Alan Modra <amodra@bigpond.net.au>
525
526 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
527 well as when -mpower4.
528
9598fbe5
NC		 5292004-05-13 Nick Clifton <nickc@redhat.com>
530
531 * po/fr.po: Updated French translation.
532
6b6e92f4
NC		 5332004-05-05 Peter Barada <peter@the-baradas.com>
534
535 * m68k-dis.c(print_insn_m68k): Add new chips, use core
536 variants in arch_mask. Only set m68881/68851 for 68k chips.
537 * m68k-op.c: Switch from ColdFire chips to core variants.
538
a404d431
AM		 5392004-05-05 Alan Modra <amodra@bigpond.net.au>
540
a30e9cc4 541 PR 147.
a404d431
AM		 542 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
543
f3806e43
BE		 5442004-04-29 Ben Elliston <bje@au.ibm.com>
545
520ceea4
BE		 546 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
547 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 548
1f1799d5
KK		 5492004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
550
551 * sh-dis.c (print_insn_sh): Print the value in constant pool
552 as a symbol if it looks like a symbol.
553
fd99574b
NC		 5542004-04-22 Peter Barada <peter@the-baradas.com>
555
556 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
557 appropriate ColdFire architectures.
558 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
559 mask addressing.
560 Add EMAC instructions, fix MAC instructions. Remove
561 macmw/macml/msacmw/msacml instructions since mask addressing now
562 supported.
563
b4781d44
JJ		 5642004-04-20 Jakub Jelinek <jakub@redhat.com>
565
566 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
567 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
568 suffix. Use fmov*x macros, create all 3 fpsize variants in one
569 macro. Adjust all users.
570
91809fda
NC		 5712004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
572
573 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
574 separately.
575
f4453dfa
NC		 5762004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
577
578 * m32r-asm.c: Regenerate.
579
9b0de91a
SS		 5802004-03-29 Stan Shebs <shebs@apple.com>
581
582 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
583 used.
584
e20c0b3d
AM		 5852004-03-19 Alan Modra <amodra@bigpond.net.au>
586
587 * aclocal.m4: Regenerate.
588 * config.in: Regenerate.
589 * configure: Regenerate.
590 * po/POTFILES.in: Regenerate.
591 * po/opcodes.pot: Regenerate.
592
fdd12ef3
AM		 5932004-03-16 Alan Modra <amodra@bigpond.net.au>
594
595 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
596 PPC_OPERANDS_GPR_0.
597 * ppc-opc.c (RA0): Define.
598 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
599 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 600 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 601
2dc111b3 6022004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 603
604 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 605
7bfeee7b
AM		 6062004-03-15 Alan Modra <amodra@bigpond.net.au>
607
608 * sparc-dis.c (print_insn_sparc): Update getword prototype.
609
7ffdda93
ML		 6102004-03-12 Michal Ludvig <mludvig@suse.cz>
611
612 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 613 (grps): Delete GRPPLOCK entry.
7ffdda93 614
cc0ec051
AM		 6152004-03-12 Alan Modra <amodra@bigpond.net.au>
616
617 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
618 (M, Mp): Use OP_M.
619 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
620 (GRPPADLCK): Define.
621 (dis386): Use NOP_Fixup on "nop".
622 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
623 (twobyte_has_modrm): Set for 0xa7.
624 (padlock_table): Delete. Move to..
625 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
626 and clflush.
627 (print_insn): Revert PADLOCK_SPECIAL code.
628 (OP_E): Delete sfence, lfence, mfence checks.
629
4fd61dcb
JJ		 6302004-03-12 Jakub Jelinek <jakub@redhat.com>
631
632 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
633 (INVLPG_Fixup): New function.
634 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
635
0f10071e
ML		 6362004-03-12 Michal Ludvig <mludvig@suse.cz>
637
638 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
639 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
640 (padlock_table): New struct with PadLock instructions.
641 (print_insn): Handle PADLOCK_SPECIAL.
642
c02908d2
AM		 6432004-03-12 Alan Modra <amodra@bigpond.net.au>
644
645 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
646 (OP_E): Twiddle clflush to sfence here.
647
d5bb7600
NC		 6482004-03-08 Nick Clifton <nickc@redhat.com>
649
650 * po/de.po: Updated German translation.
651
ae51a426
JR		 6522003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
653
654 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
655 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
656 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
657 accordingly.
658
676a64f4
RS		 6592004-03-01 Richard Sandiford <rsandifo@redhat.com>
660
661 * frv-asm.c: Regenerate.
662 * frv-desc.c: Regenerate.
663 * frv-desc.h: Regenerate.
664 * frv-dis.c: Regenerate.
665 * frv-ibld.c: Regenerate.
666 * frv-opc.c: Regenerate.
667 * frv-opc.h: Regenerate.
668
c7a48b9a
RS		 6692004-03-01 Richard Sandiford <rsandifo@redhat.com>
670
671 * frv-desc.c, frv-opc.c: Regenerate.
672
8ae0baa2
RS		 6732004-03-01 Richard Sandiford <rsandifo@redhat.com>
674
675 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
676
ce11586c
JR		 6772004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
678
679 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
680 Also correct mistake in the comment.
681
6a5709a5
JR		 6822004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
683
684 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
685 ensure that double registers have even numbers.
686 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
687 that reserved instruction 0xfffd does not decode the same
688 as 0xfdfd (ftrv).
689 * sh-opc.h: Add REG_N_D nibble type and use it whereever
690 REG_N refers to a double register.
691 Add REG_N_B01 nibble type and use it instead of REG_NM
692 in ftrv.
693 Adjust the bit patterns in a few comments.
694
e5d2b64f 6952004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 696
697 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 698
1f04b05f
AH		 6992004-02-20 Aldy Hernandez <aldyh@redhat.com>
700
701 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
702
2f3b8700
AH		 7032004-02-20 Aldy Hernandez <aldyh@redhat.com>
704
705 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
706
f0b26da6 7072004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 708
709 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
710 mtivor32, mtivor33, mtivor34.
f0b26da6 711
23d59c56 7122004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 713
714 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 715
34920d91
NC		 7162004-02-10 Petko Manolov <petkan@nucleusys.com>
717
718 * arm-opc.h Maverick accumulator register opcode fixes.
719
44d86481
BE		 7202004-02-13 Ben Elliston <bje@wasabisystems.com>
721
722 * m32r-dis.c: Regenerate.
723
17707c23
MS		 7242004-01-27 Michael Snyder <msnyder@redhat.com>
725
726 * sh-opc.h (sh_table): "fsrra", not "fssra".
727
fe3a9bc4
NC		 7282004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
729
730 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
731 contraints.
732
ff24f124
JJ		 7332004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
734
735 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
736
a02a862a
AM		 7372004-01-19 Alan Modra <amodra@bigpond.net.au>
738
739 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
740 1. Don't print scale factor on AT&T mode when index missing.
741
d164ea7f
AO		 7422004-01-16 Alexandre Oliva <aoliva@redhat.com>
743
744 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
745 when loaded into XR registers.
746
cb10e79a
RS		 7472004-01-14 Richard Sandiford <rsandifo@redhat.com>
748
749 * frv-desc.h: Regenerate.
750 * frv-desc.c: Regenerate.
751 * frv-opc.c: Regenerate.
752
f532f3fa
MS		 7532004-01-13 Michael Snyder <msnyder@redhat.com>
754
755 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
756
e45d0630
PB		 7572004-01-09 Paul Brook <paul@codesourcery.com>
758
759 * arm-opc.h (arm_opcodes): Move generic mcrr after known
760 specific opcodes.
761
3ba7a1aa
DJ		 7622004-01-07 Daniel Jacobowitz <drow@mvista.com>
763
764 * Makefile.am (libopcodes_la_DEPENDENCIES)
765 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
766 comment about the problem.
767 * Makefile.in: Regenerate.
768
ba2d3f07
AO		 7692004-01-06 Alexandre Oliva <aoliva@redhat.com>
770
771 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
772 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
773 cut&paste errors in shifting/truncating numerical operands.
774 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
775 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
776 (parse_uslo16): Likewise.
777 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
778 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
779 (parse_s12): Likewise.
780 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
781 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
782 (parse_uslo16): Likewise.
783 (parse_uhi16): Parse gothi and gotfuncdeschi.
784 (parse_d12): Parse got12 and gotfuncdesc12.
785 (parse_s12): Likewise.
786
3ab48931
NC		 7872004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
788
789 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
790 instruction which looks similar to an 'rla' instruction.
a0bd404e 791
c9e214e5 792For older changes see ChangeLog-0203
252b5132
RH		 793\f
794Local Variables:
2f6d2f85
NC		 795mode: change-log
796left-margin: 8
797fill-column: 74
252b5132
RH		 798version-control: never
799End:
GDB Binutils - Deliverables
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