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Stop the ARM short mapping symbol test being run for the symbianelf target.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a915c10f
NC		 12015-11-20 Nick Clifton <nickc@redhat.com>
2
3 PR binutils/19224
4 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
5
f8c2a965
NC		 62015-11-20 Nick Clifton <nickc@redhat.com>
7
8 * po/zh_CN.po: Updated simplified Chinese translation.
9
c2825638
MW		 102015-11-19 Matthew Wahab <matthew.wahab@arm.com>
11
12 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
13 of MSR PAN immediate operand.
14
e7286c56
NC		 152015-11-16 Nick Clifton <nickc@redhat.com>
16
17 * rx-dis.c (condition_names): Replace always and never with
18 invalid, since the always/never conditions can never be legal.
19
d8bd95ef
TG		 202015-11-13 Tristan Gingold <gingold@adacore.com>
21
22 * configure: Regenerate.
23
a680de9a
PB		 242015-11-11 Alan Modra <amodra@gmail.com>
25 Peter Bergner <bergner@vnet.ibm.com>
26
27 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
28 Add PPC_OPCODE_VSX3 to the vsx entry.
29 (powerpc_init_dialect): Set default dialect to power9.
30 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
31 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
32 extract_l1 insert_xtq6, extract_xtq6): New static functions.
33 (insert_esync): Test for illegal L operand value.
34 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
35 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
36 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
37 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
38 PPCVSX3): New defines.
39 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
40 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
41 <mcrxr>: Use XBFRARB_MASK.
42 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
43 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
44 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
45 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
46 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
47 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
48 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
49 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
50 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
51 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
52 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
53 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
54 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
55 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
56 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
57 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
58 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
59 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
60 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
61 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
62 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
63 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
64 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
65 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
66 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
67 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
68 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
69 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
70 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
71 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
72 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
73 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
74
854eb72b
NC		 752015-11-02 Nick Clifton <nickc@redhat.com>
76
77 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
78 instructions.
79 * rx-decode.c: Regenerate.
80
e292aa7a
NC		 812015-11-02 Nick Clifton <nickc@redhat.com>
82
83 * rx-decode.opc (rx_disp): If the displacement is zero, set the
84 type to RX_Operand_Zero_Indirect.
85 * rx-decode.c: Regenerate.
86 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
87
43cdf5ae
YQ		 882015-10-28 Yao Qi <yao.qi@linaro.org>
89
90 * aarch64-dis.c (aarch64_decode_insn): Add one argument
91 noaliases_p. Update comments. Pass noaliases_p rather than
92 no_aliases to aarch64_opcode_decode.
93 (print_insn_aarch64_word): Pass no_aliases to
94 aarch64_decode_insn.
95
c2f28758
VK		 962015-10-27 Vinay <Vinay.G@kpit.com>
97
98 PR binutils/19159
99 * rl78-decode.opc (MOV): Added offset to DE register in index
100 addressing mode.
101 * rl78-decode.c: Regenerate.
102
46662804
VK		 1032015-10-27 Vinay Kumar <vinay.g@kpit.com>
104
105 PR binutils/19158
106 * rl78-decode.opc: Add 's' print operator to instructions that
107 access system registers.
108 * rl78-decode.c: Regenerate.
109 * rl78-dis.c (print_insn_rl78_common): Decode all system
110 registers.
111
02f12cd4
VK		 1122015-10-27 Vinay Kumar <vinay.g@kpit.com>
113
114 PR binutils/19157
115 * rl78-decode.opc: Add 'a' print operator to mov instructions
116 using stack pointer plus index addressing.
117 * rl78-decode.c: Regenerate.
118
485f23cf
AK		 1192015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
120
121 * s390-opc.c: Fix comment.
122 * s390-opc.txt: Change instruction type for troo, trot, trto, and
123 trtt to RRF_U0RER since the second parameter does not need to be a
124 register pair.
125
3f94e60d
NC		 1262015-10-08 Nick Clifton <nickc@redhat.com>
127
128 * arc-dis.c (print_insn_arc): Initiallise insn array.
129
875880c6
YQ		 1302015-10-07 Yao Qi <yao.qi@linaro.org>
131
132 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
133 'name' rather than 'template'.
134 * aarch64-opc.c (aarch64_print_operand): Likewise.
135
886a2506
NC		 1362015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
137
138 * arc-dis.c: Revamped file for ARC support
139 * arc-dis.h: Likewise.
140 * arc-ext.c: Likewise.
141 * arc-ext.h: Likewise.
142 * arc-opc.c: Likewise.
143 * arc-fxi.h: New file.
144 * arc-regs.h: Likewise.
145 * arc-tbl.h: Likewise.
146
36f4aab1
YQ		 1472015-10-02 Yao Qi <yao.qi@linaro.org>
148
149 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
150 argument insn type to aarch64_insn. Rename to ...
151 (aarch64_decode_insn): ... it.
152 (print_insn_aarch64_word): Caller updated.
153
7232d389
YQ		 1542015-10-02 Yao Qi <yao.qi@linaro.org>
155
156 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
157 (print_insn_aarch64_word): Caller updated.
158
7ecc513a
DV		 1592015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
160
161 * s390-mkopc.c (main): Parse htm and vx flag.
162 * s390-opc.txt: Mark instructions from the hardware transactional
163 memory and vector facilities with the "htm"/"vx" flag.
164
b08b78e7
NC		 1652015-09-28 Nick Clifton <nickc@redhat.com>
166
167 * po/de.po: Updated German translation.
168
36f7a941
TR		 1692015-09-28 Tom Rix <tom@bumblecow.com>
170
171 * ppc-opc.c (PPC500): Mark some opcodes as invalid
172
b6518b38
NC		 1732015-09-23 Nick Clifton <nickc@redhat.com>
174
175 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
176 function.
177 * tic30-dis.c (print_branch): Likewise.
178 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
179 value before left shifting.
180 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
181 * hppa-dis.c (print_insn_hppa): Likewise.
182 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
183 array.
184 * msp430-dis.c (msp430_singleoperand): Likewise.
185 (msp430_doubleoperand): Likewise.
186 (print_insn_msp430): Likewise.
187 * nds32-asm.c (parse_operand): Likewise.
188 * sh-opc.h (MASK): Likewise.
189 * v850-dis.c (get_operand_value): Likewise.
190
f04265ec
NC		 1912015-09-22 Nick Clifton <nickc@redhat.com>
192
193 * rx-decode.opc (bwl): Use RX_Bad_Size.
194 (sbwl): Likewise.
195 (ubwl): Likewise. Rename to ubw.
196 (uBWL): Rename to uBW.
197 Replace all references to uBWL with uBW.
198 * rx-decode.c: Regenerate.
199 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
200 (opsize_names): Likewise.
201 (print_insn_rx): Detect and report RX_Bad_Size.
202
6dca4fd1
AB		 2032015-09-22 Anton Blanchard <anton@samba.org>
204
205 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
206
38074311
JM		 2072015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
208
209 * sparc-dis.c (print_insn_sparc): Handle the privileged register
210 %pmcdper.
211
5f40e14d
JS		 2122015-08-24 Jan Stancek <jstancek@redhat.com>
213
214 * i386-dis.c (print_insn): Fix decoding of three byte operands.
215
ab4e4ed5
AF		 2162015-08-21 Alexander Fomin <alexander.fomin@intel.com>
217
218 PR binutils/18257
219 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
220 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
221 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
222 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
223 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
224 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
225 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
226 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
227 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
228 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
229 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
230 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
231 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
232 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
233 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
234 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
235 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
236 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
237 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
238 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
239 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
240 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
241 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
242 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
243 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
244 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
245 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
246 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
247 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
248 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
249 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
250 (vex_w_table): Replace terminals with MOD_TABLE entries for
251 most of mask instructions.
252
919b75f7
AM		 2532015-08-17 Alan Modra <amodra@gmail.com>
254
255 * cgen.sh: Trim trailing space from cgen output.
256 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
257 (print_dis_table): Likewise.
258 * opc2c.c (dump_lines): Likewise.
259 (orig_filename): Warning fix.
260 * ia64-asmtab.c: Regenerate.
261
4ab90a7a
AV		 2622015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
263
264 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
265 and higher with ARM instruction set will now mark the 26-bit
266 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
267 (arm_opcodes): Fix for unpredictable nop being recognized as a
268 teq.
269
40fc1451
SD		 2702015-08-12 Simon Dardis <simon.dardis@imgtec.com>
271
272 * micromips-opc.c (micromips_opcodes): Re-order table so that move
273 based on 'or' is first.
274 * mips-opc.c (mips_builtin_opcodes): Ditto.
275
922c5db5
NC		 2762015-08-11 Nick Clifton <nickc@redhat.com>
277
278 PR 18800
279 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
280 instruction.
281
75fb7498
RS		 2822015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
283
284 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
285
36aed29d
AP		 2862015-08-07 Amit Pawar <Amit.Pawar@amd.com>
287
288 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
289 * i386-init.h: Regenerated.
290
a8484f96
L		 2912015-07-30 H.J. Lu <hongjiu.lu@intel.com>
292
293 PR binutils/13571
294 * i386-dis.c (MOD_0FC3): New.
295 (PREFIX_0FC3): Renamed to ...
296 (PREFIX_MOD_0_0FC3): This.
297 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
298 (prefix_table): Replace Ma with Ev on movntiS.
299 (mod_table): Add MOD_0FC3.
300
37a42ee9
L		 3012015-07-27 H.J. Lu <hongjiu.lu@intel.com>
302
303 * configure: Regenerated.
304
070fe95d
AM		 3052015-07-23 Alan Modra <amodra@gmail.com>
306
307 PR 18708
308 * i386-dis.c (get64): Avoid signed integer overflow.
309
20c2a615
L		 3102015-07-22 Alexander Fomin <alexander.fomin@intel.com>
311
312 PR binutils/18631
313 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
314 "EXEvexHalfBcstXmmq" for the second operand.
315 (EVEX_W_0F79_P_2): Likewise.
316 (EVEX_W_0F7A_P_2): Likewise.
317 (EVEX_W_0F7B_P_2): Likewise.
318
6f1c2142
AM		 3192015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
320
321 * arm-dis.c (print_insn_coprocessor): Added support for quarter
322 float bitfield format.
323 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
324 quarter float bitfield format.
325
8a643cc3
L		 3262015-07-14 H.J. Lu <hongjiu.lu@intel.com>
327
328 * configure: Regenerated.
329
ef5a96d5
AM		 3302015-07-03 Alan Modra <amodra@gmail.com>
331
332 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
333 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
334 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
335
c8c8175b
SL		 3362015-07-01 Sandra Loosemore <sandra@codesourcery.com>
337 Cesar Philippidis <cesar@codesourcery.com>
338
339 * nios2-dis.c (nios2_extract_opcode): New.
340 (nios2_disassembler_state): New.
341 (nios2_find_opcode_hash): Use mach parameter to select correct
342 disassembler state.
343 (nios2_print_insn_arg): Extend to support new R2 argument letters
344 and formats.
345 (print_insn_nios2): Check for 16-bit instruction at end of memory.
346 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
347 (NIOS2_NUM_OPCODES): Rename to...
348 (NIOS2_NUM_R1_OPCODES): This.
349 (nios2_r2_opcodes): New.
350 (NIOS2_NUM_R2_OPCODES): New.
351 (nios2_num_r2_opcodes): New.
352 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
353 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
354 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
355 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
356 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
357
9916071f
AP		 3582015-06-30 Amit Pawar <Amit.Pawar@amd.com>
359
360 * i386-dis.c (OP_Mwaitx): New.
361 (rm_table): Add monitorx/mwaitx.
362 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
363 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
364 (operand_type_init): Add CpuMWAITX.
365 * i386-opc.h (CpuMWAITX): New.
366 (i386_cpu_flags): Add cpumwaitx.
367 * i386-opc.tbl: Add monitorx and mwaitx.
368 * i386-init.h: Regenerated.
369 * i386-tbl.h: Likewise.
370
7b934113
PB		 3712015-06-22 Peter Bergner <bergner@vnet.ibm.com>
372
373 * ppc-opc.c (insert_ls): Test for invalid LS operands.
374 (insert_esync): New function.
375 (LS, WC): Use insert_ls.
376 (ESYNC): Use insert_esync.
377
bdc4de1b
NC		 3782015-06-22 Nick Clifton <nickc@redhat.com>
379
380 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
381 requested region lies beyond it.
382 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
383 looking for 32-bit insns.
384 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
385 data.
386 * sh-dis.c (print_insn_sh): Likewise.
387 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
388 blocks of instructions.
389 * vax-dis.c (print_insn_vax): Check that the requested address
390 does not clash with the stop_vma.
391
11a0cf2e
PB		 3922015-06-19 Peter Bergner <bergner@vnet.ibm.com>
393
070fe95d 394 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 395 * ppc-opc.c (FXM4): Add non-zero optional value.
396 (TBR): Likewise.
397 (SXL): Likewise.
398 (insert_fxm): Handle new default operand value.
399 (extract_fxm): Likewise.
400 (insert_tbr): Likewise.
401 (extract_tbr): Likewise.
402
bdfa8b95
MW		 4032015-06-16 Matthew Wahab <matthew.wahab@arm.com>
404
405 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
406
24b4cf66
SN		 4072015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
408
409 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
410
99a2c561
PB		 4112015-06-12 Peter Bergner <bergner@vnet.ibm.com>
412
413 * ppc-opc.c: Add comment accidentally removed by old commit.
414 (MTMSRD_L): Delete.
415
40f77f82
AM		 4162015-06-04 Peter Bergner <bergner@vnet.ibm.com>
417
418 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
419
13be46a2
NC		 4202015-06-04 Nick Clifton <nickc@redhat.com>
421
422 PR 18474
423 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
424
ddfded2f
MW		 4252015-06-02 Matthew Wahab <matthew.wahab@arm.com>
426
427 * arm-dis.c (arm_opcodes): Add "setpan".
428 (thumb_opcodes): Add "setpan".
429
1af1dd51
MW		 4302015-06-02 Matthew Wahab <matthew.wahab@arm.com>
431
432 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
433 macros.
434
9e1f0fa7
MW		 4352015-06-02 Matthew Wahab <matthew.wahab@arm.com>
436
437 * aarch64-tbl.h (aarch64_feature_rdma): New.
438 (RDMA): New.
439 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
440 * aarch64-asm-2.c: Regenerate.
441 * aarch64-dis-2.c: Regenerate.
442 * aarch64-opc-2.c: Regenerate.
443
290806fd
MW		 4442015-06-02 Matthew Wahab <matthew.wahab@arm.com>
445
446 * aarch64-tbl.h (aarch64_feature_lor): New.
447 (LOR): New.
448 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
449 "stllrb", "stllrh".
450 * aarch64-asm-2.c: Regenerate.
451 * aarch64-dis-2.c: Regenerate.
452 * aarch64-opc-2.c: Regenerate.
453
f21cce2c
MW		 4542015-06-01 Matthew Wahab <matthew.wahab@arm.com>
455
456 * aarch64-opc.c (F_ARCHEXT): New.
457 (aarch64_sys_regs): Add "pan".
458 (aarch64_sys_reg_supported_p): New.
459 (aarch64_pstatefields): Add "pan".
460 (aarch64_pstatefield_supported_p): New.
461
d194d186
JB		 4622015-06-01 Jan Beulich <jbeulich@suse.com>
463
464 * i386-tbl.h: Regenerate.
465
3a8547d2
JB		 4662015-06-01 Jan Beulich <jbeulich@suse.com>
467
468 * i386-dis.c (print_insn): Swap rounding mode specifier and
469 general purpose register in Intel mode.
470
015c54d5
JB		 4712015-06-01 Jan Beulich <jbeulich@suse.com>
472
473 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
474 * i386-tbl.h: Regenerate.
475
071f0063
L		 4762015-05-18 H.J. Lu <hongjiu.lu@intel.com>
477
478 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
479 * i386-init.h: Regenerated.
480
5db04b09
L		 4812015-05-15 H.J. Lu <hongjiu.lu@intel.com>
482
483 PR binutis/18386
484 * i386-dis.c: Add comments for '@'.
485 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
486 (enum x86_64_isa): New.
487 (isa64): Likewise.
488 (print_i386_disassembler_options): Add amd64 and intel64.
489 (print_insn): Handle amd64 and intel64.
490 (putop): Handle '@'.
491 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
492 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
493 * i386-opc.h (AMD64): New.
494 (CpuIntel64): Likewise.
495 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
496 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
497 Mark direct call/jmp without Disp16|Disp32 as Intel64.
498 * i386-init.h: Regenerated.
499 * i386-tbl.h: Likewise.
500
4bc0608a
PB		 5012015-05-14 Peter Bergner <bergner@vnet.ibm.com>
502
503 * ppc-opc.c (IH) New define.
504 (powerpc_opcodes) <wait>: Do not enable for POWER7.
505 <tlbie>: Add RS operand for POWER7.
506 <slbia>: Add IH operand for POWER6.
507
70cead07
L		 5082015-05-11 H.J. Lu <hongjiu.lu@intel.com>
509
510 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
511 direct branch.
512 (jmp): Likewise.
513 * i386-tbl.h: Regenerated.
514
7b6d09fb
L		 5152015-05-11 H.J. Lu <hongjiu.lu@intel.com>
516
517 * configure.ac: Support bfd_iamcu_arch.
518 * disassemble.c (disassembler): Support bfd_iamcu_arch.
519 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
520 CPU_IAMCU_COMPAT_FLAGS.
521 (cpu_flags): Add CpuIAMCU.
522 * i386-opc.h (CpuIAMCU): New.
523 (i386_cpu_flags): Add cpuiamcu.
524 * configure: Regenerated.
525 * i386-init.h: Likewise.
526 * i386-tbl.h: Likewise.
527
31955f99
L		 5282015-05-08 H.J. Lu <hongjiu.lu@intel.com>
529
530 PR binutis/18386
531 * i386-dis.c (X86_64_E8): New.
532 (X86_64_E9): Likewise.
533 Update comments on 'T', 'U', 'V'. Add comments for '^'.
534 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
535 (x86_64_table): Add X86_64_E8 and X86_64_E9.
536 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
537 (putop): Handle '^'.
538 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
539 REX_W.
540
0952813b
DD		 5412015-04-30 DJ Delorie <dj@redhat.com>
542
543 * disassemble.c (disassembler): Choose suitable disassembler based
544 on E_ABI.
545 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
546 it to decode mul/div insns.
547 * rl78-decode.c: Regenerate.
548 * rl78-dis.c (print_insn_rl78): Rename to...
549 (print_insn_rl78_common): ...this, take ISA parameter.
550 (print_insn_rl78): New.
551 (print_insn_rl78_g10): New.
552 (print_insn_rl78_g13): New.
553 (print_insn_rl78_g14): New.
554 (rl78_get_disassembler): New.
555
f9d3ecaa
NC		 5562015-04-29 Nick Clifton <nickc@redhat.com>
557
558 * po/fr.po: Updated French translation.
559
4fff86c5
PB		 5602015-04-27 Peter Bergner <bergner@vnet.ibm.com>
561
562 * ppc-opc.c (DCBT_EO): New define.
563 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
564 <lharx>: Likewise.
565 <stbcx.>: Likewise.
566 <sthcx.>: Likewise.
567 <waitrsv>: Do not enable for POWER7 and later.
568 <waitimpl>: Likewise.
569 <dcbt>: Default to the two operand form of the instruction for all
570 "old" cpus. For "new" cpus, use the operand ordering that matches
571 whether the cpu is server or embedded.
572 <dcbtst>: Likewise.
573
3b78cfe1
AK		 5742015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
575
576 * s390-opc.c: New instruction type VV0UU2.
577 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
578 and WFC.
579
04d824a4
JB		 5802015-04-23 Jan Beulich <jbeulich@suse.com>
581
582 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
583 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
584 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
585 (vfpclasspd, vfpclassps): Add %XZ.
586
09708981
L		 5872015-04-15 H.J. Lu <hongjiu.lu@intel.com>
588
589 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
590 (PREFIX_UD_REPZ): Likewise.
591 (PREFIX_UD_REPNZ): Likewise.
592 (PREFIX_UD_DATA): Likewise.
593 (PREFIX_UD_ADDR): Likewise.
594 (PREFIX_UD_LOCK): Likewise.
595
3888916d
L		 5962015-04-15 H.J. Lu <hongjiu.lu@intel.com>
597
598 * i386-dis.c (prefix_requirement): Removed.
599 (print_insn): Don't set prefix_requirement. Check
600 dp->prefix_requirement instead of prefix_requirement.
601
f24bcbaa
L		 6022015-04-15 H.J. Lu <hongjiu.lu@intel.com>
603
604 PR binutils/17898
605 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
606 (PREFIX_MOD_0_0FC7_REG_6): This.
607 (PREFIX_MOD_3_0FC7_REG_6): New.
608 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
609 (prefix_table): Replace PREFIX_0FC7_REG_6 with
610 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
611 PREFIX_MOD_3_0FC7_REG_7.
612 (mod_table): Replace PREFIX_0FC7_REG_6 with
613 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
614 PREFIX_MOD_3_0FC7_REG_7.
615
507bd325
L		 6162015-04-15 H.J. Lu <hongjiu.lu@intel.com>
617
618 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
619 (PREFIX_MANDATORY_REPNZ): Likewise.
620 (PREFIX_MANDATORY_DATA): Likewise.
621 (PREFIX_MANDATORY_ADDR): Likewise.
622 (PREFIX_MANDATORY_LOCK): Likewise.
623 (PREFIX_MANDATORY): Likewise.
624 (PREFIX_UD_SHIFT): Set to 8
625 (PREFIX_UD_REPZ): Updated.
626 (PREFIX_UD_REPNZ): Likewise.
627 (PREFIX_UD_DATA): Likewise.
628 (PREFIX_UD_ADDR): Likewise.
629 (PREFIX_UD_LOCK): Likewise.
630 (PREFIX_IGNORED_SHIFT): New.
631 (PREFIX_IGNORED_REPZ): Likewise.
632 (PREFIX_IGNORED_REPNZ): Likewise.
633 (PREFIX_IGNORED_DATA): Likewise.
634 (PREFIX_IGNORED_ADDR): Likewise.
635 (PREFIX_IGNORED_LOCK): Likewise.
636 (PREFIX_OPCODE): Likewise.
637 (PREFIX_IGNORED): Likewise.
638 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
639 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
640 (three_byte_table): Likewise.
641 (mod_table): Likewise.
642 (mandatory_prefix): Renamed to ...
643 (prefix_requirement): This.
644 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
645 Update PREFIX_90 entry.
646 (get_valid_dis386): Check prefix_requirement to see if a prefix
647 should be ignored.
648 (print_insn): Replace mandatory_prefix with prefix_requirement.
649
f0fba320
RL		 6502015-04-15 Renlin Li <renlin.li@arm.com>
651
652 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
653 use it for ssat and ssat16.
654 (print_insn_thumb32): Add handle case for 'D' control code.
655
bf890a93
IT		 6562015-04-06 Ilya Tocar <ilya.tocar@intel.com>
657 H.J. Lu <hongjiu.lu@intel.com>
658
659 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
660 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
661 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
662 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
663 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
664 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
665 Fill prefix_requirement field.
666 (struct dis386): Add prefix_requirement field.
667 (dis386): Fill prefix_requirement field.
668 (dis386_twobyte): Ditto.
669 (twobyte_has_mandatory_prefix_: Remove.
670 (reg_table): Fill prefix_requirement field.
671 (prefix_table): Ditto.
672 (x86_64_table): Ditto.
673 (three_byte_table): Ditto.
674 (xop_table): Ditto.
675 (vex_table): Ditto.
676 (vex_len_table): Ditto.
677 (vex_w_table): Ditto.
678 (mod_table): Ditto.
679 (bad_opcode): Ditto.
680 (print_insn): Use prefix_requirement.
681 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
682 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
683 (float_reg): Ditto.
684
2f783c1f
MF		 6852015-03-30 Mike Frysinger <vapier@gentoo.org>
686
687 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
688
b9d94d62
L		 6892015-03-29 H.J. Lu <hongjiu.lu@intel.com>
690
691 * Makefile.in: Regenerated.
692
27c49e9a
AB		 6932015-03-25 Anton Blanchard <anton@samba.org>
694
695 * ppc-dis.c (disassemble_init_powerpc): Only initialise
696 powerpc_opcd_indices and vle_opcd_indices once.
697
c4e676f1
AB		 6982015-03-25 Anton Blanchard <anton@samba.org>
699
700 * ppc-opc.c (powerpc_opcodes): Add slbfee.
701
823d2571
TG		 7022015-03-24 Terry Guo <terry.guo@arm.com>
703
704 * arm-dis.c (opcode32): Updated to use new arm feature struct.
705 (opcode16): Likewise.
706 (coprocessor_opcodes): Replace bit with feature struct.
707 (neon_opcodes): Likewise.
708 (arm_opcodes): Likewise.
709 (thumb_opcodes): Likewise.
710 (thumb32_opcodes): Likewise.
711 (print_insn_coprocessor): Likewise.
712 (print_insn_arm): Likewise.
713 (select_arm_features): Follow new feature struct.
714
029f3522
GG		 7152015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
716
717 * i386-dis.c (rm_table): Add clzero.
718 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
719 Add CPU_CLZERO_FLAGS.
720 (cpu_flags): Add CpuCLZERO.
721 * i386-opc.h: Add CpuCLZERO.
722 * i386-opc.tbl: Add clzero.
723 * i386-init.h: Re-generated.
724 * i386-tbl.h: Re-generated.
725
6914869a
AB		 7262015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
727
728 * mips-opc.c (decode_mips_operand): Fix constraint issues
729 with u and y operands.
730
21e20815
AB		 7312015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
732
733 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
734
6b1d7593
AK		 7352015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
736
737 * s390-opc.c: Add new IBM z13 instructions.
738 * s390-opc.txt: Likewise.
739
c8f89a34
JW		 7402015-03-10 Renlin Li <renlin.li@arm.com>
741
742 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
743 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
744 related alias.
745 * aarch64-asm-2.c: Regenerate.
746 * aarch64-dis-2.c: Likewise.
747 * aarch64-opc-2.c: Likewise.
748
d8282f0e
JW		 7492015-03-03 Jiong Wang <jiong.wang@arm.com>
750
751 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
752
ac994365
OE		 7532015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
754
755 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
756 arch_sh_up.
757 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
758 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
759
fd63f640
V		 7602015-02-23 Vinay <Vinay.G@kpit.com>
761
762 * rl78-decode.opc (MOV): Added space between two operands for
763 'mov' instruction in index addressing mode.
764 * rl78-decode.c: Regenerate.
765
f63c1776
PA		 7662015-02-19 Pedro Alves <palves@redhat.com>
767
768 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
769
07774fcc
PA		 7702015-02-10 Pedro Alves <palves@redhat.com>
771 Tom Tromey <tromey@redhat.com>
772
773 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
774 microblaze_and, microblaze_xor.
775 * microblaze-opc.h (opcodes): Adjust.
776
3f8107ab
AM		 7772015-01-28 James Bowman <james.bowman@ftdichip.com>
778
779 * Makefile.am: Add FT32 files.
780 * configure.ac: Handle FT32.
781 * disassemble.c (disassembler): Call print_insn_ft32.
782 * ft32-dis.c: New file.
783 * ft32-opc.c: New file.
784 * Makefile.in: Regenerate.
785 * configure: Regenerate.
786 * po/POTFILES.in: Regenerate.
787
e5fe4957
KLC		 7882015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
789
790 * nds32-asm.c (keyword_sr): Add new system registers.
791
1e2e8c52
AK		 7922015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
793
794 * s390-dis.c (s390_extract_operand): Support vector register
795 operands.
796 (s390_print_insn_with_opcode): Support new operands types and add
797 new handling of optional operands.
798 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
799 and include opcode/s390.h instead.
800 (struct op_struct): New field `flags'.
801 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
802 (dumpTable): Dump flags.
803 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
804 string.
805 * s390-opc.c: Add new operands types, instruction formats, and
806 instruction masks.
807 (s390_opformats): Add new formats for .insn.
808 * s390-opc.txt: Add new instructions.
809
b90efa5b 8102015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 811
b90efa5b 812 Update year range in copyright notice of all files.
bffb6004 813
b90efa5b 814For older changes see ChangeLog-2014
252b5132 815\f
b90efa5b 816Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 817
818Copying and distribution of this file, with or without modification,
819are permitted in any medium without royalty provided the copyright
820notice and this notice are preserved.
821
252b5132 822Local Variables:
2f6d2f85
NC		 823mode: change-log
824left-margin: 8
825fill-column: 74
252b5132
RH		 826version-control: never
827End:
GDB Binutils - Deliverables
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