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ubsan: moxie: left shift of negative value
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
8c9b4171
AM		 12019-12-11 Alan Modra <amodra@gmail.com>
2
3 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
4
334175b6
AM		 52019-12-11 Alan Modra <amodra@gmail.com>
6
7 * m68k-dis.c (COERCE32): Cast value first.
8 (NEXTLONG, NEXTULONG): Avoid signed overflow.
9
f8a87c78
AM		 102019-12-11 Alan Modra <amodra@gmail.com>
11
12 * h8300-dis.c (extract_immediate): Avoid signed overflow.
13 (bfd_h8_disassemble): Likewise.
14
159653d8
AM		 152019-12-11 Alan Modra <amodra@gmail.com>
16
17 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
18 past end of operands array.
19
d93bba9e
AM		 202019-12-11 Alan Modra <amodra@gmail.com>
21
22 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
23 overflow when collecting bytes of a number.
24
c202f69e
AM		 252019-12-11 Alan Modra <amodra@gmail.com>
26
27 * cris-dis.c (print_with_operands): Avoid signed integer
28 overflow when collecting bytes of a 32-bit integer.
29
0ef562a4
AM		 302019-12-11 Alan Modra <amodra@gmail.com>
31
32 * cr16-dis.c (EXTRACT, SBM): Rewrite.
33 (cr16_match_opcode): Delete duplicate bcond test.
34
2fd2b153
AM		 352019-12-11 Alan Modra <amodra@gmail.com>
36
37 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
38 (SIGNBIT): New.
39 (MASKBITS, SIGNEXTEND): Rewrite.
40 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
41 unsigned arithmetic, instead assign result of SIGNEXTEND back
42 to x.
43 (fmtconst_val): Use 1u in shift expression.
44
a11db3e9
AM		 452019-12-11 Alan Modra <amodra@gmail.com>
46
47 * arc-dis.c (find_format_from_table): Use ull constant when
48 shifting by up to 32.
49
9d48687b
AM		 502019-12-11 Alan Modra <amodra@gmail.com>
51
52 PR 25270
53 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
54 false when field is zero for sve_size_tsz_bhs.
55
b8e61daa
AM		 562019-12-11 Alan Modra <amodra@gmail.com>
57
58 * epiphany-ibld.c: Regenerate.
59
20135676
AM		 602019-12-10 Alan Modra <amodra@gmail.com>
61
62 PR 24960
63 * disassemble.c (disassemble_free_target): New function.
64
103ebbc3
AM		 652019-12-10 Alan Modra <amodra@gmail.com>
66
67 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
68 * disassemble.c (disassemble_init_for_target): Likewise.
69 * bpf-dis.c: Regenerate.
70 * epiphany-dis.c: Regenerate.
71 * fr30-dis.c: Regenerate.
72 * frv-dis.c: Regenerate.
73 * ip2k-dis.c: Regenerate.
74 * iq2000-dis.c: Regenerate.
75 * lm32-dis.c: Regenerate.
76 * m32c-dis.c: Regenerate.
77 * m32r-dis.c: Regenerate.
78 * mep-dis.c: Regenerate.
79 * mt-dis.c: Regenerate.
80 * or1k-dis.c: Regenerate.
81 * xc16x-dis.c: Regenerate.
82 * xstormy16-dis.c: Regenerate.
83
6f0e0752
AM		 842019-12-10 Alan Modra <amodra@gmail.com>
85
86 * ppc-dis.c (private): Delete variable.
87 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
88 (powerpc_init_dialect): Don't use global private.
89
e7c22a69
AM		 902019-12-10 Alan Modra <amodra@gmail.com>
91
92 * s12z-opc.c: Formatting.
93
0a6aef6b
AM		 942019-12-08 Alan Modra <amodra@gmail.com>
95
96 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
97 registers.
98
2dc4b12f
JB		 992019-12-05 Jan Beulich <jbeulich@suse.com>
100
101 * aarch64-tbl.h (aarch64_feature_crypto,
102 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
103 CRYPTO_V8_2_INSN): Delete.
104
378fd436
AM		 1052019-12-05 Alan Modra <amodra@gmail.com>
106
107 PR 25249
108 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
109 (struct string_buf): New.
110 (strbuf): New function.
111 (get_field): Use strbuf rather than strdup of local temp.
112 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
113 (get_field_rfsl, get_field_imm15): Likewise.
114 (get_field_rd, get_field_r1, get_field_r2): Update macros.
115 (get_field_special): Likewise. Don't strcpy spr. Formatting.
116 (print_insn_microblaze): Formatting. Init and pass string_buf to
117 get_field functions.
118
0ba59a29
JB		 1192019-12-04 Jan Beulich <jbeulich@suse.com>
120
121 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
122 * i386-tbl.h: Re-generate.
123
77ad8092
JB		 1242019-12-04 Jan Beulich <jbeulich@suse.com>
125
126 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
127
3036c899
JB		 1282019-12-04 Jan Beulich <jbeulich@suse.com>
129
130 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
131 forms.
132 (xbegin): Drop DefaultSize.
133 * i386-tbl.h: Re-generate.
134
8b301fbb
MI		 1352019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
136
137 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
138 Change the coproc CRC conditions to use the extension
139 feature set, second word, base on ARM_EXT2_CRC.
140
6aa385b9
JB		 1412019-11-14 Jan Beulich <jbeulich@suse.com>
142
143 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
144 * i386-tbl.h: Re-generate.
145
0cfa3eb3
JB		 1462019-11-14 Jan Beulich <jbeulich@suse.com>
147
148 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
149 JumpInterSegment, and JumpAbsolute entries.
150 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
151 JUMP_ABSOLUTE): Define.
152 (struct i386_opcode_modifier): Extend jump field to 3 bits.
153 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
154 fields.
155 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
156 JumpInterSegment): Define.
157 * i386-tbl.h: Re-generate.
158
6f2f06be
JB		 1592019-11-14 Jan Beulich <jbeulich@suse.com>
160
161 * i386-gen.c (operand_type_init): Remove
162 OPERAND_TYPE_JUMPABSOLUTE entry.
163 (opcode_modifiers): Add JumpAbsolute entry.
164 (operand_types): Remove JumpAbsolute entry.
165 * i386-opc.h (JumpAbsolute): Move between enums.
166 (struct i386_opcode_modifier): Add jumpabsolute field.
167 (union i386_operand_type): Remove jumpabsolute field.
168 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
169 * i386-init.h, i386-tbl.h: Re-generate.
170
601e8564
JB		 1712019-11-14 Jan Beulich <jbeulich@suse.com>
172
173 * i386-gen.c (opcode_modifiers): Add AnySize entry.
174 (operand_types): Remove AnySize entry.
175 * i386-opc.h (AnySize): Move between enums.
176 (struct i386_opcode_modifier): Add anysize field.
177 (OTUnused): Un-comment.
178 (union i386_operand_type): Remove anysize field.
179 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
180 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
181 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
182 AnySize.
183 * i386-tbl.h: Re-generate.
184
7722d40a
JW		 1852019-11-12 Nelson Chu <nelson.chu@sifive.com>
186
187 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
188 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
189 use the floating point register (FPR).
190
ce760a76
MI		 1912019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
192
193 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
194 cmode 1101.
195 (is_mve_encoding_conflict): Update cmode conflict checks for
196 MVE_VMVN_IMM.
197
51c8edf6
JB		 1982019-11-12 Jan Beulich <jbeulich@suse.com>
199
200 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
201 entry.
202 (operand_types): Remove EsSeg entry.
203 (main): Replace stale use of OTMax.
204 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
205 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
206 (EsSeg): Delete.
207 (OTUnused): Comment out.
208 (union i386_operand_type): Remove esseg field.
209 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
210 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
211 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
212 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
213 * i386-init.h, i386-tbl.h: Re-generate.
214
474da251
JB		 2152019-11-12 Jan Beulich <jbeulich@suse.com>
216
217 * i386-gen.c (operand_instances): Add RegB entry.
218 * i386-opc.h (enum operand_instance): Add RegB.
219 * i386-opc.tbl (RegC, RegD, RegB): Define.
220 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
221 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
222 monitorx, mwaitx): Drop ImmExt and convert encodings
223 accordingly.
224 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
225 (edx, rdx): Add Instance=RegD.
226 (ebx, rbx): Add Instance=RegB.
227 * i386-tbl.h: Re-generate.
228
75e5731b
JB		 2292019-11-12 Jan Beulich <jbeulich@suse.com>
230
231 * i386-gen.c (operand_type_init): Adjust
232 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
233 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
234 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
235 (operand_instances): New.
236 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
237 (output_operand_type): New parameter "instance". Process it.
238 (process_i386_operand_type): New local variable "instance".
239 (main): Adjust static assertions.
240 * i386-opc.h (INSTANCE_WIDTH): Define.
241 (enum operand_instance): New.
242 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
243 (union i386_operand_type): Replace acc, inoutportreg, and
244 shiftcount by instance.
245 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
246 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
247 Add Instance=.
248 * i386-init.h, i386-tbl.h: Re-generate.
249
91802f3c
JB		 2502019-11-11 Jan Beulich <jbeulich@suse.com>
251
252 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
253 smaxp/sminp entries' "tied_operand" field to 2.
254
4f5fc85d
JB		 2552019-11-11 Jan Beulich <jbeulich@suse.com>
256
257 * aarch64-opc.c (operand_general_constraint_met_p): Replace
258 "index" local variable by that of the already existing "num".
259
dc2be329
L		 2602019-11-08 H.J. Lu <hongjiu.lu@intel.com>
261
262 PR gas/25167
263 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
264 * i386-tbl.h: Regenerated.
265
f74a6307
JB		 2662019-11-08 Jan Beulich <jbeulich@suse.com>
267
268 * i386-gen.c (operand_type_init): Add Class= to
269 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
270 OPERAND_TYPE_REGBND entry.
271 (operand_classes): Add RegMask and RegBND entries.
272 (operand_types): Drop RegMask and RegBND entry.
273 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
274 (RegMask, RegBND): Delete.
275 (union i386_operand_type): Remove regmask and regbnd fields.
276 * i386-opc.tbl (RegMask, RegBND): Define.
277 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
278 Class=RegBND.
279 * i386-init.h, i386-tbl.h: Re-generate.
280
3528c362
JB		 2812019-11-08 Jan Beulich <jbeulich@suse.com>
282
283 * i386-gen.c (operand_type_init): Add Class= to
284 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
285 OPERAND_TYPE_REGZMM entries.
286 (operand_classes): Add RegMMX and RegSIMD entries.
287 (operand_types): Drop RegMMX and RegSIMD entries.
288 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
289 (RegMMX, RegSIMD): Delete.
290 (union i386_operand_type): Remove regmmx and regsimd fields.
291 * i386-opc.tbl (RegMMX): Define.
292 (RegXMM, RegYMM, RegZMM): Add Class=.
293 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
294 Class=RegSIMD.
295 * i386-init.h, i386-tbl.h: Re-generate.
296
4a5c67ed
JB		 2972019-11-08 Jan Beulich <jbeulich@suse.com>
298
299 * i386-gen.c (operand_type_init): Add Class= to
300 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
301 entries.
302 (operand_classes): Add RegCR, RegDR, and RegTR entries.
303 (operand_types): Drop Control, Debug, and Test entries.
304 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
305 (Control, Debug, Test): Delete.
306 (union i386_operand_type): Remove control, debug, and test
307 fields.
308 * i386-opc.tbl (Control, Debug, Test): Define.
309 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
310 Class=RegDR, and Test by Class=RegTR.
311 * i386-init.h, i386-tbl.h: Re-generate.
312
00cee14f
JB		 3132019-11-08 Jan Beulich <jbeulich@suse.com>
314
315 * i386-gen.c (operand_type_init): Add Class= to
316 OPERAND_TYPE_SREG entry.
317 (operand_classes): Add SReg entry.
318 (operand_types): Drop SReg entry.
319 * i386-opc.h (enum operand_class): Add SReg.
320 (SReg): Delete.
321 (union i386_operand_type): Remove sreg field.
322 * i386-opc.tbl (SReg): Define.
323 * i386-reg.tbl: Replace SReg by Class=SReg.
324 * i386-init.h, i386-tbl.h: Re-generate.
325
bab6aec1
JB		 3262019-11-08 Jan Beulich <jbeulich@suse.com>
327
328 * i386-gen.c (operand_type_init): Add Class=. New
329 OPERAND_TYPE_ANYIMM entry.
330 (operand_classes): New.
331 (operand_types): Drop Reg entry.
332 (output_operand_type): New parameter "class". Process it.
333 (process_i386_operand_type): New local variable "class".
334 (main): Adjust static assertions.
335 * i386-opc.h (CLASS_WIDTH): Define.
336 (enum operand_class): New.
337 (Reg): Replace by Class. Adjust comment.
338 (union i386_operand_type): Replace reg by class.
339 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
340 Class=.
341 * i386-reg.tbl: Replace Reg by Class=Reg.
342 * i386-init.h: Re-generate.
343
1f4cd317
MM		 3442019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
345
346 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
347 (aarch64_opcode_table): Add data gathering hint mnemonic.
348 * opcodes/aarch64-dis-2.c: Account for new instruction.
349
616ce08e
MM		 3502019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
351
352 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
353
354
8382113f
MM		 3552019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
356
357 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
358 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
359 aarch64_feature_f64mm): New feature sets.
360 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
361 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
362 instructions.
363 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
364 macros.
365 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
366 (OP_SVE_QQQ): New qualifier.
367 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
368 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
369 the movprfx constraint.
370 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
371 (aarch64_opcode_table): Define new instructions smmla,
372 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
373 uzip{1/2}, trn{1/2}.
374 * aarch64-opc.c (operand_general_constraint_met_p): Handle
375 AARCH64_OPND_SVE_ADDR_RI_S4x32.
376 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
377 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
378 Account for new instructions.
379 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
380 S4x32 operand.
381 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
382
aab2c27d
MM		 3832019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3842019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
385
386 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
387 Armv8.6-A.
388 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
389 (neon_opcodes): Add bfloat SIMD instructions.
390 (print_insn_coprocessor): Add new control character %b to print
391 condition code without checking cp_num.
392 (print_insn_neon): Account for BFloat16 instructions that have no
393 special top-byte handling.
394
33593eaf
MM		 3952019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3962019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
397
398 * arm-dis.c (print_insn_coprocessor,
399 print_insn_generic_coprocessor): Create wrapper functions around
400 the implementation of the print_insn_coprocessor control codes.
401 (print_insn_coprocessor_1): Original print_insn_coprocessor
402 function that now takes which array to look at as an argument.
403 (print_insn_arm): Use both print_insn_coprocessor and
404 print_insn_generic_coprocessor.
405 (print_insn_thumb32): As above.
406
df678013
MM		 4072019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4082019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
409
410 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
411 in reglane special case.
412 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
413 aarch64_find_next_opcode): Account for new instructions.
414 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
415 in reglane special case.
416 * aarch64-opc.c (struct operand_qualifier_data): Add data for
417 new AARCH64_OPND_QLF_S_2H qualifier.
418 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
419 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
420 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
421 sets.
422 (BFLOAT_SVE, BFLOAT): New feature set macros.
423 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
424 instructions.
425 (aarch64_opcode_table): Define new instructions bfdot,
426 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
427 bfcvtn2, bfcvt.
428
8ae2d3d9
MM		 4292019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4302019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
431
432 * aarch64-tbl.h (ARMV8_6): New macro.
433
142861df
JB		 4342019-11-07 Jan Beulich <jbeulich@suse.com>
435
436 * i386-dis.c (prefix_table): Add mcommit.
437 (rm_table): Add rdpru.
438 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
439 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
440 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
441 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
442 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
443 * i386-opc.tbl (mcommit, rdpru): New.
444 * i386-init.h, i386-tbl.h: Re-generate.
445
081e283f
JB		 4462019-11-07 Jan Beulich <jbeulich@suse.com>
447
448 * i386-dis.c (OP_Mwait): Drop local variable "names", use
449 "names32" instead.
450 (OP_Monitor): Drop local variable "op1_names", re-purpose
451 "names" for it instead, and replace former "names" uses by
452 "names32" ones.
453
c050c89a
JB		 4542019-11-07 Jan Beulich <jbeulich@suse.com>
455
456 PR/gas 25167
457 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
458 operand-less forms.
459 * opcodes/i386-tbl.h: Re-generate.
460
7abb8d81
JB		 4612019-11-05 Jan Beulich <jbeulich@suse.com>
462
463 * i386-dis.c (OP_Mwaitx): Delete.
464 (prefix_table): Use OP_Mwait for mwaitx entry.
465 (OP_Mwait): Also handle mwaitx.
466
267b8516
JB		 4672019-11-05 Jan Beulich <jbeulich@suse.com>
468
469 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
470 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
471 (prefix_table): Add respective entries.
472 (rm_table): Link to those entries.
473
f8687e93
JB		 4742019-11-05 Jan Beulich <jbeulich@suse.com>
475
476 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
477 (REG_0F1C_P_0_MOD_0): ... this.
478 (REG_0F1E_MOD_3): Rename to ...
479 (REG_0F1E_P_1_MOD_3): ... this.
480 (RM_0F01_REG_5): Rename to ...
481 (RM_0F01_REG_5_MOD_3): ... this.
482 (RM_0F01_REG_7): Rename to ...
483 (RM_0F01_REG_7_MOD_3): ... this.
484 (RM_0F1E_MOD_3_REG_7): Rename to ...
485 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
486 (RM_0FAE_REG_6): Rename to ...
487 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
488 (RM_0FAE_REG_7): Rename to ...
489 (RM_0FAE_REG_7_MOD_3): ... this.
490 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
491 (PREFIX_0F01_REG_5_MOD_0): ... this.
492 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
493 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
494 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
495 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
496 (PREFIX_0FAE_REG_0): Rename to ...
497 (PREFIX_0FAE_REG_0_MOD_3): ... this.
498 (PREFIX_0FAE_REG_1): Rename to ...
499 (PREFIX_0FAE_REG_1_MOD_3): ... this.
500 (PREFIX_0FAE_REG_2): Rename to ...
501 (PREFIX_0FAE_REG_2_MOD_3): ... this.
502 (PREFIX_0FAE_REG_3): Rename to ...
503 (PREFIX_0FAE_REG_3_MOD_3): ... this.
504 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
505 (PREFIX_0FAE_REG_4_MOD_0): ... this.
506 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
507 (PREFIX_0FAE_REG_4_MOD_3): ... this.
508 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
509 (PREFIX_0FAE_REG_5_MOD_0): ... this.
510 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
511 (PREFIX_0FAE_REG_5_MOD_3): ... this.
512 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
513 (PREFIX_0FAE_REG_6_MOD_0): ... this.
514 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
515 (PREFIX_0FAE_REG_6_MOD_3): ... this.
516 (PREFIX_0FAE_REG_7): Rename to ...
517 (PREFIX_0FAE_REG_7_MOD_0): ... this.
518 (PREFIX_MOD_0_0FC3): Rename to ...
519 (PREFIX_0FC3_MOD_0): ... this.
520 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
521 (PREFIX_0FC7_REG_6_MOD_0): ... this.
522 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
523 (PREFIX_0FC7_REG_6_MOD_3): ... this.
524 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
525 (PREFIX_0FC7_REG_7_MOD_3): ... this.
526 (reg_table, prefix_table, mod_table, rm_table): Adjust
527 accordingly.
528
5103274f
NC		 5292019-11-04 Nick Clifton <nickc@redhat.com>
530
531 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
532 of a v850 system register. Move the v850_sreg_names array into
533 this function.
534 (get_v850_reg_name): Likewise for ordinary register names.
535 (get_v850_vreg_name): Likewise for vector register names.
536 (get_v850_cc_name): Likewise for condition codes.
537 * get_v850_float_cc_name): Likewise for floating point condition
538 codes.
539 (get_v850_cacheop_name): Likewise for cache-ops.
540 (get_v850_prefop_name): Likewise for pref-ops.
541 (disassemble): Use the new accessor functions.
542
1820262b
DB		 5432019-10-30 Delia Burduv <delia.burduv@arm.com>
544
545 * aarch64-opc.c (print_immediate_offset_address): Don't print the
546 immediate for the writeback form of ldraa/ldrab if it is 0.
547 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
548 * aarch64-opc-2.c: Regenerated.
549
3cc17af5
JB		 5502019-10-30 Jan Beulich <jbeulich@suse.com>
551
552 * i386-gen.c (operand_type_shorthands): Delete.
553 (operand_type_init): Expand previous shorthands.
554 (set_bitfield_from_shorthand): Rename back to ...
555 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
556 of operand_type_init[].
557 (set_bitfield): Adjust call to the above function.
558 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
559 RegXMM, RegYMM, RegZMM): Define.
560 * i386-reg.tbl: Expand prior shorthands.
561
a2cebd03
JB		 5622019-10-30 Jan Beulich <jbeulich@suse.com>
563
564 * i386-gen.c (output_i386_opcode): Change order of fields
565 emitted to output.
566 * i386-opc.h (struct insn_template): Move operands field.
567 Convert extension_opcode field to unsigned short.
568 * i386-tbl.h: Re-generate.
569
507916b8
JB		 5702019-10-30 Jan Beulich <jbeulich@suse.com>
571
572 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
573 of W.
574 * i386-opc.h (W): Extend comment.
575 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
576 general purpose variants not allowing for byte operands.
577 * i386-tbl.h: Re-generate.
578
efea62b4
NC		 5792019-10-29 Nick Clifton <nickc@redhat.com>
580
581 * tic30-dis.c (print_branch): Correct size of operand array.
582
9adb2591
NC		 5832019-10-29 Nick Clifton <nickc@redhat.com>
584
585 * d30v-dis.c (print_insn): Check that operand index is valid
586 before attempting to access the operands array.
587
993a00a9
NC		 5882019-10-29 Nick Clifton <nickc@redhat.com>
589
590 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
591 locating the bit to be tested.
592
66a66a17
NC		 5932019-10-29 Nick Clifton <nickc@redhat.com>
594
595 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
596 values.
597 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
598 (print_insn_s12z): Check for illegal size values.
599
1ee3542c
NC		 6002019-10-28 Nick Clifton <nickc@redhat.com>
601
602 * csky-dis.c (csky_chars_to_number): Check for a negative
603 count. Use an unsigned integer to construct the return value.
604
bbf9a0b5
NC		 6052019-10-28 Nick Clifton <nickc@redhat.com>
606
607 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
608 operand buffer. Set value to 15 not 13.
609 (get_register_operand): Use OPERAND_BUFFER_LEN.
610 (get_indirect_operand): Likewise.
611 (print_two_operand): Likewise.
612 (print_three_operand): Likewise.
613 (print_oar_insn): Likewise.
614
d1e304bc
NC		 6152019-10-28 Nick Clifton <nickc@redhat.com>
616
617 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
618 (bit_extract_simple): Likewise.
619 (bit_copy): Likewise.
620 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
621 index_offset array are not accessed.
622
dee33451
NC		 6232019-10-28 Nick Clifton <nickc@redhat.com>
624
625 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
626 operand.
627
27cee81d
NC		 6282019-10-25 Nick Clifton <nickc@redhat.com>
629
630 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
631 access to opcodes.op array element.
632
de6d8dc2
NC		 6332019-10-23 Nick Clifton <nickc@redhat.com>
634
635 * rx-dis.c (get_register_name): Fix spelling typo in error
636 message.
637 (get_condition_name, get_flag_name, get_double_register_name)
638 (get_double_register_high_name, get_double_register_low_name)
639 (get_double_control_register_name, get_double_condition_name)
640 (get_opsize_name, get_size_name): Likewise.
641
6207ed28
NC		 6422019-10-22 Nick Clifton <nickc@redhat.com>
643
644 * rx-dis.c (get_size_name): New function. Provides safe
645 access to name array.
646 (get_opsize_name): Likewise.
647 (print_insn_rx): Use the accessor functions.
648
12234dfd
NC		 6492019-10-16 Nick Clifton <nickc@redhat.com>
650
651 * rx-dis.c (get_register_name): New function. Provides safe
652 access to name array.
653 (get_condition_name, get_flag_name, get_double_register_name)
654 (get_double_register_high_name, get_double_register_low_name)
655 (get_double_control_register_name, get_double_condition_name):
656 Likewise.
657 (print_insn_rx): Use the accessor functions.
658
1d378749
NC		 6592019-10-09 Nick Clifton <nickc@redhat.com>
660
661 PR 25041
662 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
663 instructions.
664
d241b910
JB		 6652019-10-07 Jan Beulich <jbeulich@suse.com>
666
667 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
668 (cmpsd): Likewise. Move EsSeg to other operand.
669 * opcodes/i386-tbl.h: Re-generate.
670
f5c5b7c1
AM		 6712019-09-23 Alan Modra <amodra@gmail.com>
672
673 * m68k-dis.c: Include cpu-m68k.h
674
7beeaeb8
AM		 6752019-09-23 Alan Modra <amodra@gmail.com>
676
677 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
678 "elf/mips.h" earlier.
679
3f9aad11
JB		 6802018-09-20 Jan Beulich <jbeulich@suse.com>
681
682 PR gas/25012
683 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
684 with SReg operand.
685 * i386-tbl.h: Re-generate.
686
fd361982
AM		 6872019-09-18 Alan Modra <amodra@gmail.com>
688
689 * arc-ext.c: Update throughout for bfd section macro changes.
690
e0b2a78c
SM		 6912019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
692
693 * Makefile.in: Re-generate.
694 * configure: Re-generate.
695
7e9ad3a3
JW		 6962019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
697
698 * riscv-opc.c (riscv_opcodes): Change subset field
699 to insn_class field for all instructions.
700 (riscv_insn_types): Likewise.
701
bb695960
PB		 7022019-09-16 Phil Blundell <pb@pbcl.net>
703
704 * configure: Regenerated.
705
8063ab7e
MV		 7062019-09-10 Miod Vallat <miod@online.fr>
707
708 PR 24982
709 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
710
60391a25
PB		 7112019-09-09 Phil Blundell <pb@pbcl.net>
712
713 binutils 2.33 branch created.
714
f44b758d
NC		 7152019-09-03 Nick Clifton <nickc@redhat.com>
716
717 PR 24961
718 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
719 greater than zero before indexing via (bufcnt -1).
720
1e4b5e7d
NC		 7212019-09-03 Nick Clifton <nickc@redhat.com>
722
723 PR 24958
724 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
725 (MAX_SPEC_REG_NAME_LEN): Define.
726 (struct mmix_dis_info): Use defined constants for array lengths.
727 (get_reg_name): New function.
728 (get_sprec_reg_name): New function.
729 (print_insn_mmix): Use new functions.
730
c4a23bf8
SP		 7312019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
732
733 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
734 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
735 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
736
a051e2f3
KT		 7372019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
738
739 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
740 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
741 (aarch64_sys_reg_supported_p): Update checks for the above.
742
08132bdd
SP		 7432019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
744
745 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
746 cases MVE_SQRSHRL and MVE_UQRSHLL.
747 (print_insn_mve): Add case for specifier 'k' to check
748 specific bit of the instruction.
749
d88bdcb4
PA		 7502019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
751
752 PR 24854
753 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
754 encountering an unknown machine type.
755 (print_insn_arc): Handle arc_insn_length returning 0. In error
756 cases return -1 rather than calling abort.
757
bc750500
JB		 7582019-08-07 Jan Beulich <jbeulich@suse.com>
759
760 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
761 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
762 IgnoreSize.
763 * i386-tbl.h: Re-generate.
764
23d188c7
BW		 7652019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
766
767 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
768 instructions.
769
c0d6f62f
JW		 7702019-07-30 Mel Chen <mel.chen@sifive.com>
771
772 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
773 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
774
775 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
776 fscsr.
777
0f3f7167
CZ		 7782019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
779
780 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
781 and MPY class instructions.
782 (parse_option): Add nps400 option.
783 (print_arc_disassembler_options): Add nps400 info.
784
7e126ba3
CZ		 7852019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
786
787 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
788 (bspop): Likewise.
789 (modapp): Likewise.
790 * arc-opc.c (RAD_CHK): Add.
791 * arc-tbl.h: Regenerate.
792
a028026d
KT		 7932019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
794
795 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
796 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
797
ac79ff9e
NC		 7982019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
799
800 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
801 instructions as UNPREDICTABLE.
802
231097b0
JM		 8032019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
804
805 * bpf-desc.c: Regenerated.
806
1d942ae9
JB		 8072019-07-17 Jan Beulich <jbeulich@suse.com>
808
809 * i386-gen.c (static_assert): Define.
810 (main): Use it.
811 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
812 (Opcode_Modifier_Num): ... this.
813 (Mem): Delete.
814
dfd69174
JB		 8152019-07-16 Jan Beulich <jbeulich@suse.com>
816
817 * i386-gen.c (operand_types): Move RegMem ...
818 (opcode_modifiers): ... here.
819 * i386-opc.h (RegMem): Move to opcode modifer enum.
820 (union i386_operand_type): Move regmem field ...
821 (struct i386_opcode_modifier): ... here.
822 * i386-opc.tbl (RegMem): Define.
823 (mov, movq): Move RegMem on segment, control, debug, and test
824 register flavors.
825 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
826 to non-SSE2AVX flavor.
827 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
828 Move RegMem on register only flavors. Drop IgnoreSize from
829 legacy encoding flavors.
830 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
831 flavors.
832 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
833 register only flavors.
834 (vmovd): Move RegMem and drop IgnoreSize on register only
835 flavor. Change opcode and operand order to store form.
836 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
837
21df382b
JB		 8382019-07-16 Jan Beulich <jbeulich@suse.com>
839
840 * i386-gen.c (operand_type_init, operand_types): Replace SReg
841 entries.
842 * i386-opc.h (SReg2, SReg3): Replace by ...
843 (SReg): ... this.
844 (union i386_operand_type): Replace sreg fields.
845 * i386-opc.tbl (mov, ): Use SReg.
846 (push, pop): Likewies. Drop i386 and x86-64 specific segment
847 register flavors.
848 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
849 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
850
3719fd55
JM		 8512019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
852
853 * bpf-desc.c: Regenerate.
854 * bpf-opc.c: Likewise.
855 * bpf-opc.h: Likewise.
856
92434a14
JM		 8572019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
858
859 * bpf-desc.c: Regenerate.
860 * bpf-opc.c: Likewise.
861
43dd7626
HPN		 8622019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
863
864 * arm-dis.c (print_insn_coprocessor): Rename index to
865 index_operand.
866
98602811
JW		 8672019-07-05 Kito Cheng <kito.cheng@sifive.com>
868
869 * riscv-opc.c (riscv_insn_types): Add r4 type.
870
871 * riscv-opc.c (riscv_insn_types): Add b and j type.
872
873 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
874 format for sb type and correct s type.
875
01c1ee4a
RS		 8762019-07-02 Richard Sandiford <richard.sandiford@arm.com>
877
878 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
879 SVE FMOV alias of FCPY.
880
83adff69
RS		 8812019-07-02 Richard Sandiford <richard.sandiford@arm.com>
882
883 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
884 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
885
89418844
RS		 8862019-07-02 Richard Sandiford <richard.sandiford@arm.com>
887
888 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
889 registers in an instruction prefixed by MOVPRFX.
890
41be57ca
MM		 8912019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
892
893 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
894 sve_size_13 icode to account for variant behaviour of
895 pmull{t,b}.
896 * aarch64-dis-2.c: Regenerate.
897 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
898 sve_size_13 icode to account for variant behaviour of
899 pmull{t,b}.
900 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
901 (OP_SVE_VVV_Q_D): Add new qualifier.
902 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
903 (struct aarch64_opcode): Split pmull{t,b} into those requiring
904 AES and those not.
905
9d3bf266
JB		 9062019-07-01 Jan Beulich <jbeulich@suse.com>
907
908 * opcodes/i386-gen.c (operand_type_init): Remove
909 OPERAND_TYPE_VEC_IMM4 entry.
910 (operand_types): Remove Vec_Imm4.
911 * opcodes/i386-opc.h (Vec_Imm4): Delete.
912 (union i386_operand_type): Remove vec_imm4.
913 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
914 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
915
c3949f43
JB		 9162019-07-01 Jan Beulich <jbeulich@suse.com>
917
918 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
919 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
920 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
921 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
922 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
923 monitorx, mwaitx): Drop ImmExt from operand-less forms.
924 * i386-tbl.h: Re-generate.
925
5641ec01
JB		 9262019-07-01 Jan Beulich <jbeulich@suse.com>
927
928 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
929 register operands.
930 * i386-tbl.h: Re-generate.
931
79dec6b7
JB		 9322019-07-01 Jan Beulich <jbeulich@suse.com>
933
934 * i386-opc.tbl (C): New.
935 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
936 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
937 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
938 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
939 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
940 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
941 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
942 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
943 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
944 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
945 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
946 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
947 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
948 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
949 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
950 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
951 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
952 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
953 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
954 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
955 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
956 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
957 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
958 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
959 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
960 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
961 flavors.
962 * i386-tbl.h: Re-generate.
963
a0a1771e
JB		 9642019-07-01 Jan Beulich <jbeulich@suse.com>
965
966 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
967 register operands.
968 * i386-tbl.h: Re-generate.
969
cd546e7b
JB		 9702019-07-01 Jan Beulich <jbeulich@suse.com>
971
972 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
973 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
974 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
975 * i386-tbl.h: Re-generate.
976
e3bba3fc
JB		 9772019-07-01 Jan Beulich <jbeulich@suse.com>
978
979 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
980 Disp8MemShift from register only templates.
981 * i386-tbl.h: Re-generate.
982
36cc073e
JB		 9832019-07-01 Jan Beulich <jbeulich@suse.com>
984
985 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
986 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
987 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
988 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
989 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
990 EVEX_W_0F11_P_3_M_1): Delete.
991 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
992 EVEX_W_0F11_P_3): New.
993 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
994 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
995 MOD_EVEX_0F11_PREFIX_3 table entries.
996 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
997 PREFIX_EVEX_0F11 table entries.
998 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
999 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1000 EVEX_W_0F11_P_3_M_{0,1} table entries.
1001
219920a7
JB		 10022019-07-01 Jan Beulich <jbeulich@suse.com>
1003
1004 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1005 Delete.
1006
e395f487
L		 10072019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1008
1009 PR binutils/24719
1010 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1011 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1012 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1013 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1014 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1015 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1016 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1017 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1018 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1019 PREFIX_EVEX_0F38C6_REG_6 entries.
1020 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1021 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1022 EVEX_W_0F38C7_R_6_P_2 entries.
1023 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1024 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1025 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1026 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1027 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1028 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1029 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1030
2b7bcc87
JB		 10312019-06-27 Jan Beulich <jbeulich@suse.com>
1032
1033 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1034 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1035 VEX_LEN_0F2D_P_3): Delete.
1036 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1037 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1038 (prefix_table): ... here.
1039
c1dc7af5
JB		 10402019-06-27 Jan Beulich <jbeulich@suse.com>
1041
1042 * i386-dis.c (Iq): Delete.
1043 (Id): New.
1044 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1045 TBM insns.
1046 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1047 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1048 (OP_E_memory): Also honor needindex when deciding whether an
1049 address size prefix needs printing.
1050 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1051
d7560e2d
JW		 10522019-06-26 Jim Wilson <jimw@sifive.com>
1053
1054 PR binutils/24739
1055 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1056 Set info->display_endian to info->endian_code.
1057
2c703856
JB		 10582019-06-25 Jan Beulich <jbeulich@suse.com>
1059
1060 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1061 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1062 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1063 OPERAND_TYPE_ACC64 entries.
1064 * i386-init.h: Re-generate.
1065
54fbadc0
JB		 10662019-06-25 Jan Beulich <jbeulich@suse.com>
1067
1068 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1069 Delete.
1070 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1071 of dqa_mode.
1072 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1073 entries here.
1074 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1075 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1076
a280ab8e
JB		 10772019-06-25 Jan Beulich <jbeulich@suse.com>
1078
1079 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1080 variables.
1081
e1a1babd
JB		 10822019-06-25 Jan Beulich <jbeulich@suse.com>
1083
1084 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1085 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1086 movnti.
d7560e2d 1087 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1088 * i386-tbl.h: Re-generate.
1089
b8364fa7
JB		 10902019-06-25 Jan Beulich <jbeulich@suse.com>
1091
1092 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1093 * i386-tbl.h: Re-generate.
1094
ad692897
L		 10952019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1096
1097 * i386-dis-evex.h: Break into ...
1098 * i386-dis-evex-len.h: New file.
1099 * i386-dis-evex-mod.h: Likewise.
1100 * i386-dis-evex-prefix.h: Likewise.
1101 * i386-dis-evex-reg.h: Likewise.
1102 * i386-dis-evex-w.h: Likewise.
1103 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1104 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1105 i386-dis-evex-mod.h.
1106
f0a6222e
L		 11072019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1108
1109 PR binutils/24700
1110 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1111 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1112 EVEX_W_0F385B_P_2.
1113 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1114 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1115 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1116 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1117 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1118 EVEX_LEN_0F385B_P_2_W_1.
1119 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1120 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1121 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1122 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1123 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1124 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1125 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1126 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1127 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1128 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1129
6e1c90b7
L		 11302019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1131
1132 PR binutils/24691
1133 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1134 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1135 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1136 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1137 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1138 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1139 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1140 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1141 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1142 EVEX_LEN_0F3A43_P_2_W_1.
1143 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1144 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1145 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1146 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1147 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1148 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1149 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1150 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1151 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1152 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1153 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1154 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1155
bcc5a6eb
NC		 11562019-06-14 Nick Clifton <nickc@redhat.com>
1157
1158 * po/fr.po; Updated French translation.
1159
e4c4ac46
SH		 11602019-06-13 Stafford Horne <shorne@gmail.com>
1161
1162 * or1k-asm.c: Regenerated.
1163 * or1k-desc.c: Regenerated.
1164 * or1k-desc.h: Regenerated.
1165 * or1k-dis.c: Regenerated.
1166 * or1k-ibld.c: Regenerated.
1167 * or1k-opc.c: Regenerated.
1168 * or1k-opc.h: Regenerated.
1169 * or1k-opinst.c: Regenerated.
1170
a0e44ef5
PB		 11712019-06-12 Peter Bergner <bergner@linux.ibm.com>
1172
1173 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1174
12efd68d
L		 11752019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1176
1177 PR binutils/24633
1178 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1179 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1180 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1181 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1182 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1183 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1184 EVEX_LEN_0F3A1B_P_2_W_1.
1185 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1186 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1187 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1188 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1189 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1190 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1191 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1192 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1193
63c6fc6c
L		 11942019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1195
1196 PR binutils/24626
1197 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1198 EVEX.vvvv when disassembling VEX and EVEX instructions.
1199 (OP_VEX): Set vex.register_specifier to 0 after readding
1200 vex.register_specifier.
1201 (OP_Vex_2src_1): Likewise.
1202 (OP_Vex_2src_2): Likewise.
1203 (OP_LWP_E): Likewise.
1204 (OP_EX_Vex): Don't check vex.register_specifier.
1205 (OP_XMM_Vex): Likewise.
1206
9186c494
L		 12072019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1208 Lili Cui <lili.cui@intel.com>
1209
1210 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1211 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1212 instructions.
1213 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1214 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1215 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1216 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1217 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1218 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1219 * i386-init.h: Regenerated.
1220 * i386-tbl.h: Likewise.
1221
5d79adc4
L		 12222019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1223 Lili Cui <lili.cui@intel.com>
1224
1225 * doc/c-i386.texi: Document enqcmd.
1226 * testsuite/gas/i386/enqcmd-intel.d: New file.
1227 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1228 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1229 * testsuite/gas/i386/enqcmd.d: Likewise.
1230 * testsuite/gas/i386/enqcmd.s: Likewise.
1231 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1232 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1233 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1234 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1235 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1236 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1237 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1238 and x86-64-enqcmd.
1239
a9d96ab9
AH		 12402019-06-04 Alan Hayward <alan.hayward@arm.com>
1241
1242 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1243
4f6d070a
AM		 12442019-06-03 Alan Modra <amodra@gmail.com>
1245
1246 * ppc-dis.c (prefix_opcd_indices): Correct size.
1247
a2f4b66c
L		 12482019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1249
1250 PR gas/24625
1251 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1252 Disp8ShiftVL.
1253 * i386-tbl.h: Regenerated.
1254
405b5bd8
AM		 12552019-05-24 Alan Modra <amodra@gmail.com>
1256
1257 * po/POTFILES.in: Regenerate.
1258
8acf1435
PB		 12592019-05-24 Peter Bergner <bergner@linux.ibm.com>
1260 Alan Modra <amodra@gmail.com>
1261
1262 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1263 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1264 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1265 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1266 XTOP>): Define and add entries.
1267 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1268 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1269 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1270 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1271
dd7efa79
PB		 12722019-05-24 Peter Bergner <bergner@linux.ibm.com>
1273 Alan Modra <amodra@gmail.com>
1274
1275 * ppc-dis.c (ppc_opts): Add "future" entry.
1276 (PREFIX_OPCD_SEGS): Define.
1277 (prefix_opcd_indices): New array.
1278 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1279 (lookup_prefix): New function.
1280 (print_insn_powerpc): Handle 64-bit prefix instructions.
1281 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1282 (PMRR, POWERXX): Define.
1283 (prefix_opcodes): New instruction table.
1284 (prefix_num_opcodes): New constant.
1285
79472b45
JM		 12862019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1287
1288 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1289 * configure: Regenerated.
1290 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1291 and cpu/bpf.opc.
1292 (HFILES): Add bpf-desc.h and bpf-opc.h.
1293 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1294 bpf-ibld.c and bpf-opc.c.
1295 (BPF_DEPS): Define.
1296 * Makefile.in: Regenerated.
1297 * disassemble.c (ARCH_bpf): Define.
1298 (disassembler): Add case for bfd_arch_bpf.
1299 (disassemble_init_for_target): Likewise.
1300 (enum epbf_isa_attr): Define.
1301 * disassemble.h: extern print_insn_bpf.
1302 * bpf-asm.c: Generated.
1303 * bpf-opc.h: Likewise.
1304 * bpf-opc.c: Likewise.
1305 * bpf-ibld.c: Likewise.
1306 * bpf-dis.c: Likewise.
1307 * bpf-desc.h: Likewise.
1308 * bpf-desc.c: Likewise.
1309
ba6cd17f
SD		 13102019-05-21 Sudakshina Das <sudi.das@arm.com>
1311
1312 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1313 and VMSR with the new operands.
1314
e39c1607
SD		 13152019-05-21 Sudakshina Das <sudi.das@arm.com>
1316
1317 * arm-dis.c (enum mve_instructions): New enum
1318 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1319 and cneg.
1320 (mve_opcodes): New instructions as above.
1321 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1322 csneg and csel.
1323 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1324
23d00a41
SD		 13252019-05-21 Sudakshina Das <sudi.das@arm.com>
1326
1327 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1328 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1329 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1330 uqshl, urshrl and urshr.
1331 (is_mve_okay_in_it): Add new instructions to TRUE list.
1332 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1333 (print_insn_mve): Updated to accept new %j,
1334 %<bitfield>m and %<bitfield>n patterns.
1335
cd4797ee
FS		 13362019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1337
1338 * mips-opc.c (mips_builtin_opcodes): Change source register
1339 constraint for DAUI.
1340
999b073b
NC		 13412019-05-20 Nick Clifton <nickc@redhat.com>
1342
1343 * po/fr.po: Updated French translation.
1344
14b456f2
AV		 13452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1346 Michael Collison <michael.collison@arm.com>
1347
1348 * arm-dis.c (thumb32_opcodes): Add new instructions.
1349 (enum mve_instructions): Likewise.
1350 (enum mve_undefined): Add new reasons.
1351 (is_mve_encoding_conflict): Handle new instructions.
1352 (is_mve_undefined): Likewise.
1353 (is_mve_unpredictable): Likewise.
1354 (print_mve_undefined): Likewise.
1355 (print_mve_size): Likewise.
1356
f49bb598
AV		 13572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1358 Michael Collison <michael.collison@arm.com>
1359
1360 * arm-dis.c (thumb32_opcodes): Add new instructions.
1361 (enum mve_instructions): Likewise.
1362 (is_mve_encoding_conflict): Handle new instructions.
1363 (is_mve_undefined): Likewise.
1364 (is_mve_unpredictable): Likewise.
1365 (print_mve_size): Likewise.
1366
56858bea
AV		 13672019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1368 Michael Collison <michael.collison@arm.com>
1369
1370 * arm-dis.c (thumb32_opcodes): Add new instructions.
1371 (enum mve_instructions): Likewise.
1372 (is_mve_encoding_conflict): Likewise.
1373 (is_mve_unpredictable): Likewise.
1374 (print_mve_size): Likewise.
1375
e523f101
AV		 13762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1377 Michael Collison <michael.collison@arm.com>
1378
1379 * arm-dis.c (thumb32_opcodes): Add new instructions.
1380 (enum mve_instructions): Likewise.
1381 (is_mve_encoding_conflict): Handle new instructions.
1382 (is_mve_undefined): Likewise.
1383 (is_mve_unpredictable): Likewise.
1384 (print_mve_size): Likewise.
1385
66dcaa5d
AV		 13862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1387 Michael Collison <michael.collison@arm.com>
1388
1389 * arm-dis.c (thumb32_opcodes): Add new instructions.
1390 (enum mve_instructions): Likewise.
1391 (is_mve_encoding_conflict): Handle new instructions.
1392 (is_mve_undefined): Likewise.
1393 (is_mve_unpredictable): Likewise.
1394 (print_mve_size): Likewise.
1395 (print_insn_mve): Likewise.
1396
d052b9b7
AV		 13972019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1398 Michael Collison <michael.collison@arm.com>
1399
1400 * arm-dis.c (thumb32_opcodes): Add new instructions.
1401 (print_insn_thumb32): Handle new instructions.
1402
ed63aa17
AV		 14032019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1404 Michael Collison <michael.collison@arm.com>
1405
1406 * arm-dis.c (enum mve_instructions): Add new instructions.
1407 (enum mve_undefined): Add new reasons.
1408 (is_mve_encoding_conflict): Handle new instructions.
1409 (is_mve_undefined): Likewise.
1410 (is_mve_unpredictable): Likewise.
1411 (print_mve_undefined): Likewise.
1412 (print_mve_size): Likewise.
1413 (print_mve_shift_n): Likewise.
1414 (print_insn_mve): Likewise.
1415
897b9bbc
AV		 14162019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1417 Michael Collison <michael.collison@arm.com>
1418
1419 * arm-dis.c (enum mve_instructions): Add new instructions.
1420 (is_mve_encoding_conflict): Handle new instructions.
1421 (is_mve_unpredictable): Likewise.
1422 (print_mve_rotate): Likewise.
1423 (print_mve_size): Likewise.
1424 (print_insn_mve): Likewise.
1425
1c8f2df8
AV		 14262019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1427 Michael Collison <michael.collison@arm.com>
1428
1429 * arm-dis.c (enum mve_instructions): Add new instructions.
1430 (is_mve_encoding_conflict): Handle new instructions.
1431 (is_mve_unpredictable): Likewise.
1432 (print_mve_size): Likewise.
1433 (print_insn_mve): Likewise.
1434
d3b63143
AV		 14352019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1436 Michael Collison <michael.collison@arm.com>
1437
1438 * arm-dis.c (enum mve_instructions): Add new instructions.
1439 (enum mve_undefined): Add new reasons.
1440 (is_mve_encoding_conflict): Handle new instructions.
1441 (is_mve_undefined): Likewise.
1442 (is_mve_unpredictable): Likewise.
1443 (print_mve_undefined): Likewise.
1444 (print_mve_size): Likewise.
1445 (print_insn_mve): Likewise.
1446
14925797
AV		 14472019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1448 Michael Collison <michael.collison@arm.com>
1449
1450 * arm-dis.c (enum mve_instructions): Add new instructions.
1451 (is_mve_encoding_conflict): Handle new instructions.
1452 (is_mve_undefined): Likewise.
1453 (is_mve_unpredictable): Likewise.
1454 (print_mve_size): Likewise.
1455 (print_insn_mve): Likewise.
1456
c507f10b
AV		 14572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1458 Michael Collison <michael.collison@arm.com>
1459
1460 * arm-dis.c (enum mve_instructions): Add new instructions.
1461 (enum mve_unpredictable): Add new reasons.
1462 (enum mve_undefined): Likewise.
1463 (is_mve_okay_in_it): Handle new isntructions.
1464 (is_mve_encoding_conflict): Likewise.
1465 (is_mve_undefined): Likewise.
1466 (is_mve_unpredictable): Likewise.
1467 (print_mve_vmov_index): Likewise.
1468 (print_simd_imm8): Likewise.
1469 (print_mve_undefined): Likewise.
1470 (print_mve_unpredictable): Likewise.
1471 (print_mve_size): Likewise.
1472 (print_insn_mve): Likewise.
1473
bf0b396d
AV		 14742019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1475 Michael Collison <michael.collison@arm.com>
1476
1477 * arm-dis.c (enum mve_instructions): Add new instructions.
1478 (enum mve_unpredictable): Add new reasons.
1479 (enum mve_undefined): Likewise.
1480 (is_mve_encoding_conflict): Handle new instructions.
1481 (is_mve_undefined): Likewise.
1482 (is_mve_unpredictable): Likewise.
1483 (print_mve_undefined): Likewise.
1484 (print_mve_unpredictable): Likewise.
1485 (print_mve_rounding_mode): Likewise.
1486 (print_mve_vcvt_size): Likewise.
1487 (print_mve_size): Likewise.
1488 (print_insn_mve): Likewise.
1489
ef1576a1
AV		 14902019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1491 Michael Collison <michael.collison@arm.com>
1492
1493 * arm-dis.c (enum mve_instructions): Add new instructions.
1494 (enum mve_unpredictable): Add new reasons.
1495 (enum mve_undefined): Likewise.
1496 (is_mve_undefined): Handle new instructions.
1497 (is_mve_unpredictable): Likewise.
1498 (print_mve_undefined): Likewise.
1499 (print_mve_unpredictable): Likewise.
1500 (print_mve_size): Likewise.
1501 (print_insn_mve): Likewise.
1502
aef6d006
AV		 15032019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1504 Michael Collison <michael.collison@arm.com>
1505
1506 * arm-dis.c (enum mve_instructions): Add new instructions.
1507 (enum mve_undefined): Add new reasons.
1508 (insns): Add new instructions.
1509 (is_mve_encoding_conflict):
1510 (print_mve_vld_str_addr): New print function.
1511 (is_mve_undefined): Handle new instructions.
1512 (is_mve_unpredictable): Likewise.
1513 (print_mve_undefined): Likewise.
1514 (print_mve_size): Likewise.
1515 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1516 (print_insn_mve): Handle new operands.
1517
04d54ace
AV		 15182019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1519 Michael Collison <michael.collison@arm.com>
1520
1521 * arm-dis.c (enum mve_instructions): Add new instructions.
1522 (enum mve_unpredictable): Add new reasons.
1523 (is_mve_encoding_conflict): Handle new instructions.
1524 (is_mve_unpredictable): Likewise.
1525 (mve_opcodes): Add new instructions.
1526 (print_mve_unpredictable): Handle new reasons.
1527 (print_mve_register_blocks): New print function.
1528 (print_mve_size): Handle new instructions.
1529 (print_insn_mve): Likewise.
1530
9743db03
AV		 15312019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1532 Michael Collison <michael.collison@arm.com>
1533
1534 * arm-dis.c (enum mve_instructions): Add new instructions.
1535 (enum mve_unpredictable): Add new reasons.
1536 (enum mve_undefined): Likewise.
1537 (is_mve_encoding_conflict): Handle new instructions.
1538 (is_mve_undefined): Likewise.
1539 (is_mve_unpredictable): Likewise.
1540 (coprocessor_opcodes): Move NEON VDUP from here...
1541 (neon_opcodes): ... to here.
1542 (mve_opcodes): Add new instructions.
1543 (print_mve_undefined): Handle new reasons.
1544 (print_mve_unpredictable): Likewise.
1545 (print_mve_size): Handle new instructions.
1546 (print_insn_neon): Handle vdup.
1547 (print_insn_mve): Handle new operands.
1548
143275ea
AV		 15492019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1550 Michael Collison <michael.collison@arm.com>
1551
1552 * arm-dis.c (enum mve_instructions): Add new instructions.
1553 (enum mve_unpredictable): Add new values.
1554 (mve_opcodes): Add new instructions.
1555 (vec_condnames): New array with vector conditions.
1556 (mve_predicatenames): New array with predicate suffixes.
1557 (mve_vec_sizename): New array with vector sizes.
1558 (enum vpt_pred_state): New enum with vector predication states.
1559 (struct vpt_block): New struct type for vpt blocks.
1560 (vpt_block_state): Global struct to keep track of state.
1561 (mve_extract_pred_mask): New helper function.
1562 (num_instructions_vpt_block): Likewise.
1563 (mark_outside_vpt_block): Likewise.
1564 (mark_inside_vpt_block): Likewise.
1565 (invert_next_predicate_state): Likewise.
1566 (update_next_predicate_state): Likewise.
1567 (update_vpt_block_state): Likewise.
1568 (is_vpt_instruction): Likewise.
1569 (is_mve_encoding_conflict): Add entries for new instructions.
1570 (is_mve_unpredictable): Likewise.
1571 (print_mve_unpredictable): Handle new cases.
1572 (print_instruction_predicate): Likewise.
1573 (print_mve_size): New function.
1574 (print_vec_condition): New function.
1575 (print_insn_mve): Handle vpt blocks and new print operands.
1576
f08d8ce3
AV		 15772019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1578
1579 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1580 8, 14 and 15 for Armv8.1-M Mainline.
1581
73cd51e5
AV		 15822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1583 Michael Collison <michael.collison@arm.com>
1584
1585 * arm-dis.c (enum mve_instructions): New enum.
1586 (enum mve_unpredictable): Likewise.
1587 (enum mve_undefined): Likewise.
1588 (struct mopcode32): New struct.
1589 (is_mve_okay_in_it): New function.
1590 (is_mve_architecture): Likewise.
1591 (arm_decode_field): Likewise.
1592 (arm_decode_field_multiple): Likewise.
1593 (is_mve_encoding_conflict): Likewise.
1594 (is_mve_undefined): Likewise.
1595 (is_mve_unpredictable): Likewise.
1596 (print_mve_undefined): Likewise.
1597 (print_mve_unpredictable): Likewise.
1598 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1599 (print_insn_mve): New function.
1600 (print_insn_thumb32): Handle MVE architecture.
1601 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1602
3076e594
NC		 16032019-05-10 Nick Clifton <nickc@redhat.com>
1604
1605 PR 24538
1606 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1607 end of the table prematurely.
1608
387e7624
FS		 16092019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1610
1611 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1612 macros for R6.
1613
0067be51
AM		 16142019-05-11 Alan Modra <amodra@gmail.com>
1615
1616 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1617 when -Mraw is in effect.
1618
42e6288f
MM		 16192019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1620
1621 * aarch64-dis-2.c: Regenerate.
1622 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1623 (OP_SVE_BBB): New variant set.
1624 (OP_SVE_DDDD): New variant set.
1625 (OP_SVE_HHH): New variant set.
1626 (OP_SVE_HHHU): New variant set.
1627 (OP_SVE_SSS): New variant set.
1628 (OP_SVE_SSSU): New variant set.
1629 (OP_SVE_SHH): New variant set.
1630 (OP_SVE_SBBU): New variant set.
1631 (OP_SVE_DSS): New variant set.
1632 (OP_SVE_DHHU): New variant set.
1633 (OP_SVE_VMV_HSD_BHS): New variant set.
1634 (OP_SVE_VVU_HSD_BHS): New variant set.
1635 (OP_SVE_VVVU_SD_BH): New variant set.
1636 (OP_SVE_VVVU_BHSD): New variant set.
1637 (OP_SVE_VVV_QHD_DBS): New variant set.
1638 (OP_SVE_VVV_HSD_BHS): New variant set.
1639 (OP_SVE_VVV_HSD_BHS2): New variant set.
1640 (OP_SVE_VVV_BHS_HSD): New variant set.
1641 (OP_SVE_VV_BHS_HSD): New variant set.
1642 (OP_SVE_VVV_SD): New variant set.
1643 (OP_SVE_VVU_BHS_HSD): New variant set.
1644 (OP_SVE_VZVV_SD): New variant set.
1645 (OP_SVE_VZVV_BH): New variant set.
1646 (OP_SVE_VZV_SD): New variant set.
1647 (aarch64_opcode_table): Add sve2 instructions.
1648
28ed815a
MM		 16492019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1650
1651 * aarch64-asm-2.c: Regenerated.
1652 * aarch64-dis-2.c: Regenerated.
1653 * aarch64-opc-2.c: Regenerated.
1654 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1655 for SVE_SHLIMM_UNPRED_22.
1656 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1657 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1658 operand.
1659
fd1dc4a0
MM		 16602019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1661
1662 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1663 sve_size_tsz_bhs iclass encode.
1664 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1665 sve_size_tsz_bhs iclass decode.
1666
31e36ab3
MM		 16672019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1668
1669 * aarch64-asm-2.c: Regenerated.
1670 * aarch64-dis-2.c: Regenerated.
1671 * aarch64-opc-2.c: Regenerated.
1672 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1673 for SVE_Zm4_11_INDEX.
1674 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1675 (fields): Handle SVE_i2h field.
1676 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1677 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1678
1be5f94f
MM		 16792019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1680
1681 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1682 sve_shift_tsz_bhsd iclass encode.
1683 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1684 sve_shift_tsz_bhsd iclass decode.
1685
3c17238b
MM		 16862019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1687
1688 * aarch64-asm-2.c: Regenerated.
1689 * aarch64-dis-2.c: Regenerated.
1690 * aarch64-opc-2.c: Regenerated.
1691 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1692 (aarch64_encode_variant_using_iclass): Handle
1693 sve_shift_tsz_hsd iclass encode.
1694 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1695 sve_shift_tsz_hsd iclass decode.
1696 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1697 for SVE_SHRIMM_UNPRED_22.
1698 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1699 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1700 operand.
1701
cd50a87a
MM		 17022019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1703
1704 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1705 sve_size_013 iclass encode.
1706 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1707 sve_size_013 iclass decode.
1708
3c705960
MM		 17092019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1710
1711 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1712 sve_size_bh iclass encode.
1713 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1714 sve_size_bh iclass decode.
1715
0a57e14f
MM		 17162019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1717
1718 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1719 sve_size_sd2 iclass encode.
1720 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1721 sve_size_sd2 iclass decode.
1722 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1723 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1724
c469c864
MM		 17252019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1726
1727 * aarch64-asm-2.c: Regenerated.
1728 * aarch64-dis-2.c: Regenerated.
1729 * aarch64-opc-2.c: Regenerated.
1730 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1731 for SVE_ADDR_ZX.
1732 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1733 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1734
116adc27
MM		 17352019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1736
1737 * aarch64-asm-2.c: Regenerated.
1738 * aarch64-dis-2.c: Regenerated.
1739 * aarch64-opc-2.c: Regenerated.
1740 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1741 for SVE_Zm3_11_INDEX.
1742 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1743 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1744 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1745 fields.
1746 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1747
3bd82c86
MM		 17482019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1749
1750 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1751 sve_size_hsd2 iclass encode.
1752 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1753 sve_size_hsd2 iclass decode.
1754 * aarch64-opc.c (fields): Handle SVE_size field.
1755 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1756
adccc507
MM		 17572019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1758
1759 * aarch64-asm-2.c: Regenerated.
1760 * aarch64-dis-2.c: Regenerated.
1761 * aarch64-opc-2.c: Regenerated.
1762 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1763 for SVE_IMM_ROT3.
1764 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1765 (fields): Handle SVE_rot3 field.
1766 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1767 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1768
5cd99750
MM		 17692019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1770
1771 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1772 instructions.
1773
7ce2460a
MM		 17742019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1775
1776 * aarch64-tbl.h
1777 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1778 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1779 aarch64_feature_sve2bitperm): New feature sets.
1780 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1781 for feature set addresses.
1782 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1783 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1784
41cee089
FS		 17852019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1786 Faraz Shahbazker <fshahbazker@wavecomp.com>
1787
1788 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1789 argument and set ASE_EVA_R6 appropriately.
1790 (set_default_mips_dis_options): Pass ISA to above.
1791 (parse_mips_dis_option): Likewise.
1792 * mips-opc.c (EVAR6): New macro.
1793 (mips_builtin_opcodes): Add llwpe, scwpe.
1794
b83b4b13
SD		 17952019-05-01 Sudakshina Das <sudi.das@arm.com>
1796
1797 * aarch64-asm-2.c: Regenerated.
1798 * aarch64-dis-2.c: Regenerated.
1799 * aarch64-opc-2.c: Regenerated.
1800 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1801 AARCH64_OPND_TME_UIMM16.
1802 (aarch64_print_operand): Likewise.
1803 * aarch64-tbl.h (QL_IMM_NIL): New.
1804 (TME): New.
1805 (_TME_INSN): New.
1806 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1807
4a90ce95
JD		 18082019-04-29 John Darrington <john@darrington.wattle.id.au>
1809
1810 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1811
a45328b9
AB		 18122019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1813 Faraz Shahbazker <fshahbazker@wavecomp.com>
1814
1815 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1816
d10be0cb
JD		 18172019-04-24 John Darrington <john@darrington.wattle.id.au>
1818
1819 * s12z-opc.h: Add extern "C" bracketing to help
1820 users who wish to use this interface in c++ code.
1821
a679f24e
JD		 18222019-04-24 John Darrington <john@darrington.wattle.id.au>
1823
1824 * s12z-opc.c (bm_decode): Handle bit map operations with the
1825 "reserved0" mode.
1826
32c36c3c
AV		 18272019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1828
1829 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1830 specifier. Add entries for VLDR and VSTR of system registers.
1831 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1832 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1833 of %J and %K format specifier.
1834
efd6b359
AV		 18352019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1836
1837 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1838 Add new entries for VSCCLRM instruction.
1839 (print_insn_coprocessor): Handle new %C format control code.
1840
6b0dd094
AV		 18412019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1842
1843 * arm-dis.c (enum isa): New enum.
1844 (struct sopcode32): New structure.
1845 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1846 set isa field of all current entries to ANY.
1847 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1848 Only match an entry if its isa field allows the current mode.
1849
4b5a202f
AV		 18502019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1851
1852 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1853 CLRM.
1854 (print_insn_thumb32): Add logic to print %n CLRM register list.
1855
60f993ce
AV		 18562019-04-15 Sudakshina Das <sudi.das@arm.com>
1857
1858 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1859 and %Q patterns.
1860
f6b2b12d
AV		 18612019-04-15 Sudakshina Das <sudi.das@arm.com>
1862
1863 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1864 (print_insn_thumb32): Edit the switch case for %Z.
1865
1889da70
AV		 18662019-04-15 Sudakshina Das <sudi.das@arm.com>
1867
1868 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1869
65d1bc05
AV		 18702019-04-15 Sudakshina Das <sudi.das@arm.com>
1871
1872 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1873
1caf72a5
AV		 18742019-04-15 Sudakshina Das <sudi.das@arm.com>
1875
1876 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1877
f1c7f421
AV		 18782019-04-15 Sudakshina Das <sudi.das@arm.com>
1879
1880 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1881 Arm register with r13 and r15 unpredictable.
1882 (thumb32_opcodes): New instructions for bfx and bflx.
1883
4389b29a
AV		 18842019-04-15 Sudakshina Das <sudi.das@arm.com>
1885
1886 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1887
e5d6e09e
AV		 18882019-04-15 Sudakshina Das <sudi.das@arm.com>
1889
1890 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1891
e12437dc
AV		 18922019-04-15 Sudakshina Das <sudi.das@arm.com>
1893
1894 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1895
031254f2
AV		 18962019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1897
1898 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1899
e5a557ac
JD		 19002019-04-12 John Darrington <john@darrington.wattle.id.au>
1901
1902 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1903 "optr". ("operator" is a reserved word in c++).
1904
bd7ceb8d
SD		 19052019-04-11 Sudakshina Das <sudi.das@arm.com>
1906
1907 * aarch64-opc.c (aarch64_print_operand): Add case for
1908 AARCH64_OPND_Rt_SP.
1909 (verify_constraints): Likewise.
1910 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1911 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1912 to accept Rt|SP as first operand.
1913 (AARCH64_OPERANDS): Add new Rt_SP.
1914 * aarch64-asm-2.c: Regenerated.
1915 * aarch64-dis-2.c: Regenerated.
1916 * aarch64-opc-2.c: Regenerated.
1917
e54010f1
SD		 19182019-04-11 Sudakshina Das <sudi.das@arm.com>
1919
1920 * aarch64-asm-2.c: Regenerated.
1921 * aarch64-dis-2.c: Likewise.
1922 * aarch64-opc-2.c: Likewise.
1923 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1924
7e96e219
RS		 19252019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1926
1927 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1928
6f2791d5
L		 19292019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1930
1931 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1932 * i386-init.h: Regenerated.
1933
e392bad3
AM		 19342019-04-07 Alan Modra <amodra@gmail.com>
1935
1936 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1937 op_separator to control printing of spaces, comma and parens
1938 rather than need_comma, need_paren and spaces vars.
1939
dffaa15c
AM		 19402019-04-07 Alan Modra <amodra@gmail.com>
1941
1942 PR 24421
1943 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1944 (print_insn_neon, print_insn_arm): Likewise.
1945
d6aab7a1
XG		 19462019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1947
1948 * i386-dis-evex.h (evex_table): Updated to support BF16
1949 instructions.
1950 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1951 and EVEX_W_0F3872_P_3.
1952 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1953 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1954 * i386-opc.h (enum): Add CpuAVX512_BF16.
1955 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1956 * i386-opc.tbl: Add AVX512 BF16 instructions.
1957 * i386-init.h: Regenerated.
1958 * i386-tbl.h: Likewise.
1959
66e85460
AM		 19602019-04-05 Alan Modra <amodra@gmail.com>
1961
1962 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1963 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1964 to favour printing of "-" branch hint when using the "y" bit.
1965 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1966
c2b1c275
AM		 19672019-04-05 Alan Modra <amodra@gmail.com>
1968
1969 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1970 opcode until first operand is output.
1971
aae9718e
PB		 19722019-04-04 Peter Bergner <bergner@linux.ibm.com>
1973
1974 PR gas/24349
1975 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1976 (valid_bo_post_v2): Add support for 'at' branch hints.
1977 (insert_bo): Only error on branch on ctr.
1978 (get_bo_hint_mask): New function.
1979 (insert_boe): Add new 'branch_taken' formal argument. Add support
1980 for inserting 'at' branch hints.
1981 (extract_boe): Add new 'branch_taken' formal argument. Add support
1982 for extracting 'at' branch hints.
1983 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1984 (BOE): Delete operand.
1985 (BOM, BOP): New operands.
1986 (RM): Update value.
1987 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1988 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1989 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1990 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1991 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1992 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1993 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1994 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1995 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1996 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1997 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1998 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1999 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2000 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2001 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2002 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2003 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2004 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2005 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2006 bttarl+>: New extended mnemonics.
2007
96a86c01
AM		 20082019-03-28 Alan Modra <amodra@gmail.com>
2009
2010 PR 24390
2011 * ppc-opc.c (BTF): Define.
2012 (powerpc_opcodes): Use for mtfsb*.
2013 * ppc-dis.c (print_insn_powerpc): Print fields with both
2014 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2015
796d6298
TC		 20162019-03-25 Tamar Christina <tamar.christina@arm.com>
2017
2018 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2019 (mapping_symbol_for_insn): Implement new algorithm.
2020 (print_insn): Remove duplicate code.
2021
60df3720
TC		 20222019-03-25 Tamar Christina <tamar.christina@arm.com>
2023
2024 * aarch64-dis.c (print_insn_aarch64):
2025 Implement override.
2026
51457761
TC		 20272019-03-25 Tamar Christina <tamar.christina@arm.com>
2028
2029 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2030 order.
2031
53b2f36b
TC		 20322019-03-25 Tamar Christina <tamar.christina@arm.com>
2033
2034 * aarch64-dis.c (last_stop_offset): New.
2035 (print_insn_aarch64): Use stop_offset.
2036
89199bb5
L		 20372019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2038
2039 PR gas/24359
2040 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2041 CPU_ANY_AVX2_FLAGS.
2042 * i386-init.h: Regenerated.
2043
97ed31ae
L		 20442019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2045
2046 PR gas/24348
2047 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2048 vmovdqu16, vmovdqu32 and vmovdqu64.
2049 * i386-tbl.h: Regenerated.
2050
0919bfe9
AK		 20512019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2052
2053 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2054 from vstrszb, vstrszh, and vstrszf.
2055
20562019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2057
2058 * s390-opc.txt: Add instruction descriptions.
2059
21820ebe
JW		 20602019-02-08 Jim Wilson <jimw@sifive.com>
2061
2062 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2063 <bne>: Likewise.
2064
f7dd2fb2
TC		 20652019-02-07 Tamar Christina <tamar.christina@arm.com>
2066
2067 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2068
6456d318
TC		 20692019-02-07 Tamar Christina <tamar.christina@arm.com>
2070
2071 PR binutils/23212
2072 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2073 * aarch64-opc.c (verify_elem_sd): New.
2074 (fields): Add FLD_sz entr.
2075 * aarch64-tbl.h (_SIMD_INSN): New.
2076 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2077 fmulx scalar and vector by element isns.
2078
4a83b610
NC		 20792019-02-07 Nick Clifton <nickc@redhat.com>
2080
2081 * po/sv.po: Updated Swedish translation.
2082
fc60b8c8
AK		 20832019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2084
2085 * s390-mkopc.c (main): Accept arch13 as cpu string.
2086 * s390-opc.c: Add new instruction formats and instruction opcode
2087 masks.
2088 * s390-opc.txt: Add new arch13 instructions.
2089
e10620d3
TC		 20902019-01-25 Sudakshina Das <sudi.das@arm.com>
2091
2092 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2093 (aarch64_opcode): Change encoding for stg, stzg
2094 st2g and st2zg.
2095 * aarch64-asm-2.c: Regenerated.
2096 * aarch64-dis-2.c: Regenerated.
2097 * aarch64-opc-2.c: Regenerated.
2098
20a4ca55
SD		 20992019-01-25 Sudakshina Das <sudi.das@arm.com>
2100
2101 * aarch64-asm-2.c: Regenerated.
2102 * aarch64-dis-2.c: Likewise.
2103 * aarch64-opc-2.c: Likewise.
2104 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2105
550fd7bf
SD		 21062019-01-25 Sudakshina Das <sudi.das@arm.com>
2107 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2108
2109 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2110 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2111 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2112 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2113 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2114 case for ldstgv_indexed.
2115 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2116 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2117 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2118 * aarch64-asm-2.c: Regenerated.
2119 * aarch64-dis-2.c: Regenerated.
2120 * aarch64-opc-2.c: Regenerated.
2121
d9938630
NC		 21222019-01-23 Nick Clifton <nickc@redhat.com>
2123
2124 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2125
375cd423
NC		 21262019-01-21 Nick Clifton <nickc@redhat.com>
2127
2128 * po/de.po: Updated German translation.
2129 * po/uk.po: Updated Ukranian translation.
2130
57299f48
CX		 21312019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2132 * mips-dis.c (mips_arch_choices): Fix typo in
2133 gs464, gs464e and gs264e descriptors.
2134
f48dfe41
NC		 21352019-01-19 Nick Clifton <nickc@redhat.com>
2136
2137 * configure: Regenerate.
2138 * po/opcodes.pot: Regenerate.
2139
f974f26c
NC		 21402018-06-24 Nick Clifton <nickc@redhat.com>
2141
2142 2.32 branch created.
2143
39f286cd
JD		 21442019-01-09 John Darrington <john@darrington.wattle.id.au>
2145
448b8ca8
JD		 2146 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2147 if it is null.
2148 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2149 zero.
2150
3107326d
AP		 21512019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2152
2153 * configure: Regenerate.
2154
7e9ca91e
AM		 21552019-01-07 Alan Modra <amodra@gmail.com>
2156
2157 * configure: Regenerate.
2158 * po/POTFILES.in: Regenerate.
2159
ef1ad42b
JD		 21602019-01-03 John Darrington <john@darrington.wattle.id.au>
2161
2162 * s12z-opc.c: New file.
2163 * s12z-opc.h: New file.
2164 * s12z-dis.c: Removed all code not directly related to display
2165 of instructions. Used the interface provided by the new files
2166 instead.
2167 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2168 * Makefile.in: Regenerate.
ef1ad42b 2169 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2170 * configure: Regenerate.
ef1ad42b 2171
82704155
AM		 21722019-01-01 Alan Modra <amodra@gmail.com>
2173
2174 Update year range in copyright notice of all files.
2175
d5c04e1b 2176For older changes see ChangeLog-2018
3499769a 2177\f
d5c04e1b 2178Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2179
2180Copying and distribution of this file, with or without modification,
2181are permitted in any medium without royalty provided the copyright
2182notice and this notice are preserved.
2183
2184Local Variables:
2185mode: change-log
2186left-margin: 8
2187fill-column: 74
2188version-control: never
2189End:
GDB Binutils - Deliverables
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