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sim: m68hc11: fix default endian
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ff8646ee
TP		 12015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
2
3 * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex,
4 ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by
5 ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
6
4ed7ed8d
TP		 72015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
8
9 * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
10 stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
11 ARM_EXT_V8.
12 (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
13
239efab1
YS		 142015-12-22 Yoshinori Sato <ysato@users.sourceforge.jp>
15
331e6131
AM		 16 * rx-decode.opc (movco): Use uniqe id.
17 (movli): Likewise.
18 (stnz): Condition fix.
19 (mvtacgu): Destination fix.
20 * rx-decode.c: Regenerate.
239efab1 21
a117b0a5
YS		 222015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
23
24 * rx-deocde.opc: Add new instructions pattern.
25 * rx-deocde.c: Regenerate.
26 * rx-dis.c (register_name): Add new register.
27
4fd0a9fd
MW		 282015-12-14 Matthew Wahab <matthew.wahab@arm.com>
29
30 * aarch64-asm-2.c: Regenerate.
31 * aarch64-dis-2.c: Regenerate.
32 * aarch64-opc-2.c: Regenerate.
33 * aarch64-tbl.h (QL_SSHIFT_H): New.
34 (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
35 and fcvtzu to the Adv.SIMD scalar shift by immediate group.
36
b5b0f34c
MW		 372015-12-14 Matthew Wahab <matthew.wahab@arm.com>
38
39 * aarch64-asm-2.c: Regenerate.
40 * aarch64-dis-2.c: Regenerate.
41 * aarch64-opc-2.c: Regenerate.
42 * aarch64-tbl.h (QL_VSHIFT_H): New.
43 (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
44 and fcvtzu to the Adv.SIMD shift by immediate group.
45
b195470d
MW		 462015-12-14 Matthew Wahab <matthew.wahab@arm.com>
47
48 * aarch64-asm-2.c: Regenerate.
49 * aarch64-dis-2.c: Regenerate.
50 * aarch64-opc-2.c: Regenerate.
51 * aarch64-tbl.h (QL_SISD_PAIR_H): New.
52 (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
53 fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
54
3067d3b9
MW		 552015-12-14 Matthew Wahab <matthew.wahab@arm.coM>
56
57 * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
58 and adjust calculation to ignore qualifier for type 2H.
59 * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
60
4b5fc357
MW		 612015-12-14 Matthew Wahab <matthew.wahab@arm.com>
62
63 * aarch64-asm-2.c: Regenerate.
64 * aarch64-dis-2.c: Regenerate.
65 * aarch64-opc-2.c: Regenerate.
66 * aarch64-tbl.h (QL_SIMD_IMM_H): New.
67 (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
68 modified immediate group.
69
bb515fea
MW		 702015-12-14 Matthew Wahab <matthew.wahab@arm.com>
71
72 * aarch64-asm-2.c: Regenerate.
73 * aarch64-dis-2.c: Regenerate.
74 * aarch64-opc-2.c: Regenerate.
75 * aarch64-tbl.h (QL_XLANES_FP_H): New.
76 (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
77 fminnmv, fminv to the Adv.SIMD across lanes group.
78
5f7728b7
MW		 792015-12-14 Matthew Wahab <matthew.wahab@arm.com>
80
81 * aarch64-asm-2.c: Regenerate.
82 * aarch64-dis-2.c: Regenerate.
83 * aarch64-opc-2.c: Regenerate.
84 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
85 fmls, fmul and fmulx to the scalar indexed element group.
86
42f23f62
MW		 872015-12-14 Matthew Wahab <matthew.wahab@arm.com>
88
89 * aarch64-asm-2.c: Regenerate.
90 * aarch64-dis-2.c: Regenerate.
91 * aarch64-opc-2.c: Regenerate.
92 * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
93 (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
94 fmulx to the vector indexed element group.
95
80776b29
MW		 962015-12-14 Matthew Wahab <matthew.wahab@arm.com>
97
98 * aarch64-asm-2.c: Regenerate.
99 * aarch64-dis-2.c: Regenerate.
100 * aarch64-opc-2.c: Regenerate.
101 * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
102 (QL_S_2SAMEH): New.
103 (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
104 fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
105 frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
106 fcvtzu and frsqrte to the scalar two register misc. group.
107
f3aa142b
MW		 1082015-12-14 Matthew Wahab <matthew.wahab@arm.com>
109
110 * aarch64-asm-2.c: Regenerate.
111 * aarch64-dis-2.c: Regenerate.
112 * aarch64-opc-2.c: Regenerate.
113 * aarch64-tbl.h (QL_V2SAMEH): New.
114 (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
115 fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
116 frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
117 fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
118 and fsqrt to the vector register misc. group.
119
6b4680fb
MW		 1202015-12-14 Matthew Wahab <matthew.wahab@arm.com>
121
122 * aarch64-asm-2.c: Regenerate.
123 * aarch64-dis-2.c: Regenerate.
124 * aarch64-opc-2.c: Regenerate.
125 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
126 fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
127 to the scalar three same group.
128
51d543ed
MW		 1292015-12-14 Matthew Wahab <matthew.wahab@arm.com>
130
131 * aarch64-asm-2.c: Regenerate.
132 * aarch64-dis-2.c: Regenerate.
133 * aarch64-opc-2.c: Regenerate.
134 * aarch64-tbl.h (QL_V3SAMEH): New.
135 (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
136 fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
137 fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
138 fcmgt, facgt and fminp to the vector three same group.
139
40d16a76
MW		 1402015-12-14 Matthew Wahab <matthew.wahab@arm.com>
141
142 * aarch64-tbl.h (aarch64_feature_simd_f16): New.
143 (SIMD_F16): New.
144
63511907
MW		 1452015-12-14 Matthew Wahab <matthew.wahab@arm.com>
146
147 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
148 removed statement.
149 (aarch64_pstatefield_supported_p): Move feature checks for AT
150 registers ..
151 (aarch64_sys_ins_reg_supported_p): .. to here.
152
b817670b
AM		 1532015-12-12 Alan Modra <amodra@gmail.com>
154
155 PR 19359
156 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
157 (powerpc_opcodes): Remove single-operand mfcr.
158
9ed608f9
MW		 1592015-12-11 Matthew Wahab <matthew.wahab@arm.com>
160
161 * aarch64-asm.c (aarch64_ins_hint): New.
162 * aarch64-asm.h (aarch64_ins_hint): Declare.
163 * aarch64-dis.c (aarch64_ext_hint): New.
164 * aarch64-dis.h (aarch64_ext_hint): Declare.
165 * aarch64-opc-2.c: Regenerate.
166 * aarch64-opc.c (aarch64_hint_options): New.
167 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
168
a0f7013a
MW		 1692015-12-11 Matthew Wahab <matthew.wahab@arm.com>
170
171 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
172
55c144e6
MW		 1732015-12-11 Matthew Wahab <matthew.wahab@arm.com>
174
175 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
176 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
177 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
178 pmscr_el2.
179 (aarch64_sys_reg_supported_p): Add architecture feature tests for
180 the new registers.
181
22a5455c
MW		 1822015-12-10 Matthew Wahab <matthew.wahab@arm.com>
183
184 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
185 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
186 feature test for "s1e1rp" and "s1e1wp".
187
d6bf7ce6
MW		 1882015-12-10 Matthew Wahab <matthew.wahab@arm.com>
189
190 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
191 (aarch64_sys_ins_reg_supported_p): New.
192
ea2deeec
MW		 1932015-12-10 Matthew Wahab <matthew.wahab@arm.com>
194
195 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
196 with aarch64_sys_ins_reg_has_xt.
197 (aarch64_ext_sysins_op): Likewise.
198 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
199 (F_HASXT): New.
200 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
201 (aarch64_sys_regs_dc): Likewise.
202 (aarch64_sys_regs_at): Likewise.
203 (aarch64_sys_regs_tlbi): Likewise.
204 (aarch64_sys_ins_reg_has_xt): New.
205
6479e48e
MW		 2062015-12-10 Matthew Wahab <matthew.wahab@arm.com>
207
208 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
209 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
210 (aarch64_pstatefields): Add "uao".
211 (aarch64_pstatefield_supported_p): Add checks for "uao".
212
47f81142
MW		 2132015-12-10 Matthew Wahab <matthew.wahab@arm.com>
214
215 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
216 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
217 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
218 (aarch64_sys_reg_supported_p): Add architecture feature tests for
219 new registers.
220
c8a6db6f
MW		 2212015-12-10 Matthew Wahab <matthew.wahab@arm.com>
222
223 * aarch64-asm-2.c: Regenerate.
224 * aarch64-dis-2.c: Regenerate.
225 * aarch64-tbl.h (aarch64_feature_ras): New.
226 (RAS): New.
227 (aarch64_opcode_table): Add "esb".
228
8eab4136
L		 2292015-12-09 H.J. Lu <hongjiu.lu@intel.com>
230
231 * i386-dis.c (MOD_0F01_REG_5): New.
232 (RM_0F01_REG_5): Likewise.
233 (reg_table): Use MOD_0F01_REG_5.
234 (mod_table): Add MOD_0F01_REG_5.
235 (rm_table): Add RM_0F01_REG_5.
236 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
237 (cpu_flags): Add CpuOSPKE.
238 * i386-opc.h (CpuOSPKE): New.
239 (i386_cpu_flags): Add cpuospke.
240 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
241 * i386-init.h: Regenerated.
242 * i386-tbl.h: Likewise.
243
1eac08cc
DD		 2442015-12-07 DJ Delorie <dj@redhat.com>
245
246 * rl78-decode.opc: Enable MULU for all ISAs.
247 * rl78-decode.c: Regenerate.
248
dd2887fc
AM		 2492015-12-07 Alan Modra <amodra@gmail.com>
250
331e6131 251 * ppc-opc.c (powerpc_opcodes): Sort power9 insns by
dd2887fc
AM		 252 major opcode/xop.
253
24b368f8
CZ		 2542015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
255
256 * arc-dis.c (special_flag_p): Match full mnemonic.
257 * arc-opc.c (print_insn_arc): Check section size to read
258 appropriate number of bytes. Fix printing.
259 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
260 arguments.
261
3395762e
AV		 2622015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
263
264 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
265 <ldah>: ... to this.
266
622b9eb1
MW		 2672015-11-27 Matthew Wahab <matthew.wahab@arm.com>
268
269 * aarch64-asm-2.c: Regenerate.
270 * aarch64-dis-2.c: Regenerate.
271 * aarch64-opc-2.c: Regenerate.
272 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
273 (QL_INT2FP_H, QL_FP2INT_H): New.
274 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
275 (QL_DST_H): New.
276 (QL_FCCMP_H): New.
277 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
278 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
279 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
280 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
281 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
282 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
283 fcsel.
284
cf86120b
MW		 2852015-11-27 Matthew Wahab <matthew.wahab@arm.com>
286
287 * aarch64-opc.c (half_conv_t): New.
331e6131 288 (expand_fp_imm): Replace is_dp flag with the parameter size to
cf86120b
MW		 289 specify the number of bytes for the required expansion. Treat
290 a 16-bit expansion like a 32-bit expansion. Add check for an
291 unsupported size request. Update comment.
292 (aarch64_print_operand): Update to support 16-bit floating point
293 values. Update for changes to expand_fp_imm.
294
3bd894a7
MW		 2952015-11-27 Matthew Wahab <matthew.wahab@arm.com>
296
297 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
298 (FP_F16): New.
299
64357d2e
MW		 3002015-11-27 Matthew Wahab <matthew.wahab@arm.com>
301
302 * aarch64-asm-2.c: Regenerate.
303 * aarch64-dis-2.c: Regenerate.
304 * aarch64-opc-2.c: Regenerate.
305 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
306 "rev64".
307
d685192a
MW		 3082015-11-27 Matthew Wahab <matthew.wahab@arm.com>
309
310 * aarch64-asm-2.c: Regenerate.
311 * aarch64-asm.c (convert_bfc_to_bfm): New.
312 (convert_to_real): Add case for OP_BFC.
313 * aarch64-dis-2.c: Regenerate.
314 * aarch64-dis.c: (convert_bfm_to_bfc): New.
315 (convert_to_alias): Add case for OP_BFC.
316 * aarch64-opc-2.c: Regenerate.
317 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
318 to allow width operand in three-operand instructions.
319 * aarch64-tbl.h (QL_BF1): New.
320 (aarch64_feature_v8_2): New.
321 (ARMV8_2): New.
322 (aarch64_opcode_table): Add "bfc".
323
35822b38
MW		 3242015-11-27 Matthew Wahab <matthew.wahab@arm.com>
325
326 * aarch64-asm-2.c: Regenerate.
327 * aarch64-dis-2.c: Regenerate.
328 * aarch64-dis.c: Weaken assert.
329 * aarch64-gen.c: Include the instruction in the list of its
330 possible aliases.
331
1a04d1a7
MW		 3322015-11-27 Matthew Wahab <matthew.wahab@arm.com>
333
334 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
335 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
336 feature test.
337
e49d43ff
TG		 3382015-11-23 Tristan Gingold <gingold@adacore.com>
339
340 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
341
250aafa4
MW		 3422015-11-20 Matthew Wahab <matthew.wahab@arm.com>
343
344 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
345 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
346 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
347 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
348 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
349 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
350 cnthv_ctl_el2, cnthv_cval_el2.
351 (aarch64_sys_reg_supported_p): Update for the new system
352 registers.
353
a915c10f
NC		 3542015-11-20 Nick Clifton <nickc@redhat.com>
355
356 PR binutils/19224
357 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
358
f8c2a965
NC		 3592015-11-20 Nick Clifton <nickc@redhat.com>
360
361 * po/zh_CN.po: Updated simplified Chinese translation.
362
c2825638
MW		 3632015-11-19 Matthew Wahab <matthew.wahab@arm.com>
364
365 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
366 of MSR PAN immediate operand.
367
e7286c56
NC		 3682015-11-16 Nick Clifton <nickc@redhat.com>
369
370 * rx-dis.c (condition_names): Replace always and never with
371 invalid, since the always/never conditions can never be legal.
372
d8bd95ef
TG		 3732015-11-13 Tristan Gingold <gingold@adacore.com>
374
375 * configure: Regenerate.
376
a680de9a
PB		 3772015-11-11 Alan Modra <amodra@gmail.com>
378 Peter Bergner <bergner@vnet.ibm.com>
379
380 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
381 Add PPC_OPCODE_VSX3 to the vsx entry.
382 (powerpc_init_dialect): Set default dialect to power9.
383 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
384 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
385 extract_l1 insert_xtq6, extract_xtq6): New static functions.
386 (insert_esync): Test for illegal L operand value.
387 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
388 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
389 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
390 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
391 PPCVSX3): New defines.
392 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
393 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
394 <mcrxr>: Use XBFRARB_MASK.
395 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
396 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
397 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
398 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
399 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
400 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
401 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
402 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
403 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
404 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
405 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
406 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
407 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
408 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
409 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
410 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
411 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
412 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
413 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
414 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
415 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
416 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
417 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
418 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
419 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
420 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
421 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
422 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
423 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
424 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
425 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
426 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
427
854eb72b
NC		 4282015-11-02 Nick Clifton <nickc@redhat.com>
429
430 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
431 instructions.
432 * rx-decode.c: Regenerate.
433
e292aa7a
NC		 4342015-11-02 Nick Clifton <nickc@redhat.com>
435
436 * rx-decode.opc (rx_disp): If the displacement is zero, set the
437 type to RX_Operand_Zero_Indirect.
438 * rx-decode.c: Regenerate.
439 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
440
43cdf5ae
YQ		 4412015-10-28 Yao Qi <yao.qi@linaro.org>
442
443 * aarch64-dis.c (aarch64_decode_insn): Add one argument
444 noaliases_p. Update comments. Pass noaliases_p rather than
445 no_aliases to aarch64_opcode_decode.
446 (print_insn_aarch64_word): Pass no_aliases to
447 aarch64_decode_insn.
448
c2f28758
VK		 4492015-10-27 Vinay <Vinay.G@kpit.com>
450
451 PR binutils/19159
452 * rl78-decode.opc (MOV): Added offset to DE register in index
453 addressing mode.
454 * rl78-decode.c: Regenerate.
455
46662804
VK		 4562015-10-27 Vinay Kumar <vinay.g@kpit.com>
457
458 PR binutils/19158
459 * rl78-decode.opc: Add 's' print operator to instructions that
460 access system registers.
461 * rl78-decode.c: Regenerate.
462 * rl78-dis.c (print_insn_rl78_common): Decode all system
463 registers.
464
02f12cd4
VK		 4652015-10-27 Vinay Kumar <vinay.g@kpit.com>
466
467 PR binutils/19157
468 * rl78-decode.opc: Add 'a' print operator to mov instructions
469 using stack pointer plus index addressing.
470 * rl78-decode.c: Regenerate.
471
485f23cf
AK		 4722015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
473
474 * s390-opc.c: Fix comment.
475 * s390-opc.txt: Change instruction type for troo, trot, trto, and
476 trtt to RRF_U0RER since the second parameter does not need to be a
477 register pair.
478
3f94e60d
NC		 4792015-10-08 Nick Clifton <nickc@redhat.com>
480
481 * arc-dis.c (print_insn_arc): Initiallise insn array.
482
875880c6
YQ		 4832015-10-07 Yao Qi <yao.qi@linaro.org>
484
485 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
486 'name' rather than 'template'.
487 * aarch64-opc.c (aarch64_print_operand): Likewise.
488
886a2506
NC		 4892015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
490
491 * arc-dis.c: Revamped file for ARC support
492 * arc-dis.h: Likewise.
493 * arc-ext.c: Likewise.
494 * arc-ext.h: Likewise.
495 * arc-opc.c: Likewise.
496 * arc-fxi.h: New file.
497 * arc-regs.h: Likewise.
498 * arc-tbl.h: Likewise.
499
36f4aab1
YQ		 5002015-10-02 Yao Qi <yao.qi@linaro.org>
501
502 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
503 argument insn type to aarch64_insn. Rename to ...
504 (aarch64_decode_insn): ... it.
505 (print_insn_aarch64_word): Caller updated.
506
7232d389
YQ		 5072015-10-02 Yao Qi <yao.qi@linaro.org>
508
509 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
510 (print_insn_aarch64_word): Caller updated.
511
7ecc513a
DV		 5122015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
513
514 * s390-mkopc.c (main): Parse htm and vx flag.
515 * s390-opc.txt: Mark instructions from the hardware transactional
516 memory and vector facilities with the "htm"/"vx" flag.
517
b08b78e7
NC		 5182015-09-28 Nick Clifton <nickc@redhat.com>
519
520 * po/de.po: Updated German translation.
521
36f7a941
TR		 5222015-09-28 Tom Rix <tom@bumblecow.com>
523
524 * ppc-opc.c (PPC500): Mark some opcodes as invalid
525
b6518b38
NC		 5262015-09-23 Nick Clifton <nickc@redhat.com>
527
528 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
529 function.
530 * tic30-dis.c (print_branch): Likewise.
531 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
532 value before left shifting.
533 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
534 * hppa-dis.c (print_insn_hppa): Likewise.
535 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
536 array.
537 * msp430-dis.c (msp430_singleoperand): Likewise.
538 (msp430_doubleoperand): Likewise.
539 (print_insn_msp430): Likewise.
540 * nds32-asm.c (parse_operand): Likewise.
541 * sh-opc.h (MASK): Likewise.
542 * v850-dis.c (get_operand_value): Likewise.
543
f04265ec
NC		 5442015-09-22 Nick Clifton <nickc@redhat.com>
545
546 * rx-decode.opc (bwl): Use RX_Bad_Size.
547 (sbwl): Likewise.
548 (ubwl): Likewise. Rename to ubw.
549 (uBWL): Rename to uBW.
550 Replace all references to uBWL with uBW.
551 * rx-decode.c: Regenerate.
552 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
553 (opsize_names): Likewise.
554 (print_insn_rx): Detect and report RX_Bad_Size.
555
6dca4fd1
AB		 5562015-09-22 Anton Blanchard <anton@samba.org>
557
558 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
559
38074311
JM		 5602015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
561
562 * sparc-dis.c (print_insn_sparc): Handle the privileged register
563 %pmcdper.
564
5f40e14d
JS		 5652015-08-24 Jan Stancek <jstancek@redhat.com>
566
567 * i386-dis.c (print_insn): Fix decoding of three byte operands.
568
ab4e4ed5
AF		 5692015-08-21 Alexander Fomin <alexander.fomin@intel.com>
570
571 PR binutils/18257
572 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
573 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
574 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
575 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
576 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
577 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
578 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
579 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
580 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
581 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
582 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
583 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
584 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
585 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
586 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
587 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
588 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
589 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
590 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
591 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
592 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
593 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
594 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
595 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
596 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
597 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
598 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
599 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
600 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
601 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
602 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
603 (vex_w_table): Replace terminals with MOD_TABLE entries for
604 most of mask instructions.
605
919b75f7
AM		 6062015-08-17 Alan Modra <amodra@gmail.com>
607
608 * cgen.sh: Trim trailing space from cgen output.
609 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
610 (print_dis_table): Likewise.
611 * opc2c.c (dump_lines): Likewise.
612 (orig_filename): Warning fix.
613 * ia64-asmtab.c: Regenerate.
614
4ab90a7a
AV		 6152015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
616
617 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
618 and higher with ARM instruction set will now mark the 26-bit
619 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
620 (arm_opcodes): Fix for unpredictable nop being recognized as a
621 teq.
622
40fc1451
SD		 6232015-08-12 Simon Dardis <simon.dardis@imgtec.com>
624
625 * micromips-opc.c (micromips_opcodes): Re-order table so that move
626 based on 'or' is first.
627 * mips-opc.c (mips_builtin_opcodes): Ditto.
628
922c5db5
NC		 6292015-08-11 Nick Clifton <nickc@redhat.com>
630
631 PR 18800
632 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
633 instruction.
634
75fb7498
RS		 6352015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
636
637 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
638
36aed29d
AP		 6392015-08-07 Amit Pawar <Amit.Pawar@amd.com>
640
641 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
642 * i386-init.h: Regenerated.
643
a8484f96
L		 6442015-07-30 H.J. Lu <hongjiu.lu@intel.com>
645
646 PR binutils/13571
647 * i386-dis.c (MOD_0FC3): New.
648 (PREFIX_0FC3): Renamed to ...
649 (PREFIX_MOD_0_0FC3): This.
650 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
651 (prefix_table): Replace Ma with Ev on movntiS.
652 (mod_table): Add MOD_0FC3.
653
37a42ee9
L		 6542015-07-27 H.J. Lu <hongjiu.lu@intel.com>
655
656 * configure: Regenerated.
657
070fe95d
AM		 6582015-07-23 Alan Modra <amodra@gmail.com>
659
660 PR 18708
661 * i386-dis.c (get64): Avoid signed integer overflow.
662
20c2a615
L		 6632015-07-22 Alexander Fomin <alexander.fomin@intel.com>
664
665 PR binutils/18631
666 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
667 "EXEvexHalfBcstXmmq" for the second operand.
668 (EVEX_W_0F79_P_2): Likewise.
669 (EVEX_W_0F7A_P_2): Likewise.
670 (EVEX_W_0F7B_P_2): Likewise.
671
6f1c2142
AM		 6722015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
673
674 * arm-dis.c (print_insn_coprocessor): Added support for quarter
675 float bitfield format.
676 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
677 quarter float bitfield format.
678
8a643cc3
L		 6792015-07-14 H.J. Lu <hongjiu.lu@intel.com>
680
681 * configure: Regenerated.
682
ef5a96d5
AM		 6832015-07-03 Alan Modra <amodra@gmail.com>
684
685 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
686 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
687 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
688
c8c8175b
SL		 6892015-07-01 Sandra Loosemore <sandra@codesourcery.com>
690 Cesar Philippidis <cesar@codesourcery.com>
691
692 * nios2-dis.c (nios2_extract_opcode): New.
693 (nios2_disassembler_state): New.
694 (nios2_find_opcode_hash): Use mach parameter to select correct
695 disassembler state.
696 (nios2_print_insn_arg): Extend to support new R2 argument letters
697 and formats.
698 (print_insn_nios2): Check for 16-bit instruction at end of memory.
699 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
700 (NIOS2_NUM_OPCODES): Rename to...
701 (NIOS2_NUM_R1_OPCODES): This.
702 (nios2_r2_opcodes): New.
703 (NIOS2_NUM_R2_OPCODES): New.
704 (nios2_num_r2_opcodes): New.
705 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
706 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
707 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
708 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
709 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
710
9916071f
AP		 7112015-06-30 Amit Pawar <Amit.Pawar@amd.com>
712
713 * i386-dis.c (OP_Mwaitx): New.
714 (rm_table): Add monitorx/mwaitx.
715 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
716 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
717 (operand_type_init): Add CpuMWAITX.
718 * i386-opc.h (CpuMWAITX): New.
719 (i386_cpu_flags): Add cpumwaitx.
720 * i386-opc.tbl: Add monitorx and mwaitx.
721 * i386-init.h: Regenerated.
722 * i386-tbl.h: Likewise.
723
7b934113
PB		 7242015-06-22 Peter Bergner <bergner@vnet.ibm.com>
725
726 * ppc-opc.c (insert_ls): Test for invalid LS operands.
727 (insert_esync): New function.
728 (LS, WC): Use insert_ls.
729 (ESYNC): Use insert_esync.
730
bdc4de1b
NC		 7312015-06-22 Nick Clifton <nickc@redhat.com>
732
733 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
734 requested region lies beyond it.
735 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
736 looking for 32-bit insns.
737 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
738 data.
739 * sh-dis.c (print_insn_sh): Likewise.
740 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
741 blocks of instructions.
742 * vax-dis.c (print_insn_vax): Check that the requested address
743 does not clash with the stop_vma.
744
11a0cf2e
PB		 7452015-06-19 Peter Bergner <bergner@vnet.ibm.com>
746
070fe95d 747 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 748 * ppc-opc.c (FXM4): Add non-zero optional value.
749 (TBR): Likewise.
750 (SXL): Likewise.
751 (insert_fxm): Handle new default operand value.
752 (extract_fxm): Likewise.
753 (insert_tbr): Likewise.
754 (extract_tbr): Likewise.
755
bdfa8b95
MW		 7562015-06-16 Matthew Wahab <matthew.wahab@arm.com>
757
758 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
759
24b4cf66
SN		 7602015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
761
762 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
763
99a2c561
PB		 7642015-06-12 Peter Bergner <bergner@vnet.ibm.com>
765
766 * ppc-opc.c: Add comment accidentally removed by old commit.
767 (MTMSRD_L): Delete.
768
40f77f82
AM		 7692015-06-04 Peter Bergner <bergner@vnet.ibm.com>
770
771 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
772
13be46a2
NC		 7732015-06-04 Nick Clifton <nickc@redhat.com>
774
775 PR 18474
776 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
777
ddfded2f
MW		 7782015-06-02 Matthew Wahab <matthew.wahab@arm.com>
779
780 * arm-dis.c (arm_opcodes): Add "setpan".
781 (thumb_opcodes): Add "setpan".
782
1af1dd51
MW		 7832015-06-02 Matthew Wahab <matthew.wahab@arm.com>
784
785 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
786 macros.
787
9e1f0fa7
MW		 7882015-06-02 Matthew Wahab <matthew.wahab@arm.com>
789
790 * aarch64-tbl.h (aarch64_feature_rdma): New.
791 (RDMA): New.
792 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
793 * aarch64-asm-2.c: Regenerate.
794 * aarch64-dis-2.c: Regenerate.
795 * aarch64-opc-2.c: Regenerate.
796
290806fd
MW		 7972015-06-02 Matthew Wahab <matthew.wahab@arm.com>
798
799 * aarch64-tbl.h (aarch64_feature_lor): New.
800 (LOR): New.
801 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
802 "stllrb", "stllrh".
803 * aarch64-asm-2.c: Regenerate.
804 * aarch64-dis-2.c: Regenerate.
805 * aarch64-opc-2.c: Regenerate.
806
f21cce2c
MW		 8072015-06-01 Matthew Wahab <matthew.wahab@arm.com>
808
809 * aarch64-opc.c (F_ARCHEXT): New.
810 (aarch64_sys_regs): Add "pan".
811 (aarch64_sys_reg_supported_p): New.
812 (aarch64_pstatefields): Add "pan".
813 (aarch64_pstatefield_supported_p): New.
814
d194d186
JB		 8152015-06-01 Jan Beulich <jbeulich@suse.com>
816
817 * i386-tbl.h: Regenerate.
818
3a8547d2
JB		 8192015-06-01 Jan Beulich <jbeulich@suse.com>
820
821 * i386-dis.c (print_insn): Swap rounding mode specifier and
822 general purpose register in Intel mode.
823
015c54d5
JB		 8242015-06-01 Jan Beulich <jbeulich@suse.com>
825
826 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
827 * i386-tbl.h: Regenerate.
828
071f0063
L		 8292015-05-18 H.J. Lu <hongjiu.lu@intel.com>
830
831 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
832 * i386-init.h: Regenerated.
833
5db04b09
L		 8342015-05-15 H.J. Lu <hongjiu.lu@intel.com>
835
836 PR binutis/18386
837 * i386-dis.c: Add comments for '@'.
838 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
839 (enum x86_64_isa): New.
840 (isa64): Likewise.
841 (print_i386_disassembler_options): Add amd64 and intel64.
842 (print_insn): Handle amd64 and intel64.
843 (putop): Handle '@'.
844 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
845 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
846 * i386-opc.h (AMD64): New.
847 (CpuIntel64): Likewise.
848 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
849 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
850 Mark direct call/jmp without Disp16|Disp32 as Intel64.
851 * i386-init.h: Regenerated.
852 * i386-tbl.h: Likewise.
853
4bc0608a
PB		 8542015-05-14 Peter Bergner <bergner@vnet.ibm.com>
855
856 * ppc-opc.c (IH) New define.
857 (powerpc_opcodes) <wait>: Do not enable for POWER7.
858 <tlbie>: Add RS operand for POWER7.
859 <slbia>: Add IH operand for POWER6.
860
70cead07
L		 8612015-05-11 H.J. Lu <hongjiu.lu@intel.com>
862
331e6131 863 * i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
70cead07
L		 864 direct branch.
865 (jmp): Likewise.
866 * i386-tbl.h: Regenerated.
867
7b6d09fb
L		 8682015-05-11 H.J. Lu <hongjiu.lu@intel.com>
869
870 * configure.ac: Support bfd_iamcu_arch.
871 * disassemble.c (disassembler): Support bfd_iamcu_arch.
872 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
873 CPU_IAMCU_COMPAT_FLAGS.
874 (cpu_flags): Add CpuIAMCU.
875 * i386-opc.h (CpuIAMCU): New.
876 (i386_cpu_flags): Add cpuiamcu.
877 * configure: Regenerated.
878 * i386-init.h: Likewise.
879 * i386-tbl.h: Likewise.
880
31955f99
L		 8812015-05-08 H.J. Lu <hongjiu.lu@intel.com>
882
883 PR binutis/18386
884 * i386-dis.c (X86_64_E8): New.
885 (X86_64_E9): Likewise.
886 Update comments on 'T', 'U', 'V'. Add comments for '^'.
887 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
888 (x86_64_table): Add X86_64_E8 and X86_64_E9.
889 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
890 (putop): Handle '^'.
891 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
892 REX_W.
893
0952813b
DD		 8942015-04-30 DJ Delorie <dj@redhat.com>
895
896 * disassemble.c (disassembler): Choose suitable disassembler based
897 on E_ABI.
898 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
899 it to decode mul/div insns.
900 * rl78-decode.c: Regenerate.
901 * rl78-dis.c (print_insn_rl78): Rename to...
902 (print_insn_rl78_common): ...this, take ISA parameter.
903 (print_insn_rl78): New.
904 (print_insn_rl78_g10): New.
905 (print_insn_rl78_g13): New.
906 (print_insn_rl78_g14): New.
907 (rl78_get_disassembler): New.
908
f9d3ecaa
NC		 9092015-04-29 Nick Clifton <nickc@redhat.com>
910
911 * po/fr.po: Updated French translation.
912
4fff86c5
PB		 9132015-04-27 Peter Bergner <bergner@vnet.ibm.com>
914
915 * ppc-opc.c (DCBT_EO): New define.
916 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
917 <lharx>: Likewise.
918 <stbcx.>: Likewise.
919 <sthcx.>: Likewise.
920 <waitrsv>: Do not enable for POWER7 and later.
921 <waitimpl>: Likewise.
922 <dcbt>: Default to the two operand form of the instruction for all
923 "old" cpus. For "new" cpus, use the operand ordering that matches
924 whether the cpu is server or embedded.
925 <dcbtst>: Likewise.
926
3b78cfe1
AK		 9272015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
928
929 * s390-opc.c: New instruction type VV0UU2.
930 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
931 and WFC.
932
04d824a4
JB		 9332015-04-23 Jan Beulich <jbeulich@suse.com>
934
935 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
936 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
937 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
938 (vfpclasspd, vfpclassps): Add %XZ.
939
09708981
L		 9402015-04-15 H.J. Lu <hongjiu.lu@intel.com>
941
942 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
943 (PREFIX_UD_REPZ): Likewise.
944 (PREFIX_UD_REPNZ): Likewise.
945 (PREFIX_UD_DATA): Likewise.
946 (PREFIX_UD_ADDR): Likewise.
947 (PREFIX_UD_LOCK): Likewise.
948
3888916d
L		 9492015-04-15 H.J. Lu <hongjiu.lu@intel.com>
950
951 * i386-dis.c (prefix_requirement): Removed.
952 (print_insn): Don't set prefix_requirement. Check
953 dp->prefix_requirement instead of prefix_requirement.
954
f24bcbaa
L		 9552015-04-15 H.J. Lu <hongjiu.lu@intel.com>
956
957 PR binutils/17898
958 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
959 (PREFIX_MOD_0_0FC7_REG_6): This.
960 (PREFIX_MOD_3_0FC7_REG_6): New.
961 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
962 (prefix_table): Replace PREFIX_0FC7_REG_6 with
963 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
964 PREFIX_MOD_3_0FC7_REG_7.
965 (mod_table): Replace PREFIX_0FC7_REG_6 with
966 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
967 PREFIX_MOD_3_0FC7_REG_7.
968
507bd325
L		 9692015-04-15 H.J. Lu <hongjiu.lu@intel.com>
970
971 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
972 (PREFIX_MANDATORY_REPNZ): Likewise.
973 (PREFIX_MANDATORY_DATA): Likewise.
974 (PREFIX_MANDATORY_ADDR): Likewise.
975 (PREFIX_MANDATORY_LOCK): Likewise.
976 (PREFIX_MANDATORY): Likewise.
977 (PREFIX_UD_SHIFT): Set to 8
978 (PREFIX_UD_REPZ): Updated.
979 (PREFIX_UD_REPNZ): Likewise.
980 (PREFIX_UD_DATA): Likewise.
981 (PREFIX_UD_ADDR): Likewise.
982 (PREFIX_UD_LOCK): Likewise.
983 (PREFIX_IGNORED_SHIFT): New.
984 (PREFIX_IGNORED_REPZ): Likewise.
985 (PREFIX_IGNORED_REPNZ): Likewise.
986 (PREFIX_IGNORED_DATA): Likewise.
987 (PREFIX_IGNORED_ADDR): Likewise.
988 (PREFIX_IGNORED_LOCK): Likewise.
989 (PREFIX_OPCODE): Likewise.
990 (PREFIX_IGNORED): Likewise.
991 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
992 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
993 (three_byte_table): Likewise.
994 (mod_table): Likewise.
995 (mandatory_prefix): Renamed to ...
996 (prefix_requirement): This.
997 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
998 Update PREFIX_90 entry.
999 (get_valid_dis386): Check prefix_requirement to see if a prefix
1000 should be ignored.
1001 (print_insn): Replace mandatory_prefix with prefix_requirement.
1002
f0fba320
RL		 10032015-04-15 Renlin Li <renlin.li@arm.com>
1004
1005 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
1006 use it for ssat and ssat16.
1007 (print_insn_thumb32): Add handle case for 'D' control code.
1008
bf890a93
IT		 10092015-04-06 Ilya Tocar <ilya.tocar@intel.com>
1010 H.J. Lu <hongjiu.lu@intel.com>
1011
1012 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
1013 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
1014 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
1015 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
1016 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
1017 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
1018 Fill prefix_requirement field.
1019 (struct dis386): Add prefix_requirement field.
1020 (dis386): Fill prefix_requirement field.
1021 (dis386_twobyte): Ditto.
1022 (twobyte_has_mandatory_prefix_: Remove.
1023 (reg_table): Fill prefix_requirement field.
1024 (prefix_table): Ditto.
1025 (x86_64_table): Ditto.
1026 (three_byte_table): Ditto.
1027 (xop_table): Ditto.
1028 (vex_table): Ditto.
1029 (vex_len_table): Ditto.
1030 (vex_w_table): Ditto.
1031 (mod_table): Ditto.
1032 (bad_opcode): Ditto.
1033 (print_insn): Use prefix_requirement.
1034 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
1035 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
1036 (float_reg): Ditto.
1037
2f783c1f
MF		 10382015-03-30 Mike Frysinger <vapier@gentoo.org>
1039
1040 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
1041
b9d94d62
L		 10422015-03-29 H.J. Lu <hongjiu.lu@intel.com>
1043
1044 * Makefile.in: Regenerated.
1045
27c49e9a
AB		 10462015-03-25 Anton Blanchard <anton@samba.org>
1047
1048 * ppc-dis.c (disassemble_init_powerpc): Only initialise
1049 powerpc_opcd_indices and vle_opcd_indices once.
1050
c4e676f1
AB		 10512015-03-25 Anton Blanchard <anton@samba.org>
1052
1053 * ppc-opc.c (powerpc_opcodes): Add slbfee.
1054
823d2571
TG		 10552015-03-24 Terry Guo <terry.guo@arm.com>
1056
1057 * arm-dis.c (opcode32): Updated to use new arm feature struct.
1058 (opcode16): Likewise.
1059 (coprocessor_opcodes): Replace bit with feature struct.
1060 (neon_opcodes): Likewise.
1061 (arm_opcodes): Likewise.
1062 (thumb_opcodes): Likewise.
1063 (thumb32_opcodes): Likewise.
1064 (print_insn_coprocessor): Likewise.
1065 (print_insn_arm): Likewise.
1066 (select_arm_features): Follow new feature struct.
1067
029f3522
GG		 10682015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
1069
1070 * i386-dis.c (rm_table): Add clzero.
1071 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
1072 Add CPU_CLZERO_FLAGS.
1073 (cpu_flags): Add CpuCLZERO.
1074 * i386-opc.h: Add CpuCLZERO.
1075 * i386-opc.tbl: Add clzero.
1076 * i386-init.h: Re-generated.
1077 * i386-tbl.h: Re-generated.
1078
6914869a
AB		 10792015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1080
1081 * mips-opc.c (decode_mips_operand): Fix constraint issues
1082 with u and y operands.
1083
21e20815
AB		 10842015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1085
1086 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1087
6b1d7593
AK		 10882015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1089
1090 * s390-opc.c: Add new IBM z13 instructions.
1091 * s390-opc.txt: Likewise.
1092
c8f89a34
JW		 10932015-03-10 Renlin Li <renlin.li@arm.com>
1094
1095 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1096 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1097 related alias.
1098 * aarch64-asm-2.c: Regenerate.
1099 * aarch64-dis-2.c: Likewise.
1100 * aarch64-opc-2.c: Likewise.
1101
d8282f0e
JW		 11022015-03-03 Jiong Wang <jiong.wang@arm.com>
1103
1104 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1105
ac994365
OE		 11062015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
1107
1108 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1109 arch_sh_up.
1110 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1111 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1112
fd63f640
V		 11132015-02-23 Vinay <Vinay.G@kpit.com>
1114
1115 * rl78-decode.opc (MOV): Added space between two operands for
1116 'mov' instruction in index addressing mode.
1117 * rl78-decode.c: Regenerate.
1118
f63c1776
PA		 11192015-02-19 Pedro Alves <palves@redhat.com>
1120
1121 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1122
07774fcc
PA		 11232015-02-10 Pedro Alves <palves@redhat.com>
1124 Tom Tromey <tromey@redhat.com>
1125
1126 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1127 microblaze_and, microblaze_xor.
1128 * microblaze-opc.h (opcodes): Adjust.
1129
3f8107ab
AM		 11302015-01-28 James Bowman <james.bowman@ftdichip.com>
1131
1132 * Makefile.am: Add FT32 files.
1133 * configure.ac: Handle FT32.
1134 * disassemble.c (disassembler): Call print_insn_ft32.
1135 * ft32-dis.c: New file.
1136 * ft32-opc.c: New file.
1137 * Makefile.in: Regenerate.
1138 * configure: Regenerate.
1139 * po/POTFILES.in: Regenerate.
1140
e5fe4957
KLC		 11412015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1142
1143 * nds32-asm.c (keyword_sr): Add new system registers.
1144
1e2e8c52
AK		 11452015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1146
1147 * s390-dis.c (s390_extract_operand): Support vector register
1148 operands.
1149 (s390_print_insn_with_opcode): Support new operands types and add
1150 new handling of optional operands.
1151 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1152 and include opcode/s390.h instead.
1153 (struct op_struct): New field `flags'.
1154 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1155 (dumpTable): Dump flags.
1156 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1157 string.
1158 * s390-opc.c: Add new operands types, instruction formats, and
1159 instruction masks.
1160 (s390_opformats): Add new formats for .insn.
1161 * s390-opc.txt: Add new instructions.
1162
b90efa5b 11632015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 1164
b90efa5b 1165 Update year range in copyright notice of all files.
bffb6004 1166
b90efa5b 1167For older changes see ChangeLog-2014
252b5132 1168\f
b90efa5b 1169Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 1170
1171Copying and distribution of this file, with or without modification,
1172are permitted in any medium without royalty provided the copyright
1173notice and this notice are preserved.
1174
252b5132 1175Local Variables:
2f6d2f85
NC		 1176mode: change-log
1177left-margin: 8
1178fill-column: 74
252b5132
RH		 1179version-control: never
1180End:
GDB Binutils - Deliverables
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