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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
8e295ce0
NC		 12010-11-10 Nick Clifton <nickc@redhat.com>
2
3 * po/fi.po: Updated Finnish translation.
4
2ee0aedf
TG		 52010-11-05 Tristan Gingold <gingold@adacore.com>
6
7 * po/opcodes.pot: Regenerate
8
af478898
MR		 92010-10-28 Maciej W. Rozycki <macro@codesourcery.com>
10
11 * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".
12
be7a250d
AK		 132010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
14
15 * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
16
d958d1a3
CF		 172010-10-25 Chao-ying Fu <fu@mips.com>
18
19 * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
20
c0621d88
NS		 212010-10-25 Nathan Sidwell <nathan@codesourcery.com>
22
23 * tic6x-dis.c: Add attribution.
24
a43817df
AM		 252010-10-22 Alan Modra <amodra@gmail.com>
26
27 * Makefile.am (CLEANFILES): Add stamp-lm32. Sort.
28 * Makefile.in: Regenerate.
29
704897fb
MR		 302010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
31
32 * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
33 macros before their corresponding MIPS III hardware instructions.
34
da98bb4c
L		 352010-10-16 H.J. Lu <hongjiu.lu@intel.com>
36
37 * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
38
39 * i386-init.h: Regenerated.
40
e1791cb8
MF		 412010-10-15 Mike Frysinger <vapier@gentoo.org>
42
43 * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M.
44
553d0a74
L		 452010-10-14 H.J. Lu <hongjiu.lu@intel.com>
46
47 * i386-opc.tbl: Remove CheckRegSize from movq.
48 * i386-tbl.h: Regenerated.
49
cfc08d49
L		 502010-10-14 H.J. Lu <hongjiu.lu@intel.com>
51
52 * i386-opc.tbl: Remove CheckRegSize from instructions with
53 0, 1 or fixed operands.
54 * i386-tbl.h: Regenerated.
55
56ffb741
L		 562010-10-14 H.J. Lu <hongjiu.lu@intel.com>
57
58 * i386-gen.c (opcode_modifiers): Add CheckRegSize.
59
60 * i386-opc.h (CheckRegSize): New.
61 (i386_opcode_modifier): Add checkregsize.
62
63 * i386-opc.tbl: Add CheckRegSize to instructions which
64 require register size check.
65 * i386-tbl.h: Regenerated.
66
1a2dab1f
AS		 672010-10-12 Andreas Schwab <schwab@linux-m68k.org>
68
69 * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
70
a3ec2691
AK		 712010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
72
73 * s390-opc.c: Make the instruction masks for the load/store on
74 condition instructions to cover the condition code mask as well.
75 * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
76
d92fa646
JK		 772010-10-11 Jan Kratochvil <jan.kratochvil@redhat.com>
78 Jiang Jilin <freephp@gmail.com>
79
80 * Makefile.am (libopcodes_a_SOURCES): New as empty.
81 * Makefile.in: Regenerate.
82
4469d2be
AM		 832010-10-09 Matt Rice <ratmice@gmail.com>
84
85 * fr30-desc.h: Regenerate.
86 * frv-desc.h: Regenerate.
87 * ip2k-desc.h: Regenerate.
88 * iq2000-desc.h: Regenerate.
89 * lm32-desc.h: Regenerate.
90 * m32c-desc.h: Regenerate.
91 * m32r-desc.h: Regenerate.
92 * mep-desc.h: Regenerate.
93 * mep-opc.c: Regenerate.
94 * mt-desc.h: Regenerate.
95 * openrisc-desc.h: Regenerate.
96 * xc16x-desc.h: Regenerate.
97 * xstormy16-desc.h: Regenerate.
98
9ccb8af9
AM		 992010-10-08 Pierre Muller <muller@ics.u-strasbg.fr>
100
101 Fix build with -DDEBUG=7
102 * frv-opc.c: Regenerate.
103 * or32-dis.c (DEBUG): Don't redefine.
104 (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
105 Adapt DEBUG code to some type changes throughout.
106 * or32-opc.c (or32_extract): Likewise.
107
5d4c71e1
BS		 1082010-10-07 Bernd Schmidt <bernds@codesourcery.com>
109
110 * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
111 in SPKERNEL instructions.
112
9ce00134
L		 1132010-10-02 H.J. Lu <hongjiu.lu@intel.com>
114
115 PR binutils/12076
116 * i386-dis.c (RMAL): Remove duplicate.
117
e7390eec
PM		 1182010-09-30 Pierre Muller <muller@ics.u-strasbg.fr>
119
120 * s390-mkopc.c (main): Exit with error 1 if sscanf fails
121 to parse all 6 parameters.
122
d2ae9c84
PM		 1232010-09-28 Pierre Muller <muller@ics.u-strasbg.fr>
124
125 * s390-mkopc.c (main): Change description array size to 80.
126 Add maximum length of 79 to description parsing.
127
3cac54d2
RW		 1282010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
129
130 * configure: Regenerate.
131
d9aee5d7
AK		 1322010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
133
134 * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
135 (main): Recognize the new CPU string.
136 * s390-opc.c: Add new instruction formats and masks.
137 * s390-opc.txt: Add new z196 instructions.
138
02cbf767
AK		 1392010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
140
141 * s390-dis.c (print_insn_s390): Pick instruction with most
142 specific mask.
143 * s390-opc.c: Add unused bits to the insn mask.
144 * s390-opc.txt: Reorder some instructions to prefer more recent
145 versions.
146
6844b2c2
MGD		 1472010-09-27 Tejas Belagod <tejas.belagod@arm.com>
148
149 * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
150 correction to unaligned PCs while printing comment.
151
90ec0d68
MGD		 1522010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
153
154 * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
155 (thumb32_opcodes): Likewise.
156 (banked_regname): New function.
157 (print_insn_arm): Add Virtualization Extensions support.
158 (print_insn_thumb32): Likewise.
159
eea54501
MGD		 1602010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
161
162 * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
163 ARM state.
164
f4c65163
MGD		 1652010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
166
167 * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
168 (thumb32_opcodes): Likewise.
169
60e5ef9f
MGD		 1702010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
171
172 * arm-dis.c (arm_opcodes): Add support for pldw.
173 (thumb32_opcodes): Likewise.
174
7a360e83
MF		 1752010-09-22 Robin Getz <robin.getz@analog.com>
176
177 * bfin-dis.c (fmtconst): Cast address to 32bits.
178
35fc57f3
MF		 1792010-09-22 Mike Frysinger <vapier@gentoo.org>
180
181 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
182
219b747a
MF		 1832010-09-22 Robin Getz <robin.getz@analog.com>
184
185 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
186 Reject P6/P7 to TESTSET.
187 (decode_PushPopReg_0): Check for parallel insns. Reject pushing
188 SP onto the stack.
189 (decode_PushPopMultiple_0): Check for parallel insns. Make sure
190 P/D fields match all the time.
191 (decode_CCflag_0): Check for parallel insns. Verify x/y fields
192 are 0 for accumulator compares.
193 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
194 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
195 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
196 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
197 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
198 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
199 insns.
200 (decode_dagMODim_0): Verify br field for IREG ops.
201 (decode_LDST_0): Reject preg load into same preg.
202 (_print_insn_bfin): Handle returns for ILLEGAL decodes.
203 (print_insn_bfin): Likewise.
204
775f1cf0
MF		 2052010-09-22 Mike Frysinger <vapier@gentoo.org>
206
207 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
208
0b7691fd
MF		 2092010-09-22 Robin Getz <robin.getz@analog.com>
210
211 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
212
b2459327
MF		 2132010-09-22 Mike Frysinger <vapier@gentoo.org>
214
215 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
216
50e2162a
MF		 2172010-09-22 Robin Getz <robin.getz@analog.com>
218
219 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
220 register values greater than 8.
221 (IS_RESERVEDREG, allreg, mostreg): New helpers.
222 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
223 (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
224 (decode_CC2dreg_0): Check valid CC register number.
225
a01eda85
MF		 2262010-09-22 Robin Getz <robin.getz@analog.com>
227
228 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
229
22215ae0
MF		 2302010-09-22 Robin Getz <robin.getz@analog.com>
231
232 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
233 (reg_names): Likewise.
234 (decode_statbits): Likewise; while reformatting to make manageable.
235
73a63ccf
MF		 2362010-09-22 Mike Frysinger <vapier@gentoo.org>
237
238 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
239 (decode_pseudoOChar_0): New function.
240 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
241
59a82d23
MF		 2422010-09-22 Robin Getz <robin.getz@analog.com>
243
244 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
245 LSHIFT instead of SHIFT.
246
528c6277
MF		 2472010-09-22 Mike Frysinger <vapier@gentoo.org>
248
249 * bfin-dis.c (constant_formats): Constify the whole structure.
250 (fmtconst): Add const to return value.
251 (reg_names): Mark const.
252 (decode_multfunc): Mark s0/s1 as const.
253 (decode_macfunc): Mark a/sop as const.
254
db472d6f
MGD		 2552010-09-17 Tejas Belagod <tejas.belagod@arm.com>
256
257 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
258
f6690563
MR		 2592010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
260
261 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
262 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
263
8901a3cd
PM		 2642010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
265
266 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
267 dlx_insn_type array.
268
d9e3625e
L		 2692010-08-31 H.J. Lu <hongjiu.lu@intel.com>
270
271 PR binutils/11960
272 * i386-dis.c (sIv): New.
273 (dis386): Replace Iq with sIv on "pushT".
274 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
4469d2be 275 (x86_64_table): Replace {T|}/{P|} with P.
d9e3625e
L		 276 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
277 (OP_sI): Update v_mode. Remove w_mode.
278
f383de66
NF		 2792010-08-27 Nathan Froyd <froydnj@codesourcery.com>
280
281 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
282 on E500 and E500MC.
283
1ab03f4b
L		 2842010-08-17 H.J. Lu <hongjiu.lu@intel.com>
285
286 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
287 prefetchw.
288
22109423
L		 2892010-08-06 Quentin Neill <quentin.neill@amd.com>
290
291 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
292 to processor flags for PENTIUMPRO processors and later.
293 * i386-opc.h (enum): Add CpuNop.
294 (i386_cpu_flags): Add cpunop bit.
295 * i386-opc.tbl: Change nop cpu_flags.
296 * i386-init.h: Regenerated.
297 * i386-tbl.h: Likewise.
298
b49dfb4a
L		 2992010-08-06 Quentin Neill <quentin.neill@amd.com>
300
301 * i386-opc.h (enum): Fix typos in comments.
302
6ca4eb77
AM		 3032010-08-06 Alan Modra <amodra@gmail.com>
304
305 * disassemble.c: Formatting.
306 (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
307
92d4d42e
L		 3082010-08-05 H.J. Lu <hongjiu.lu@intel.com>
309
310 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
311 * i386-tbl.h: Regenerated.
312
b414985b
L		 3132010-08-05 H.J. Lu <hongjiu.lu@intel.com>
314
315 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
316
317 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
318 * i386-tbl.h: Regenerated.
319
f9c7014e
DD		 3202010-07-29 DJ Delorie <dj@redhat.com>
321
322 * rx-decode.opc (SRR): New.
323 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
324 r0,r0) and NOP3 (max r0,r0) special cases.
325 * rx-decode.c: Regenerate.
6ca4eb77 326
592a252b
L		 3272010-07-28 H.J. Lu <hongjiu.lu@intel.com>
328
329 * i386-dis.c: Add 0F to VEX opcode enums.
330
3cf79a01
DD		 3312010-07-27 DJ Delorie <dj@redhat.com>
332
333 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
334 (rx_decode_opcode): Likewise.
335 * rx-decode.c: Regenerate.
336
1cd986c5
NC		 3372010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
338 Ina Pandit <ina.pandit@kpitcummins.com>
339
340 * v850-dis.c (v850_sreg_names): Updated structure for system
341 registers.
342 (float_cc_names): new structure for condition codes.
343 (print_value): Update the function that prints value.
344 (get_operand_value): New function to get the operand value.
345 (disassemble): Updated to handle the disassembly of instructions.
346 (print_insn_v850): Updated function to print instruction for different
347 families.
348 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
349 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
350 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
351 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
352 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
353 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
354 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
355 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
356 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
357 (v850_operands): Update with the relocation name. Also update
358 the instructions with specific set of processors.
359
52e7f43d
RE		 3602010-07-08 Tejas Belagod <tejas.belagod@arm.com>
361
362 * arm-dis.c (print_insn_arm): Add cases for printing more
363 symbolic operands.
364 (print_insn_thumb32): Likewise.
365
c680e7f6
MR		 3662010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
367
368 * mips-dis.c (print_insn_mips): Correct branch instruction type
369 determination.
370
9a2c7088
MR		 3712010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
372
373 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
374 type and delay slot determination.
375 (print_insn_mips16): Extend branch instruction type and delay
376 slot determination to cover all instructions.
377 * mips16-opc.c (BR): Remove macro.
378 (UBR, CBR): New macros.
379 (mips16_opcodes): Update branch annotation for "b", "beqz",
380 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
381 and "jrc".
382
d7d9a9f8
L		 3832010-07-05 H.J. Lu <hongjiu.lu@intel.com>
384
385 AVX Programming Reference (June, 2010)
386 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
387 * i386-opc.tbl: Likewise.
388 * i386-tbl.h: Regenerated.
389
77321f53
L		 3902010-07-05 H.J. Lu <hongjiu.lu@intel.com>
391
392 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
393
7102e95e
AS		 3942010-07-03 Andreas Schwab <schwab@linux-m68k.org>
395
396 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
397 ppc_cpu_t before inverting.
3a5530ea
AS		 398 (ppc_parse_cpu): Likewise.
399 (print_insn_powerpc): Likewise.
7102e95e 400
bdc70b4a
AM		 4012010-07-03 Alan Modra <amodra@gmail.com>
402
403 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
404 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
405 (PPC64, MFDEC2): Update.
406 (NON32, NO371): Define.
407 (powerpc_opcode): Update to not use old opcode flags, and avoid
408 -m601 duplicates.
409
21375995
DD		 4102010-07-03 DJ Delorie <dj@delorie.com>
411
412 * m32c-ibld.c: Regenerate.
413
81a0b7e2
AM		 4142010-07-03 Alan Modra <amodra@gmail.com>
415
416 * ppc-opc.c (PWR2COM): Define.
417 (PPCPWR2): Add PPC_OPCODE_COMMON.
418 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
419 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
420 "rac" from -mcom.
421
c7b8aa3a
L		 4222010-07-01 H.J. Lu <hongjiu.lu@intel.com>
423
424 AVX Programming Reference (June, 2010)
425 * i386-dis.c (PREFIX_0FAE_REG_0): New.
426 (PREFIX_0FAE_REG_1): Likewise.
427 (PREFIX_0FAE_REG_2): Likewise.
428 (PREFIX_0FAE_REG_3): Likewise.
429 (PREFIX_VEX_3813): Likewise.
430 (PREFIX_VEX_3A1D): Likewise.
431 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
432 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
433 PREFIX_VEX_3A1D.
434 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
435 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
436 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
437
438 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
439 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
440 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
441
442 * i386-opc.h (CpuXsaveopt): New.
77321f53 443 (CpuFSGSBase): Likewise.
c7b8aa3a
L		 444 (CpuRdRnd): Likewise.
445 (CpuF16C): Likewise.
446 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
447 cpuf16c.
448
449 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
450 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
a00eb5e8
L		 451 * i386-init.h: Regenerated.
452 * i386-tbl.h: Likewise.
c7b8aa3a 453
09a8ad8d
AM		 4542010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
455
456 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
457 and mtocrf on EFS.
458
360cfc9c
AM		 4592010-06-29 Alan Modra <amodra@gmail.com>
460
461 * maxq-dis.c: Delete file.
462 * Makefile.am: Remove references to maxq.
463 * configure.in: Likewise.
464 * disassemble.c: Likewise.
465 * Makefile.in: Regenerate.
466 * configure: Regenerate.
467 * po/POTFILES.in: Regenerate.
468
dc898d5e
AM		 4692010-06-29 Alan Modra <amodra@gmail.com>
470
471 * mep-dis.c: Regenerate.
472
8e560766
MGD		 4732010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
474
475 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
476
c7e2358a
AM		 4772010-06-27 Alan Modra <amodra@gmail.com>
478
479 * arc-dis.c (arc_sprintf): Delete set but unused variables.
480 (decodeInstr): Likewise.
481 * dlx-dis.c (print_insn_dlx): Likewise.
482 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
483 * maxq-dis.c (check_move, print_insn): Likewise.
484 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
485 * msp430-dis.c (msp430_branchinstr): Likewise.
486 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
487 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
488 * sparc-dis.c (print_insn_sparc): Likewise.
489 * fr30-asm.c: Regenerate.
490 * frv-asm.c: Regenerate.
491 * ip2k-asm.c: Regenerate.
492 * iq2000-asm.c: Regenerate.
493 * lm32-asm.c: Regenerate.
494 * m32c-asm.c: Regenerate.
495 * m32r-asm.c: Regenerate.
496 * mep-asm.c: Regenerate.
497 * mt-asm.c: Regenerate.
498 * openrisc-asm.c: Regenerate.
499 * xc16x-asm.c: Regenerate.
500 * xstormy16-asm.c: Regenerate.
501
6ffe3d99
NC		 5022010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
503
504 PR gas/11673
505 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
506
09ec0d17
NC		 5072010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
508
509 PR binutils/11676
510 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
511
e01d869a
AM		 5122010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
513
514 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
515 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
516 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
517 touch floating point regs and are enabled by COM, PPC or PPCCOM.
518 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
519 Treat lwsync as msync on e500.
520
1f4e4950
MGD		 5212010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
522
523 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
524
9d82ec38
MGD		 5252010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
526
e01d869a 527 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
9d82ec38
MGD		 528 constants is the same on 32-bit and 64-bit hosts.
529
c3a6ea62 5302010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
d8b24b95
NC		 531
532 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
533 .short directives so that they can be reassembled.
534
9db8dccb
CM		 5352010-05-26 Catherine Moore <clm@codesourcery.com>
536 David Ung <davidu@mips.com>
537
538 * mips-opc.c: Change membership to I1 for instructions ssnop and
539 ehb.
540
dfc8cf43
L		 5412010-05-26 H.J. Lu <hongjiu.lu@intel.com>
542
543 * i386-dis.c (sib): New.
544 (get_sib): Likewise.
545 (print_insn): Call get_sib.
546 OP_E_memory): Use sib.
547
f79e2745
CM		 5482010-05-26 Catherine Moore <clm@codesoourcery.com>
549
550 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
551 * mips-opc.c (I16): Remove.
552 (mips_builtin_op): Reclassify jalx.
553
51b5d4a8
AM		 5542010-05-19 Alan Modra <amodra@gmail.com>
555
556 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
557 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
558
85d4ac0b
AM		 5592010-05-13 Alan Modra <amodra@gmail.com>
560
561 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
562
4547cb56
NC		 5632010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
564
565 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
566 format.
567 (print_insn_thumb16): Add support for new %W format.
568
6540b386
TG		 5692010-05-07 Tristan Gingold <gingold@adacore.com>
570
571 * Makefile.in: Regenerate with automake 1.11.1.
572 * aclocal.m4: Ditto.
573
3e01a7fd
NC		 5742010-05-05 Nick Clifton <nickc@redhat.com>
575
576 * po/es.po: Updated Spanish translation.
577
9c9c98a5
NC		 5782010-04-22 Nick Clifton <nickc@redhat.com>
579
580 * po/opcodes.pot: Updated by the Translation project.
581 * po/vi.po: Updated Vietnamese translation.
582
f07af43e
L		 5832010-04-16 H.J. Lu <hongjiu.lu@intel.com>
584
585 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
586 bits in opcode.
587
3d540e93
NC		 5882010-04-09 Nick Clifton <nickc@redhat.com>
589
590 * i386-dis.c (print_insn): Remove unused variable op.
591 (OP_sI): Remove unused variable mask.
592
397841b5
AM		 5932010-04-07 Alan Modra <amodra@gmail.com>
594
595 * configure: Regenerate.
596
cee62821
PB		 5972010-04-06 Peter Bergner <bergner@vnet.ibm.com>
598
599 * ppc-opc.c (RBOPT): New define.
600 ("dccci"): Enable for PPCA2. Make operands optional.
601 ("iccci"): Likewise. Do not deprecate for PPC476.
602
accf4463
NC		 6032010-04-02 Masaki Muranaka <monaka@monami-software.com>
604
605 * cr16-opc.c (cr16_instruction): Fix typo in comment.
606
40b36596
JM		 6072010-03-25 Joseph Myers <joseph@codesourcery.com>
608
609 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
610 * Makefile.in: Regenerate.
611 * configure.in (bfd_tic6x_arch): New.
612 * configure: Regenerate.
613 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
614 (disassembler): Handle TI C6X.
615 * tic6x-dis.c: New.
616
1985c81c
MF		 6172010-03-24 Mike Frysinger <vapier@gentoo.org>
618
619 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
620
f66187fd
JM		 6212010-03-23 Joseph Myers <joseph@codesourcery.com>
622
623 * dis-buf.c (buffer_read_memory): Give error for reading just
624 before the start of memory.
625
ce7d077e
SP		 6262010-03-22 Sebastian Pop <sebastian.pop@amd.com>
627 Quentin Neill <quentin.neill@amd.com>
628
629 * i386-dis.c (OP_LWP_I): Removed.
630 (reg_table): Do not use OP_LWP_I, use Iq.
631 (OP_LWPCB_E): Remove use of names16.
632 (OP_LWP_E): Same.
633 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
634 should not set the Vex.length bit.
635 * i386-tbl.h: Regenerated.
636
63d0fa4e
AM		 6372010-02-25 Edmar Wienskoski <edmar@freescale.com>
638
639 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
640
c060226a
NC		 6412010-02-24 Nick Clifton <nickc@redhat.com>
642
643 PR binutils/6773
644 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
645 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
646 (thumb32_opcodes): Likewise.
647
ab7875de
NC		 6482010-02-15 Nick Clifton <nickc@redhat.com>
649
650 * po/vi.po: Updated Vietnamese translation.
651
fee1d3e8
DE		 6522010-02-12 Doug Evans <dje@sebabeach.org>
653
654 * lm32-opinst.c: Regenerate.
655
37ec9240
DE		 6562010-02-11 Doug Evans <dje@sebabeach.org>
657
9468ae89
DE		 658 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
659 (print_address): Delete CGEN_PRINT_ADDRESS.
660 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
661 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
662 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
663 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
664
37ec9240
DE		 665 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
666 * frv-desc.c, * frv-desc.h, * frv-opc.c,
667 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
668 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
669 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
670 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
671 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
672 * mep-desc.c, * mep-desc.h, * mep-opc.c,
673 * mt-desc.c, * mt-desc.h, * mt-opc.c,
674 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
675 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
676 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
677
c75ef631
L		 6782010-02-11 H.J. Lu <hongjiu.lu@intel.com>
679
680 * i386-dis.c: Update copyright.
681 * i386-gen.c: Likewise.
682 * i386-opc.h: Likewise.
683 * i386-opc.tbl: Likewise.
684
a683cc34
SP		 6852010-02-10 Quentin Neill <quentin.neill@amd.com>
686 Sebastian Pop <sebastian.pop@amd.com>
687
688 * i386-dis.c (OP_EX_VexImmW): Reintroduced
689 function to handle 5th imm8 operand.
690 (PREFIX_VEX_3A48): Added.
691 (PREFIX_VEX_3A49): Added.
692 (VEX_W_3A48_P_2): Added.
693 (VEX_W_3A49_P_2): Added.
694 (prefix table): Added entries for PREFIX_VEX_3A48
695 and PREFIX_VEX_3A49.
696 (vex table): Added entries for VEX_W_3A48_P_2 and
697 and VEX_W_3A49_P_2.
698 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
699 for Vec_Imm4 operands.
700 * i386-opc.h (enum): Added Vec_Imm4.
701 (i386_operand_type): Added vec_imm4.
702 * i386-opc.tbl: Add entries for vpermilp[ds].
703 * i386-init.h: Regenerated.
704 * i386-tbl.h: Regenerated.
705
cdc51b07
RS		 7062010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
707
708 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
709 and "pwr7". Move "a2" into alphabetical order.
710
ce3d2015
AM		 7112010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
712
713 * ppc-dis.c (ppc_opts): Add titan entry.
714 * ppc-opc.c (TITAN, MULHW): Define.
715 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
716
68339fdf
SP		 7172010-02-03 Quentin Neill <quentin.neill@amd.com>
718
719 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
720 to CPU_BDVER1_FLAGS
721 * i386-init.h: Regenerated.
722
f3d55a94
AG		 7232010-02-03 Anthony Green <green@moxielogic.com>
724
725 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
726 0x0f, and make 0x00 an illegal instruction.
727
b0e28b39
DJ		 7282010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
729
730 * opcodes/arm-dis.c (struct arm_private_data): New.
731 (print_insn_coprocessor, print_insn_arm): Update to use struct
732 arm_private_data.
733 (is_mapping_symbol, get_map_sym_type): New functions.
734 (get_sym_code_type): Check the symbol's section. Do not check
735 mapping symbols.
736 (print_insn): Default to disassembling ARM mode code. Check
737 for mapping symbols separately from other symbols. Use
738 struct arm_private_data.
739
1c480963
L		 7402010-01-28 H.J. Lu <hongjiu.lu@intel.com>
741
742 * i386-dis.c (EXVexWdqScalar): New.
743 (vex_scalar_w_dq_mode): Likewise.
744 (prefix_table): Update entries for PREFIX_VEX_3899,
745 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
746 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
747 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
748 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
749 (intel_operand_size): Handle vex_scalar_w_dq_mode.
750 (OP_EX): Likewise.
751
539f890d
L		 7522010-01-27 H.J. Lu <hongjiu.lu@intel.com>
753
754 * i386-dis.c (XMScalar): New.
755 (EXdScalar): Likewise.
756 (EXqScalar): Likewise.
757 (EXqScalarS): Likewise.
758 (VexScalar): Likewise.
759 (EXdVexScalarS): Likewise.
760 (EXqVexScalarS): Likewise.
761 (XMVexScalar): Likewise.
762 (scalar_mode): Likewise.
763 (d_scalar_mode): Likewise.
764 (d_scalar_swap_mode): Likewise.
765 (q_scalar_mode): Likewise.
766 (q_scalar_swap_mode): Likewise.
767 (vex_scalar_mode): Likewise.
768 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
769 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
770 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
771 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
772 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
773 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
774 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
775 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
776 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
777 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
778 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
779 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
780 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
781 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
782 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
783 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
784 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
785 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
786 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
787 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
788 q_scalar_mode, q_scalar_swap_mode.
789 (OP_XMM): Handle scalar_mode.
790 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
791 and q_scalar_swap_mode.
792 (OP_VEX): Handle vex_scalar_mode.
793
208b4d78
L		 7942010-01-24 H.J. Lu <hongjiu.lu@intel.com>
795
796 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
797
448b213a
L		 7982010-01-24 H.J. Lu <hongjiu.lu@intel.com>
799
800 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
801
47cf8fa0
L		 8022010-01-24 H.J. Lu <hongjiu.lu@intel.com>
803
804 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
805
592d1631
L		 8062010-01-24 H.J. Lu <hongjiu.lu@intel.com>
807
808 * i386-dis.c (Bad_Opcode): New.
809 (bad_opcode): Likewise.
810 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
811 (dis386_twobyte): Likewise.
812 (reg_table): Likewise.
813 (prefix_table): Likewise.
814 (x86_64_table): Likewise.
815 (vex_len_table): Likewise.
816 (vex_w_table): Likewise.
817 (mod_table): Likewise.
818 (rm_table): Likewise.
819 (float_reg): Likewise.
820 (reg_table): Remove trailing "(bad)" entries.
821 (prefix_table): Likewise.
822 (x86_64_table): Likewise.
823 (vex_len_table): Likewise.
824 (vex_w_table): Likewise.
825 (mod_table): Likewise.
826 (rm_table): Likewise.
827 (get_valid_dis386): Handle bytemode 0.
828
712366da
L		 8292010-01-23 H.J. Lu <hongjiu.lu@intel.com>
830
831 * i386-opc.h (VEXScalar): New.
832
833 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
834 instructions.
835 * i386-tbl.h: Regenerated.
836
706e8205 8372010-01-21 H.J. Lu <hongjiu.lu@intel.com>
73bb6729
L		 838
839 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
840
841 * i386-opc.tbl: Add xsave64 and xrstor64.
842 * i386-tbl.h: Regenerated.
843
99ea83aa
NC		 8442010-01-20 Nick Clifton <nickc@redhat.com>
845
846 PR 11170
847 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
848 based post-indexed addressing.
849
a6461c02
SP		 8502010-01-15 Sebastian Pop <sebastian.pop@amd.com>
851
852 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
853 * i386-tbl.h: Regenerated.
854
a2a7d12c
L		 8552010-01-14 H.J. Lu <hongjiu.lu@intel.com>
856
857 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
858 comments.
859
b9733481
L		 8602010-01-14 H.J. Lu <hongjiu.lu@intel.com>
861
862 * i386-dis.c (names_mm): New.
863 (intel_names_mm): Likewise.
864 (att_names_mm): Likewise.
865 (names_xmm): Likewise.
866 (intel_names_xmm): Likewise.
867 (att_names_xmm): Likewise.
868 (names_ymm): Likewise.
869 (intel_names_ymm): Likewise.
870 (att_names_ymm): Likewise.
871 (print_insn): Set names_mm, names_xmm and names_ymm.
872 (OP_MMX): Use names_mm, names_xmm and names_ymm.
873 (OP_XMM): Likewise.
874 (OP_EM): Likewise.
875 (OP_EMC): Likewise.
876 (OP_MXC): Likewise.
877 (OP_EX): Likewise.
878 (XMM_Fixup): Likewise.
879 (OP_VEX): Likewise.
880 (OP_EX_VexReg): Likewise.
881 (OP_Vex_2src): Likewise.
882 (OP_Vex_2src_1): Likewise.
883 (OP_Vex_2src_2): Likewise.
884 (OP_REG_VexI4): Likewise.
885
5e6718e4
L		 8862010-01-13 H.J. Lu <hongjiu.lu@intel.com>
887
888 * i386-dis.c (print_insn): Update comments.
889
d869730d
L		 8902010-01-12 H.J. Lu <hongjiu.lu@intel.com>
891
892 * i386-dis.c (rex_original): Removed.
893 (ckprefix): Remove rex_original.
894 (print_insn): Update comments.
895
3725885a
RW		 8962010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
897
898 * Makefile.in: Regenerate.
899 * configure: Regenerate.
900
b7cd1872
DE		 9012010-01-07 Doug Evans <dje@sebabeach.org>
902
903 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
904 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
905 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
906 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
907 * xstormy16-ibld.c: Regenerate.
908
69dd9865
SP		 9092010-01-06 Quentin Neill <quentin.neill@amd.com>
910
911 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
912 * i386-init.h: Regenerated.
913
e3e535bc
NC		 9142010-01-06 Daniel Gutson <dgutson@codesourcery.com>
915
916 * arm-dis.c (print_insn): Fixed search for next symbol and data
917 dumping condition, and the initial mapping symbol state.
918
fe8afbc4
DE		 9192010-01-05 Doug Evans <dje@sebabeach.org>
920
921 * cgen-ibld.in: #include "cgen/basic-modes.h".
922 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
923 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
924 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
925 * xstormy16-ibld.c: Regenerate.
926
2edcd244
NC		 9272010-01-04 Nick Clifton <nickc@redhat.com>
928
929 PR 11123
930 * arm-dis.c (print_insn_coprocessor): Initialise value.
931
0dc93057
AM		 9322010-01-04 Edmar Wienskoski <edmar@freescale.com>
933
934 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
935
05994f45
DE		 9362010-01-02 Doug Evans <dje@sebabeach.org>
937
938 * cgen-asm.in: Update copyright year.
939 * cgen-dis.in: Update copyright year.
940 * cgen-ibld.in: Update copyright year.
941 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
942 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
943 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
944 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
945 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
946 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
947 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
948 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
949 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
950 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
951 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
952 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
953 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
954 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
955 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
956 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
957 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
958 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
959 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
960 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
961 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2426c15f 962
43ecc30f 963For older changes see ChangeLog-2009
252b5132
RH		 964\f
965Local Variables:
2f6d2f85
NC		 966mode: change-log
967left-margin: 8
968fill-column: 74
252b5132
RH		 969version-control: never
970End:
GDB Binutils - Deliverables
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