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2005-05-07 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
920a34a7
L		 12005-05-07 H.J. Lu <hongjiu.lu@intel.com>
2
3 * d10v-dis.c (dis_2_short): Support 64bit host.
4
5de773c1
NC		 52005-05-07 Nick Clifton <nickc@redhat.com>
6
7 * po/nl.po: Updated translation.
8
f4321104
NC		 92005-05-07 Nick Clifton <nickc@redhat.com>
10
11 * Update the address and phone number of the FSF organization in
12 the GPL notices in the following files:
13 a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c,
14 arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h,
15 avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in,
16 cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c,
17 crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c,
18 d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c,
19 fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c,
20 fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h,
21 frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c,
22 h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c,
23 i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c,
24 ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c,
25 ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c,
26 ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h,
27 ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c,
28 iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c,
29 iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c,
30 m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h,
31 m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c,
32 m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c,
33 maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c,
34 mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c,
35 openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c,
36 openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h,
37 or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c,
38 pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c,
39 s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c,
40 sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c,
41 tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c,
42 v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h,
43 xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h,
44 xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c,
45 xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c
46
10b076a2
JW		 472005-05-05 James E Wilson <wilson@specifixinc.com>
48
49 * ia64-opc.c: Include sysdep.h before libiberty.h.
50
022716b6
NC		 512005-05-05 Nick Clifton <nickc@redhat.com>
52
53 * configure.in (ALL_LINGUAS): Add vi.
54 * configure: Regenerate.
55 * po/vi.po: New.
56
db5152b4
JG		 572005-04-26 Jerome Guitton <guitton@gnat.com>
58
59 * configure.in: Fix the check for basename declaration.
60 * configure: Regenerate.
61
eed0d89a
AM		 622005-04-19 Alan Modra <amodra@bigpond.net.au>
63
64 * ppc-opc.c (RTO): Define.
65 (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
66 entries to suit PPC440.
67
791fe849
MK		 682005-04-18 Mark Kettenis <kettenis@gnu.org>
69
70 * i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
71 Add xcrypt-ctr.
72
ffe58f7c
NC		 732005-04-14 Nick Clifton <nickc@redhat.com>
74
75 * po/fi.po: New translation: Finnish.
76 * configure.in (ALL_LINGUAS): Add fi.
77 * configure: Regenerate.
78
9e9b66a9
AM		 792005-04-14 Alan Modra <amodra@bigpond.net.au>
80
81 * Makefile.am (NO_WERROR): Define.
82 * configure.in: Invoke AM_BINUTILS_WARNINGS.
83 * Makefile.in: Regenerate.
84 * aclocal.m4: Regenerate.
85 * configure: Regenerate.
86
9494d739
NC		 872005-04-04 Nick Clifton <nickc@redhat.com>
88
89 * fr30-asm.c: Regenerate.
90 * frv-asm.c: Regenerate.
91 * iq2000-asm.c: Regenerate.
92 * m32r-asm.c: Regenerate.
93 * openrisc-asm.c: Regenerate.
94
6128c599
JB		 952005-04-01 Jan Beulich <jbeulich@novell.com>
96
97 * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
98 visible operands in Intel mode. The first operand of monitor is
99 %rax in 64-bit mode.
100
373ff435
JB		 1012005-04-01 Jan Beulich <jbeulich@novell.com>
102
103 * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
104 easier future additions.
105
4bd60896
JG		 1062005-03-31 Jerome Guitton <guitton@gnat.com>
107
108 * configure.in: Check for basename.
109 * configure: Regenerate.
110 * config.in: Ditto.
111
4cc91dba
L		 1122005-03-29 H.J. Lu <hongjiu.lu@intel.com>
113
114 * i386-dis.c (SEG_Fixup): New.
115 (Sv): New.
116 (dis386): Use "Sv" for 0x8c and 0x8e.
117
ec72cfe5
NC		 1182005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
119 Nick Clifton <nickc@redhat.com>
120
121 * vax-dis.c: (entry_addr): New varible: An array of user supplied
122 function entry mask addresses.
123 (entry_addr_occupied_slots): New variable: The number of occupied
124 elements in entry_addr.
125 (entry_addr_total_slots): New variable: The total number of
126 elements in entry_addr.
127 (parse_disassembler_options): New function. Fills in the entry_addr
128 array.
129 (free_entry_array): New function. Release the memory used by the
130 entry addr array. Suppressed because there is no way to call it.
131 (is_function_entry): Check if a given address is a function's
132 start address by looking at supplied entry mask addresses and
133 symbol information, if available.
134 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
135
85064c79
L		 1362005-03-23 H.J. Lu <hongjiu.lu@intel.com>
137
138 * cris-dis.c (print_with_operands): Use ~31L for long instead
139 of ~31.
140
de7141c7
L		 1412005-03-20 H.J. Lu <hongjiu.lu@intel.com>
142
143 * mmix-opc.c (O): Revert the last change.
144 (Z): Likewise.
145
e493ab45
L		 1462005-03-19 H.J. Lu <hongjiu.lu@intel.com>
147
148 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
149 (Z): Likewise.
150
d8d7c459
HPN		 1512005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
152
153 * mmix-opc.c (O, Z): Force expression as unsigned long.
154
ebdb0383
NC		 1552005-03-18 Nick Clifton <nickc@redhat.com>
156
157 * ip2k-asm.c: Regenerate.
158 * op/opcodes.pot: Regenerate.
159
1ad12f97
NC		 1602005-03-16 Nick Clifton <nickc@redhat.com>
161 Ben Elliston <bje@au.ibm.com>
162
569acd2c 163 * configure.in (werror): New switch: Add -Werror to the
1ad12f97 164 compiler command line. Enabled by default. Disable via
569acd2c 165 --disable-werror.
1ad12f97
NC		 166 * configure: Regenerate.
167
4eb30afc
AM		 1682005-03-16 Alan Modra <amodra@bigpond.net.au>
169
170 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
171 BOOKE.
172
ea8409f7
AM		 1732005-03-15 Alan Modra <amodra@bigpond.net.au>
174
729ae8d2
AM		 175 * po/es.po: Commit new Spanish translation.
176
ea8409f7
AM		 177 * po/fr.po: Commit new French translation.
178
4f495e61
NC		 1792005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
180
181 * vax-dis.c: Fix spelling error
182 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
183 of just "Entry mask: < r1 ... >"
184
0a003adc
ZW		 1852005-03-12 Zack Weinberg <zack@codesourcery.com>
186
187 * arm-dis.c (arm_opcodes): Document %E and %V.
188 Add entries for v6T2 ARM instructions:
189 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
190 (print_insn_arm): Add support for %E and %V.
885fc257 191 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
0a003adc 192
da99ee72
AM		 1932005-03-10 Jeff Baker <jbaker@qnx.com>
194 Alan Modra <amodra@bigpond.net.au>
195
196 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
197 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
198 (SPRG_MASK): Delete.
199 (XSPRG_MASK): Mask off extra bits now part of sprg field.
0a003adc 200 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
da99ee72
AM		 201 mfsprg4..7 after msprg and consolidate.
202
220abb21
AM		 2032005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
204
205 * vax-dis.c (entry_mask_bit): New array.
206 (print_insn_vax): Decode function entry mask.
207
0e06657a
AH		 2082005-03-07 Aldy Hernandez <aldyh@redhat.com>
209
210 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
211
06647dfd
AM		 2122005-03-05 Alan Modra <amodra@bigpond.net.au>
213
214 * po/opcodes.pot: Regenerate.
215
82b829a7
RR		 2162005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
217
220abb21 218 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 219 (dsmOneArcInst): Use the enum values for the decoding class.
220 Remove redundant case in the switch for decodingClass value 11.
82b829a7 221
c4a530c5
JB		 2222005-03-02 Jan Beulich <jbeulich@novell.com>
223
224 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
225 accesses.
226 (OP_C): Consider lock prefix in non-64-bit modes.
227
47d8304e
AM		 2282005-02-24 Alan Modra <amodra@bigpond.net.au>
229
230 * cris-dis.c (format_hex): Remove ineffective warning fix.
231 * crx-dis.c (make_instruction): Warning fix.
232 * frv-asm.c: Regenerate.
233
ec36c4a4
NC		 2342005-02-23 Nick Clifton <nickc@redhat.com>
235
33b71eeb
NC		 236 * cgen-dis.in: Use bfd_byte for buffers that are passed to
237 read_memory.
06647dfd 238
33b71eeb 239 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 240
ec36c4a4
NC		 241 * crx-dis.c (make_instruction): Move argument structure into inner
242 scope and ensure that all of its fields are initialised before
243 they are used.
244
33b71eeb
NC		 245 * fr30-asm.c: Regenerate.
246 * fr30-dis.c: Regenerate.
247 * frv-asm.c: Regenerate.
248 * frv-dis.c: Regenerate.
249 * ip2k-asm.c: Regenerate.
250 * ip2k-dis.c: Regenerate.
251 * iq2000-asm.c: Regenerate.
252 * iq2000-dis.c: Regenerate.
253 * m32r-asm.c: Regenerate.
254 * m32r-dis.c: Regenerate.
255 * openrisc-asm.c: Regenerate.
256 * openrisc-dis.c: Regenerate.
257 * xstormy16-asm.c: Regenerate.
258 * xstormy16-dis.c: Regenerate.
259
53c9ebc5
AM		 2602005-02-22 Alan Modra <amodra@bigpond.net.au>
261
262 * arc-ext.c: Warning fixes.
263 * arc-ext.h: Likewise.
264 * cgen-opc.c: Likewise.
265 * ia64-gen.c: Likewise.
266 * maxq-dis.c: Likewise.
267 * ns32k-dis.c: Likewise.
268 * w65-dis.c: Likewise.
269 * ia64-asmtab.c: Regenerate.
270
610ad19b
AM		 2712005-02-22 Alan Modra <amodra@bigpond.net.au>
272
273 * fr30-desc.c: Regenerate.
274 * fr30-desc.h: Regenerate.
275 * fr30-opc.c: Regenerate.
276 * fr30-opc.h: Regenerate.
277 * frv-desc.c: Regenerate.
278 * frv-desc.h: Regenerate.
279 * frv-opc.c: Regenerate.
280 * frv-opc.h: Regenerate.
281 * ip2k-desc.c: Regenerate.
282 * ip2k-desc.h: Regenerate.
283 * ip2k-opc.c: Regenerate.
284 * ip2k-opc.h: Regenerate.
285 * iq2000-desc.c: Regenerate.
286 * iq2000-desc.h: Regenerate.
287 * iq2000-opc.c: Regenerate.
288 * iq2000-opc.h: Regenerate.
289 * m32r-desc.c: Regenerate.
290 * m32r-desc.h: Regenerate.
291 * m32r-opc.c: Regenerate.
292 * m32r-opc.h: Regenerate.
293 * m32r-opinst.c: Regenerate.
294 * openrisc-desc.c: Regenerate.
295 * openrisc-desc.h: Regenerate.
296 * openrisc-opc.c: Regenerate.
297 * openrisc-opc.h: Regenerate.
298 * xstormy16-desc.c: Regenerate.
299 * xstormy16-desc.h: Regenerate.
300 * xstormy16-opc.c: Regenerate.
301 * xstormy16-opc.h: Regenerate.
302
db9db6f2
AM		 3032005-02-21 Alan Modra <amodra@bigpond.net.au>
304
305 * Makefile.am: Run "make dep-am"
306 * Makefile.in: Regenerate.
307
bf143b25
NC		 3082005-02-15 Nick Clifton <nickc@redhat.com>
309
310 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
311 compile time warnings.
312 (print_keyword): Likewise.
313 (default_print_insn): Likewise.
314
315 * fr30-desc.c: Regenerated.
316 * fr30-desc.h: Regenerated.
317 * fr30-dis.c: Regenerated.
318 * fr30-opc.c: Regenerated.
319 * fr30-opc.h: Regenerated.
320 * frv-desc.c: Regenerated.
321 * frv-dis.c: Regenerated.
322 * frv-opc.c: Regenerated.
323 * ip2k-asm.c: Regenerated.
324 * ip2k-desc.c: Regenerated.
325 * ip2k-desc.h: Regenerated.
326 * ip2k-dis.c: Regenerated.
327 * ip2k-opc.c: Regenerated.
328 * ip2k-opc.h: Regenerated.
329 * iq2000-desc.c: Regenerated.
330 * iq2000-dis.c: Regenerated.
331 * iq2000-opc.c: Regenerated.
332 * m32r-asm.c: Regenerated.
333 * m32r-desc.c: Regenerated.
334 * m32r-desc.h: Regenerated.
335 * m32r-dis.c: Regenerated.
336 * m32r-opc.c: Regenerated.
337 * m32r-opc.h: Regenerated.
338 * m32r-opinst.c: Regenerated.
339 * openrisc-desc.c: Regenerated.
340 * openrisc-desc.h: Regenerated.
341 * openrisc-dis.c: Regenerated.
342 * openrisc-opc.c: Regenerated.
343 * openrisc-opc.h: Regenerated.
344 * xstormy16-desc.c: Regenerated.
345 * xstormy16-desc.h: Regenerated.
346 * xstormy16-dis.c: Regenerated.
347 * xstormy16-opc.c: Regenerated.
348 * xstormy16-opc.h: Regenerated.
349
d6098898
L		 3502005-02-14 H.J. Lu <hongjiu.lu@intel.com>
351
352 * dis-buf.c (perror_memory): Use sprintf_vma to print out
353 address.
354
5a84f3e0
NC		 3552005-02-11 Nick Clifton <nickc@redhat.com>
356
bc18c937
NC		 357 * iq2000-asm.c: Regenerate.
358
5a84f3e0
NC		 359 * frv-dis.c: Regenerate.
360
0a40490e
JB		 3612005-02-07 Jim Blandy <jimb@redhat.com>
362
363 * Makefile.am (CGEN): Load guile.scm before calling the main
364 application script.
365 * Makefile.in: Regenerated.
366 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
367 Simply pass the cgen-opc.scm path to ${cgen} as its first
368 argument; ${cgen} itself now contains the '-s', or whatever is
369 appropriate for the Scheme being used.
370
c46f8c51
AC		 3712005-01-31 Andrew Cagney <cagney@gnu.org>
372
373 * configure: Regenerate to track ../gettext.m4.
374
60b9a617
JB		 3752005-01-31 Jan Beulich <jbeulich@novell.com>
376
377 * ia64-gen.c (NELEMS): Define.
378 (shrink): Generate alias with missing second predicate register when
379 opcode has two outputs and these are both predicates.
380 * ia64-opc-i.c (FULL17): Define.
381 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
382 here to generate output template.
383 (TBITCM, TNATCM): Undefine after use.
384 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
385 first input. Add ld16 aliases without ar.csd as second output. Add
386 st16 aliases without ar.csd as second input. Add cmpxchg aliases
387 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
388 ar.ccv as third/fourth inputs. Consolidate through...
389 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
390 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
391 * ia64-asmtab.c: Regenerate.
392
a53bf506
AC		 3932005-01-27 Andrew Cagney <cagney@gnu.org>
394
395 * configure: Regenerate to track ../gettext.m4 change.
396
90219bd0
AO		 3972005-01-25 Alexandre Oliva <aoliva@redhat.com>
398
399 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
400 * frv-asm.c: Rebuilt.
401 * frv-desc.c: Rebuilt.
402 * frv-desc.h: Rebuilt.
403 * frv-dis.c: Rebuilt.
404 * frv-ibld.c: Rebuilt.
405 * frv-opc.c: Rebuilt.
406 * frv-opc.h: Rebuilt.
407
45181ed1
AC		 4082005-01-24 Andrew Cagney <cagney@gnu.org>
409
410 * configure: Regenerate, ../gettext.m4 was updated.
411
9e836e3d
FF		 4122005-01-21 Fred Fish <fnf@specifixinc.com>
413
414 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
415 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
416 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
417 * mips-dis.c: Ditto.
418
5e8cb021
AM		 4192005-01-20 Alan Modra <amodra@bigpond.net.au>
420
421 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
422
986e18a5
FF		 4232005-01-19 Fred Fish <fnf@specifixinc.com>
424
425 * mips-dis.c (no_aliases): New disassembly option flag.
426 (set_default_mips_dis_options): Init no_aliases to zero.
427 (parse_mips_dis_option): Handle no-aliases option.
428 (print_insn_mips): Ignore table entries that are aliases
429 if no_aliases is set.
430 (print_insn_mips16): Ditto.
431 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
432 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
433 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
434 * mips16-opc.c (mips16_opcodes): Ditto.
435
e38bc3b5
NC		 4362005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
437
438 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
439 (inheritance diagram): Add missing edge.
440 (arch_sh1_up): Rename arch_sh_up to match external name to make life
441 easier for the testsuite.
442 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
443 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 444 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 445 arch_sh2a_or_sh4_up child.
446 (sh_table): Do renaming as above.
447 Correct comment for ldc.l for gas testsuite to read.
448 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
449 Correct comments for movy.w and movy.l for gas testsuite to read.
450 Correct comments for fmov.d and fmov.s for gas testsuite to read.
451
9df48ba9
L		 4522005-01-12 H.J. Lu <hongjiu.lu@intel.com>
453
454 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
455
2033b4b9
L		 4562005-01-12 H.J. Lu <hongjiu.lu@intel.com>
457
458 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
459
0bcb06d2
AS		 4602005-01-10 Andreas Schwab <schwab@suse.de>
461
462 * disassemble.c (disassemble_init_for_target) <case
463 bfd_arch_ia64>: Set skip_zeroes to 16.
464 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
465
47add74d
TL		 4662004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
467
468 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
469
246f4c05
SS		 4702004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
471
472 * avr-dis.c: Prettyprint. Added printing of symbol names in all
473 memory references. Convert avr_operand() to C90 formatting.
474
0e1200e5
TL		 4752004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
476
477 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
478
89a649f7
TL		 4792004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
480
481 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
482 (no_op_insn): Initialize array with instructions that have no
483 operands.
484 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
485
6255809c
RE		 4862004-11-29 Richard Earnshaw <rearnsha@arm.com>
487
488 * arm-dis.c: Correct top-level comment.
489
2fbad815
RE		 4902004-11-27 Richard Earnshaw <rearnsha@arm.com>
491
492 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
493 architecuture defining the insn.
494 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 495 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
496 field.
2fbad815
RE		 497 Also include opcode/arm.h.
498 * Makefile.am (arm-dis.lo): Update dependency list.
499 * Makefile.in: Regenerate.
500
d81acc42
NC		 5012004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
502
503 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
504 reflect the change to the short immediate syntax.
505
ca4f2377
AM		 5062004-11-19 Alan Modra <amodra@bigpond.net.au>
507
5da8bf1b
AM		 508 * or32-opc.c (debug): Warning fix.
509 * po/POTFILES.in: Regenerate.
510
ca4f2377
AM		 511 * maxq-dis.c: Formatting.
512 (print_insn): Warning fix.
513
b7693d02
DJ		 5142004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
515
516 * arm-dis.c (WORD_ADDRESS): Define.
517 (print_insn): Use it. Correct big-endian end-of-section handling.
518
300dac7e
NC		 5192004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
520 Vineet Sharma <vineets@noida.hcltech.com>
521
522 * maxq-dis.c: New file.
523 * disassemble.c (ARCH_maxq): Define.
610ad19b 524 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 525 instructions..
526 * configure.in: Add case for bfd_maxq_arch.
527 * configure: Regenerate.
528 * Makefile.am: Add support for maxq-dis.c
529 * Makefile.in: Regenerate.
530 * aclocal.m4: Regenerate.
531
42048ee7
TL		 5322004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
533
534 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
535 mode.
536 * crx-dis.c: Likewise.
537
bd21e58e
HPN		 5382004-11-04 Hans-Peter Nilsson <hp@axis.com>
539
540 Generally, handle CRISv32.
541 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
542 (struct cris_disasm_data): New type.
543 (format_reg, format_hex, cris_constraint, print_flags)
544 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
545 callers changed.
546 (format_sup_reg, print_insn_crisv32_with_register_prefix)
547 (print_insn_crisv32_without_register_prefix)
548 (print_insn_crisv10_v32_with_register_prefix)
549 (print_insn_crisv10_v32_without_register_prefix)
550 (cris_parse_disassembler_options): New functions.
551 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
552 parameter. All callers changed.
553 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
554 failure.
555 (cris_constraint) <case 'Y', 'U'>: New cases.
556 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
557 for constraint 'n'.
558 (print_with_operands) <case 'Y'>: New case.
559 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
560 <case 'N', 'Y', 'Q'>: New cases.
561 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
562 (print_insn_cris_with_register_prefix)
563 (print_insn_cris_without_register_prefix): Call
564 cris_parse_disassembler_options.
565 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
566 for CRISv32 and the size of immediate operands. New v32-only
567 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
568 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
569 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
570 Change brp to be v3..v10.
571 (cris_support_regs): New vector.
572 (cris_opcodes): Update head comment. New format characters '[',
573 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
574 Add new opcodes for v32 and adjust existing opcodes to accommodate
575 differences to earlier variants.
576 (cris_cond15s): New vector.
577
9306ca4a
JB		 5782004-11-04 Jan Beulich <jbeulich@novell.com>
579
580 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
581 (indirEb): Remove.
582 (Mp): Use f_mode rather than none at all.
583 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
584 replaces what previously was x_mode; x_mode now means 128-bit SSE
585 operands.
586 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
587 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
588 pinsrw's second operand is Edqw.
589 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
590 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
591 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
592 mode when an operand size override is present or always suffixing.
593 More instructions will need to be added to this group.
594 (putop): Handle new macro chars 'C' (short/long suffix selector),
595 'I' (Intel mode override for following macro char), and 'J' (for
596 adding the 'l' prefix to far branches in AT&T mode). When an
597 alternative was specified in the template, honor macro character when
598 specified for Intel mode.
599 (OP_E): Handle new *_mode values. Correct pointer specifications for
600 memory operands. Consolidate output of index register.
601 (OP_G): Handle new *_mode values.
602 (OP_I): Handle const_1_mode.
603 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
604 respective opcode prefix bits have been consumed.
605 (OP_EM, OP_EX): Provide some default handling for generating pointer
606 specifications.
607
f39c96a9
TL		 6082004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
609
610 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
611 COP_INST macro.
612
812337be
TL		 6132004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
614
615 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
616 (getregliststring): Support HI/LO and user registers.
610ad19b 617 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 618 rearrangement done in CRX opcode header file.
619 (crx_regtab): Likewise.
620 (crx_optab): Likewise.
610ad19b 621 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 622 formats.
623 support new Co-Processor instruction 'cpi'.
624
4030fa5a
NC		 6252004-10-27 Nick Clifton <nickc@redhat.com>
626
627 * opcodes/iq2000-asm.c: Regenerate.
628 * opcodes/iq2000-desc.c: Regenerate.
629 * opcodes/iq2000-desc.h: Regenerate.
630 * opcodes/iq2000-dis.c: Regenerate.
631 * opcodes/iq2000-ibld.c: Regenerate.
632 * opcodes/iq2000-opc.c: Regenerate.
633 * opcodes/iq2000-opc.h: Regenerate.
634
fc3d45e8
TL		 6352004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
636
637 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
638 us4, us5 (respectively).
639 Remove unsupported 'popa' instruction.
640 Reverse operands order in store co-processor instructions.
641
3c55da70
AM		 6422004-10-15 Alan Modra <amodra@bigpond.net.au>
643
644 * Makefile.am: Run "make dep-am"
645 * Makefile.in: Regenerate.
646
7fa3d080
BW		 6472004-10-12 Bob Wilson <bob.wilson@acm.org>
648
649 * xtensa-dis.c: Use ISO C90 formatting.
650
e612bb4d
AM		 6512004-10-09 Alan Modra <amodra@bigpond.net.au>
652
653 * ppc-opc.c: Revert 2004-09-09 change.
654
43cd72b9
BW		 6552004-10-07 Bob Wilson <bob.wilson@acm.org>
656
657 * xtensa-dis.c (state_names): Delete.
658 (fetch_data): Use xtensa_isa_maxlength.
659 (print_xtensa_operand): Replace operand parameter with opcode/operand
660 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
661 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
662 instruction bundles. Use xmalloc instead of malloc.
663
bbac1f2a
NC		 6642004-10-07 David Gibson <david@gibson.dropbear.id.au>
665
666 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
667 initializers.
668
48c9f030
NC		 6692004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
670
671 * crx-opc.c (crx_instruction): Support Co-processor insns.
672 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
673 (getregliststring): Change function to use the above enum.
674 (print_arg): Handle CO-Processor insns.
675 (crx_cinvs): Add 'b' option to invalidate the branch-target
676 cache.
677
12c64a4e
AH		 6782004-10-06 Aldy Hernandez <aldyh@redhat.com>
679
680 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
681 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
682 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
683 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
684 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
685
14127cc4
NC		 6862004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
687
688 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
689 rather than add it.
690
0dd132b6
NC		 6912004-09-30 Paul Brook <paul@codesourcery.com>
692
693 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
694 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
695
3f85e526
L		 6962004-09-17 H.J. Lu <hongjiu.lu@intel.com>
697
698 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
699 (CONFIG_STATUS_DEPENDENCIES): New.
700 (Makefile): Removed.
701 (config.status): Likewise.
702 * Makefile.in: Regenerated.
703
8ae85421
AM		 7042004-09-17 Alan Modra <amodra@bigpond.net.au>
705
706 * Makefile.am: Run "make dep-am".
707 * Makefile.in: Regenerate.
708 * aclocal.m4: Regenerate.
709 * configure: Regenerate.
710 * po/POTFILES.in: Regenerate.
711 * po/opcodes.pot: Regenerate.
712
24443139
AS		 7132004-09-11 Andreas Schwab <schwab@suse.de>
714
715 * configure: Rebuild.
716
2a309db0
AM		 7172004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
718
719 * ppc-opc.c (L): Make this field not optional.
720
42851540
NC		 7212004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
722
723 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
724 Fix parameter to 'm[t|f]csr' insns.
725
979273e3
NN		 7262004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
727
728 * configure.in: Autoupdate to autoconf 2.59.
729 * aclocal.m4: Rebuild with aclocal 1.4p6.
730 * configure: Rebuild with autoconf 2.59.
731 * Makefile.in: Rebuild with automake 1.4p6 (picking up
732 bfd changes for autoconf 2.59 on the way).
733 * config.in: Rebuild with autoheader 2.59.
734
ac28a1cb
RS		 7352004-08-27 Richard Sandiford <rsandifo@redhat.com>
736
737 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
738
30d1c836
ML		 7392004-07-30 Michal Ludvig <mludvig@suse.cz>
740
741 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
742 (GRPPADLCK2): New define.
743 (twobyte_has_modrm): True for 0xA6.
744 (grps): GRPPADLCK2 for opcode 0xA6.
745
0b0ac059
AO		 7462004-07-29 Alexandre Oliva <aoliva@redhat.com>
747
748 Introduce SH2a support.
749 * sh-opc.h (arch_sh2a_base): Renumber.
750 (arch_sh2a_nofpu_base): Remove.
751 (arch_sh_base_mask): Adjust.
752 (arch_opann_mask): New.
753 (arch_sh2a, arch_sh2a_nofpu): Adjust.
754 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
755 (sh_table): Adjust whitespace.
756 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
757 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
758 instruction list throughout.
759 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
760 of arch_sh2a in instruction list throughout.
761 (arch_sh2e_up): Accomodate above changes.
762 (arch_sh2_up): Ditto.
763 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
764 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
765 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
766 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
767 * sh-opc.h (arch_sh2a_nofpu): New.
768 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
769 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
770 instruction.
771 2004-01-20 DJ Delorie <dj@redhat.com>
772 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
773 2003-12-29 DJ Delorie <dj@redhat.com>
774 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
775 sh_opcode_info, sh_table): Add sh2a support.
776 (arch_op32): New, to tag 32-bit opcodes.
777 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
778 2003-12-02 Michael Snyder <msnyder@redhat.com>
779 * sh-opc.h (arch_sh2a): Add.
780 * sh-dis.c (arch_sh2a): Handle.
781 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
782
670ec21d
NC		 7832004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
784
785 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
786
ed049af3
NC		 7872004-07-22 Nick Clifton <nickc@redhat.com>
788
789 PR/280
790 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
791 insns - this is done by objdump itself.
792 * h8500-dis.c (print_insn_h8500): Likewise.
793
20f0a1fc
NC		 7942004-07-21 Jan Beulich <jbeulich@novell.com>
795
796 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
797 regardless of address size prefix in effect.
798 (ptr_reg): Size or address registers does not depend on rex64, but
799 on the presence of an address size override.
800 (OP_MMX): Use rex.x only for xmm registers.
801 (OP_EM): Use rex.z only for xmm registers.
802
6f14957b
MR		 8032004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
804
805 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
806 move/branch operations to the bottom so that VR5400 multimedia
807 instructions take precedence in disassembly.
808
1586d91e
MR		 8092004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
810
811 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
812 ISA-specific "break" encoding.
813
982de27a
NC		 8142004-07-13 Elvis Chiang <elvisfb@gmail.com>
815
816 * arm-opc.h: Fix typo in comment.
817
4300ab10
AS		 8182004-07-11 Andreas Schwab <schwab@suse.de>
819
820 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
821
8577e690
AS		 8222004-07-09 Andreas Schwab <schwab@suse.de>
823
824 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
825
1fe1f39c
NC		 8262004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
827
828 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
829 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
830 (crx-dis.lo): New target.
831 (crx-opc.lo): Likewise.
832 * Makefile.in: Regenerate.
833 * configure.in: Handle bfd_crx_arch.
834 * configure: Regenerate.
835 * crx-dis.c: New file.
836 * crx-opc.c: New file.
837 * disassemble.c (ARCH_crx): Define.
838 (disassembler): Handle ARCH_crx.
839
7a33b495
JW		 8402004-06-29 James E Wilson <wilson@specifixinc.com>
841
842 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
843 * ia64-asmtab.c: Regnerate.
844
98e69875
AM		 8452004-06-28 Alan Modra <amodra@bigpond.net.au>
846
847 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
848 (extract_fxm): Don't test dialect.
849 (XFXFXM_MASK): Include the power4 bit.
850 (XFXM): Add p4 param.
851 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
852
a53b85e2
AO		 8532004-06-27 Alexandre Oliva <aoliva@redhat.com>
854
855 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
856 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
857
d0618d1c
AM		 8582004-06-26 Alan Modra <amodra@bigpond.net.au>
859
860 * ppc-opc.c (BH, XLBH_MASK): Define.
861 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
862
1d9f512f
AM		 8632004-06-24 Alan Modra <amodra@bigpond.net.au>
864
865 * i386-dis.c (x_mode): Comment.
866 (two_source_ops): File scope.
867 (float_mem): Correct fisttpll and fistpll.
868 (float_mem_mode): New table.
869 (dofloat): Use it.
870 (OP_E): Correct intel mode PTR output.
871 (ptr_reg): Use open_char and close_char.
872 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
873 operands. Set two_source_ops.
874
52886d70
AM		 8752004-06-15 Alan Modra <amodra@bigpond.net.au>
876
877 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
878 instead of _raw_size.
879
bad9ceea
JJ		 8802004-06-08 Jakub Jelinek <jakub@redhat.com>
881
882 * ia64-gen.c (in_iclass): Handle more postinc st
883 and ld variants.
884 * ia64-asmtab.c: Rebuilt.
885
0451f5df
MS		 8862004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
887
888 * s390-opc.txt: Correct architecture mask for some opcodes.
889 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
890 in the esa mode as well.
891
f6f9408f
JR		 8922004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
893
894 * sh-dis.c (target_arch): Make unsigned.
895 (print_insn_sh): Replace (most of) switch with a call to
896 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
897 * sh-opc.h: Redefine architecture flags values.
898 Add sh3-nommu architecture.
899 Reorganise <arch>_up macros so they make more visual sense.
900 (SH_MERGE_ARCH_SET): Define new macro.
901 (SH_VALID_BASE_ARCH_SET): Likewise.
902 (SH_VALID_MMU_ARCH_SET): Likewise.
903 (SH_VALID_CO_ARCH_SET): Likewise.
904 (SH_VALID_ARCH_SET): Likewise.
905 (SH_MERGE_ARCH_SET_VALID): Likewise.
906 (SH_ARCH_SET_HAS_FPU): Likewise.
907 (SH_ARCH_SET_HAS_DSP): Likewise.
908 (SH_ARCH_UNKNOWN_ARCH): Likewise.
909 (sh_get_arch_from_bfd_mach): Add prototype.
910 (sh_get_arch_up_from_bfd_mach): Likewise.
911 (sh_get_bfd_mach_from_arch_set): Likewise.
912 (sh_merge_bfd_arc): Likewise.
913
be8c092b
NC		 9142004-05-24 Peter Barada <peter@the-baradas.com>
915
916 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 917 into new match_insn_m68k function. Loop over canidate
918 matches and select first that completely matches.
be8c092b
NC		 919 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
920 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 921 to verify addressing for MAC/EMAC.
be8c092b
NC		 922 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
923 reigster halves since 'fpu' and 'spl' look misleading.
924 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
925 * m68k-opc.c: Rearragne mac/emac cases to use longest for
926 first, tighten up match masks.
927 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
928 'size' from special case code in print_insn_m68k to
929 determine decode size of insns.
930
a30e9cc4
AM		 9312004-05-19 Alan Modra <amodra@bigpond.net.au>
932
933 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
934 well as when -mpower4.
935
9598fbe5
NC		 9362004-05-13 Nick Clifton <nickc@redhat.com>
937
938 * po/fr.po: Updated French translation.
939
6b6e92f4
NC		 9402004-05-05 Peter Barada <peter@the-baradas.com>
941
942 * m68k-dis.c(print_insn_m68k): Add new chips, use core
943 variants in arch_mask. Only set m68881/68851 for 68k chips.
944 * m68k-op.c: Switch from ColdFire chips to core variants.
945
a404d431
AM		 9462004-05-05 Alan Modra <amodra@bigpond.net.au>
947
a30e9cc4 948 PR 147.
a404d431
AM		 949 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
950
f3806e43
BE		 9512004-04-29 Ben Elliston <bje@au.ibm.com>
952
520ceea4
BE		 953 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
954 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 955
1f1799d5
KK		 9562004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
957
958 * sh-dis.c (print_insn_sh): Print the value in constant pool
959 as a symbol if it looks like a symbol.
960
fd99574b
NC		 9612004-04-22 Peter Barada <peter@the-baradas.com>
962
963 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
964 appropriate ColdFire architectures.
965 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
966 mask addressing.
967 Add EMAC instructions, fix MAC instructions. Remove
968 macmw/macml/msacmw/msacml instructions since mask addressing now
969 supported.
970
b4781d44
JJ		 9712004-04-20 Jakub Jelinek <jakub@redhat.com>
972
973 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
974 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
975 suffix. Use fmov*x macros, create all 3 fpsize variants in one
976 macro. Adjust all users.
977
91809fda 9782004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 979
91809fda
NC		 980 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
981 separately.
982
f4453dfa
NC		 9832004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
984
985 * m32r-asm.c: Regenerate.
986
9b0de91a
SS		 9872004-03-29 Stan Shebs <shebs@apple.com>
988
989 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
990 used.
991
e20c0b3d
AM		 9922004-03-19 Alan Modra <amodra@bigpond.net.au>
993
994 * aclocal.m4: Regenerate.
995 * config.in: Regenerate.
996 * configure: Regenerate.
997 * po/POTFILES.in: Regenerate.
998 * po/opcodes.pot: Regenerate.
999
fdd12ef3
AM		 10002004-03-16 Alan Modra <amodra@bigpond.net.au>
1001
1002 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
1003 PPC_OPERANDS_GPR_0.
1004 * ppc-opc.c (RA0): Define.
1005 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
1006 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 1007 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 1008
2dc111b3 10092004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 1010
1011 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 1012
7bfeee7b
AM		 10132004-03-15 Alan Modra <amodra@bigpond.net.au>
1014
1015 * sparc-dis.c (print_insn_sparc): Update getword prototype.
1016
7ffdda93
ML		 10172004-03-12 Michal Ludvig <mludvig@suse.cz>
1018
1019 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 1020 (grps): Delete GRPPLOCK entry.
7ffdda93 1021
cc0ec051
AM		 10222004-03-12 Alan Modra <amodra@bigpond.net.au>
1023
1024 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
1025 (M, Mp): Use OP_M.
1026 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
1027 (GRPPADLCK): Define.
1028 (dis386): Use NOP_Fixup on "nop".
1029 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
1030 (twobyte_has_modrm): Set for 0xa7.
1031 (padlock_table): Delete. Move to..
1032 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
1033 and clflush.
1034 (print_insn): Revert PADLOCK_SPECIAL code.
1035 (OP_E): Delete sfence, lfence, mfence checks.
1036
4fd61dcb
JJ		 10372004-03-12 Jakub Jelinek <jakub@redhat.com>
1038
1039 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
1040 (INVLPG_Fixup): New function.
1041 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
1042
0f10071e
ML		 10432004-03-12 Michal Ludvig <mludvig@suse.cz>
1044
1045 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
1046 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
1047 (padlock_table): New struct with PadLock instructions.
1048 (print_insn): Handle PADLOCK_SPECIAL.
1049
c02908d2
AM		 10502004-03-12 Alan Modra <amodra@bigpond.net.au>
1051
1052 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
1053 (OP_E): Twiddle clflush to sfence here.
1054
d5bb7600
NC		 10552004-03-08 Nick Clifton <nickc@redhat.com>
1056
1057 * po/de.po: Updated German translation.
1058
ae51a426
JR		 10592003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
1060
1061 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
1062 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
1063 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
1064 accordingly.
1065
676a64f4
RS		 10662004-03-01 Richard Sandiford <rsandifo@redhat.com>
1067
1068 * frv-asm.c: Regenerate.
1069 * frv-desc.c: Regenerate.
1070 * frv-desc.h: Regenerate.
1071 * frv-dis.c: Regenerate.
1072 * frv-ibld.c: Regenerate.
1073 * frv-opc.c: Regenerate.
1074 * frv-opc.h: Regenerate.
1075
c7a48b9a
RS		 10762004-03-01 Richard Sandiford <rsandifo@redhat.com>
1077
1078 * frv-desc.c, frv-opc.c: Regenerate.
1079
8ae0baa2
RS		 10802004-03-01 Richard Sandiford <rsandifo@redhat.com>
1081
1082 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
1083
ce11586c
JR		 10842004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1085
1086 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
1087 Also correct mistake in the comment.
1088
6a5709a5
JR		 10892004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1090
1091 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
1092 ensure that double registers have even numbers.
1093 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
1094 that reserved instruction 0xfffd does not decode the same
1095 as 0xfdfd (ftrv).
1096 * sh-opc.h: Add REG_N_D nibble type and use it whereever
1097 REG_N refers to a double register.
1098 Add REG_N_B01 nibble type and use it instead of REG_NM
1099 in ftrv.
1100 Adjust the bit patterns in a few comments.
1101
e5d2b64f 11022004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1103
1104 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 1105
1f04b05f
AH		 11062004-02-20 Aldy Hernandez <aldyh@redhat.com>
1107
1108 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
1109
2f3b8700
AH		 11102004-02-20 Aldy Hernandez <aldyh@redhat.com>
1111
1112 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
1113
f0b26da6 11142004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1115
1116 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1117 mtivor32, mtivor33, mtivor34.
f0b26da6 1118
23d59c56 11192004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1120
1121 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 1122
34920d91
NC		 11232004-02-10 Petko Manolov <petkan@nucleusys.com>
1124
1125 * arm-opc.h Maverick accumulator register opcode fixes.
1126
44d86481
BE		 11272004-02-13 Ben Elliston <bje@wasabisystems.com>
1128
1129 * m32r-dis.c: Regenerate.
1130
17707c23
MS		 11312004-01-27 Michael Snyder <msnyder@redhat.com>
1132
1133 * sh-opc.h (sh_table): "fsrra", not "fssra".
1134
fe3a9bc4
NC		 11352004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1136
1137 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1138 contraints.
1139
ff24f124
JJ		 11402004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1141
1142 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1143
a02a862a
AM		 11442004-01-19 Alan Modra <amodra@bigpond.net.au>
1145
1146 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1147 1. Don't print scale factor on AT&T mode when index missing.
1148
d164ea7f
AO		 11492004-01-16 Alexandre Oliva <aoliva@redhat.com>
1150
1151 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1152 when loaded into XR registers.
1153
cb10e79a
RS		 11542004-01-14 Richard Sandiford <rsandifo@redhat.com>
1155
1156 * frv-desc.h: Regenerate.
1157 * frv-desc.c: Regenerate.
1158 * frv-opc.c: Regenerate.
1159
f532f3fa
MS		 11602004-01-13 Michael Snyder <msnyder@redhat.com>
1161
1162 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1163
e45d0630
PB		 11642004-01-09 Paul Brook <paul@codesourcery.com>
1165
1166 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1167 specific opcodes.
1168
3ba7a1aa
DJ		 11692004-01-07 Daniel Jacobowitz <drow@mvista.com>
1170
1171 * Makefile.am (libopcodes_la_DEPENDENCIES)
1172 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1173 comment about the problem.
1174 * Makefile.in: Regenerate.
1175
ba2d3f07
AO		 11762004-01-06 Alexandre Oliva <aoliva@redhat.com>
1177
1178 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1179 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1180 cut&paste errors in shifting/truncating numerical operands.
1181 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1182 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1183 (parse_uslo16): Likewise.
1184 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1185 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1186 (parse_s12): Likewise.
1187 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1188 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1189 (parse_uslo16): Likewise.
1190 (parse_uhi16): Parse gothi and gotfuncdeschi.
1191 (parse_d12): Parse got12 and gotfuncdesc12.
1192 (parse_s12): Likewise.
1193
3ab48931
NC		 11942004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1195
1196 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1197 instruction which looks similar to an 'rla' instruction.
a0bd404e 1198
c9e214e5 1199For older changes see ChangeLog-0203
252b5132
RH		 1200\f
1201Local Variables:
2f6d2f85
NC		 1202mode: change-log
1203left-margin: 8
1204fill-column: 74
252b5132
RH		 1205version-control: never
1206End:
GDB Binutils - Deliverables
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