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x86: re-work operand handling for 5-operand XOP insns
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
93abb146
JB		 12020-07-08 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
4 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
5 OP_EX_VexReg): Delete.
6 (OP_VexI4, VexI4): New.
7 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
8 (prefix_table): ... here.
9 (print_insn): Drop setting of vex_w_done.
10
b13b1bc0
JB		 112020-07-08 Jan Beulich <jbeulich@suse.com>
12
13 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
14 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
15 (xop_table): Replace operands of 4-operand insns.
16 (OP_REG_VexI4): Move VEX.W based operand swaping here.
17
f337259f
CZ		 182020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
19
20 * arc-opc.c (insert_rbd): New function.
21 (RBD): Define.
22 (RBDdup): Likewise.
23 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
24 instructions.
25
931452b6
JB		 262020-07-07 Jan Beulich <jbeulich@suse.com>
27
28 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
29 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
30 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
31 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
32 Delete.
33 (putop): Handle "BW".
34 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
35 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
36 and 0F3A3F ...
37 * i386-dis-evex-prefix.h: ... here.
38
b5b098c2
JB		 392020-07-06 Jan Beulich <jbeulich@suse.com>
40
41 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
42 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
43 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
44 VEX_W_0FXOP_09_83): New enumerators.
45 (xop_table): Reference the above.
46 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
47 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
48 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
49 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
50
21a3faeb
JB		 512020-07-06 Jan Beulich <jbeulich@suse.com>
52
53 * i386-dis.c (EVEX_W_0F3838_P_1,
54 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
55 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
56 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
57 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
58 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
59 (putop): Centralize management of last[]. Delete SAVE_LAST.
60 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
61 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
62 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
63 * i386-dis-evex-prefix.h: here.
64
bc152a17
JB		 652020-07-06 Jan Beulich <jbeulich@suse.com>
66
67 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
68 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
69 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
70 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
71 enumerators.
72 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
73 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
74 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
75 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
76 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
77 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
78 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
79 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
80 these, respectively.
81 * i386-dis-evex-len.h: Adjust comments.
82 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
83 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
84 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
85 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
86 MOD_EVEX_0F385B_P_2_W_1 table entries.
87 * i386-dis-evex-w.h: Reference mod_table[] for
88 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
89 EVEX_W_0F385B_P_2.
90
c82a99a0
JB		 912020-07-06 Jan Beulich <jbeulich@suse.com>
92
93 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
94 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
95 EXymm.
96 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
97 Likewise. Mark 256-bit entries invalid.
98
fedfb81e
JB		 992020-07-06 Jan Beulich <jbeulich@suse.com>
100
101 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
102 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
103 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
104 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
105 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
106 PREFIX_EVEX_0F382B): Delete.
107 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
108 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
109 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
110 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
111 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
112 to ...
113 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
114 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
115 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
116 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
117 respectively.
118 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
119 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
120 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
121 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
122 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
123 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
124 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
125 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
126 PREFIX_EVEX_0F382B): Remove table entries.
127 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
128 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
129 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
130
3a57774c
JB		 1312020-07-06 Jan Beulich <jbeulich@suse.com>
132
133 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
134 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
135 enumerators.
136 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
137 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
138 EVEX_LEN_0F3A01_P_2_W_1 table entries.
139 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
140 entries.
141
e74d9fa9
JB		 1422020-07-06 Jan Beulich <jbeulich@suse.com>
143
144 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
145 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
146 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
147 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
148 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
149 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
150 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
151 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
152 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
153 entries.
154
6431c801
JB		 1552020-07-06 Jan Beulich <jbeulich@suse.com>
156
157 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
158 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
159 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
160 respectively.
161 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
162 entries.
163 * i386-dis-evex.h (evex_table): Reference VEX table entry for
164 opcode 0F3A1D.
165 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
166 entry.
167 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
168
6df22cf6
JB		 1692020-07-06 Jan Beulich <jbeulich@suse.com>
170
171 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
172 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
173 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
174 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
175 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
176 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
177 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
178 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
179 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
180 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
181 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
182 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
183 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
184 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
185 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
186 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
187 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
188 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
189 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
190 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
191 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
192 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
193 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
194 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
195 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
196 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
197 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
198 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
199 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
200 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
201 (prefix_table): Add EXxEVexR to FMA table entries.
202 (OP_Rounding): Move abort() invocation.
203 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
204 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
205 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
206 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
207 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
208 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
209 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
210 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
211 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
212 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
213 0F3ACE, 0F3ACF.
214 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
215 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
216 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
217 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
218 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
219 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
220 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
221 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
222 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
223 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
224 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
225 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
226 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
227 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
228 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
229 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
230 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
231 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
232 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
233 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
234 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
235 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
236 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
237 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
238 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
239 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
240 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
241 Delete table entries.
242 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
243 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
244 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
245 Likewise.
246
39e0f456
JB		 2472020-07-06 Jan Beulich <jbeulich@suse.com>
248
249 * i386-dis.c (EXqScalarS): Delete.
250 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
251 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
252
5b872f7d
JB		 2532020-07-06 Jan Beulich <jbeulich@suse.com>
254
255 * i386-dis.c (safe-ctype.h): Include.
256 (EXdScalar, EXqScalar): Delete.
257 (d_scalar_mode, q_scalar_mode): Delete.
258 (prefix_table, vex_len_table): Use EXxmm_md in place of
259 EXdScalar and EXxmm_mq in place of EXqScalar.
260 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
261 d_scalar_mode and q_scalar_mode.
262 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
263 (vmovsd): Use EXxmm_mq.
264
ddc73fa9
NC		 2652020-07-06 Yuri Chornoivan <yurchor@ukr.net>
266
267 PR 26204
268 * arc-dis.c: Fix spelling mistake.
269 * po/opcodes.pot: Regenerate.
270
17550be7
NC		 2712020-07-06 Nick Clifton <nickc@redhat.com>
272
273 * po/pt_BR.po: Updated Brazilian Portugugese translation.
274 * po/uk.po: Updated Ukranian translation.
275
b19d852d
NC		 2762020-07-04 Nick Clifton <nickc@redhat.com>
277
278 * configure: Regenerate.
279 * po/opcodes.pot: Regenerate.
280
b115b9fd
NC		 2812020-07-04 Nick Clifton <nickc@redhat.com>
282
283 Binutils 2.35 branch created.
284
c2ecccb3
L		 2852020-07-02 H.J. Lu <hongjiu.lu@intel.com>
286
287 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
288 * i386-opc.h (VexSwapSources): New.
289 (i386_opcode_modifier): Add vexswapsources.
290 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
291 with two source operands swapped.
292 * i386-tbl.h: Regenerated.
293
08ccfccf
NC		 2942020-06-30 Nelson Chu <nelson.chu@sifive.com>
295
296 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
297 unprivileged CSR can also be initialized.
298
279edac5
AM		 2992020-06-29 Alan Modra <amodra@gmail.com>
300
301 * arm-dis.c: Use C style comments.
302 * cr16-opc.c: Likewise.
303 * ft32-dis.c: Likewise.
304 * moxie-opc.c: Likewise.
305 * tic54x-dis.c: Likewise.
306 * s12z-opc.c: Remove useless comment.
307 * xgate-dis.c: Likewise.
308
e978ad62
L		 3092020-06-26 H.J. Lu <hongjiu.lu@intel.com>
310
311 * i386-opc.tbl: Add a blank line.
312
63112cd6
L		 3132020-06-26 H.J. Lu <hongjiu.lu@intel.com>
314
315 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
316 (VecSIB128): Renamed to ...
317 (VECSIB128): This.
318 (VecSIB256): Renamed to ...
319 (VECSIB256): This.
320 (VecSIB512): Renamed to ...
321 (VECSIB512): This.
322 (VecSIB): Renamed to ...
323 (SIB): This.
324 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 325 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 326 (VecSIB256): Likewise.
327 (VecSIB512): Likewise.
79b32e73 328 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 329 and VecSIB512, respectively.
330
d1c36125
JB		 3312020-06-26 Jan Beulich <jbeulich@suse.com>
332
333 * i386-dis.c: Adjust description of I macro.
334 (x86_64_table): Drop use of I.
335 (float_mem): Replace use of I.
336 (putop): Remove handling of I. Adjust setting/clearing of "alt".
337
2a1bb84c
JB		 3382020-06-26 Jan Beulich <jbeulich@suse.com>
339
340 * i386-dis.c: (print_insn): Avoid straight assignment to
341 priv.orig_sizeflag when processing -M sub-options.
342
8f570d62
JB		 3432020-06-25 Jan Beulich <jbeulich@suse.com>
344
345 * i386-dis.c: Adjust description of J macro.
346 (dis386, x86_64_table, mod_table): Replace J.
347 (putop): Remove handling of J.
348
464dc4af
JB		 3492020-06-25 Jan Beulich <jbeulich@suse.com>
350
351 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
352
589958d6
JB		 3532020-06-25 Jan Beulich <jbeulich@suse.com>
354
355 * i386-dis.c: Adjust description of "LQ" macro.
356 (dis386_twobyte): Use LQ for sysret.
357 (putop): Adjust handling of LQ.
358
39ff0b81
NC		 3592020-06-22 Nelson Chu <nelson.chu@sifive.com>
360
361 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
362 * riscv-dis.c: Include elfxx-riscv.h.
363
d27c357a
JB		 3642020-06-18 H.J. Lu <hongjiu.lu@intel.com>
365
366 * i386-dis.c (prefix_table): Revert the last vmgexit change.
367
6fde587f
CL		 3682020-06-17 Lili Cui <lili.cui@intel.com>
369
370 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
371
efe30057
L		 3722020-06-14 H.J. Lu <hongjiu.lu@intel.com>
373
374 PR gas/26115
375 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
376 * i386-opc.tbl: Likewise.
377 * i386-tbl.h: Regenerated.
378
d8af286f
NC		 3792020-06-12 Nelson Chu <nelson.chu@sifive.com>
380
381 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
382
14962256
AC		 3832020-06-11 Alex Coplan <alex.coplan@arm.com>
384
385 * aarch64-opc.c (SYSREG): New macro for describing system registers.
386 (SR_CORE): Likewise.
387 (SR_FEAT): Likewise.
388 (SR_RNG): Likewise.
389 (SR_V8_1): Likewise.
390 (SR_V8_2): Likewise.
391 (SR_V8_3): Likewise.
392 (SR_V8_4): Likewise.
393 (SR_PAN): Likewise.
394 (SR_RAS): Likewise.
395 (SR_SSBS): Likewise.
396 (SR_SVE): Likewise.
397 (SR_ID_PFR2): Likewise.
398 (SR_PROFILE): Likewise.
399 (SR_MEMTAG): Likewise.
400 (SR_SCXTNUM): Likewise.
401 (aarch64_sys_regs): Refactor to store feature information in the table.
402 (aarch64_sys_reg_supported_p): Collapse logic for system registers
403 that now describe their own features.
404 (aarch64_pstatefield_supported_p): Likewise.
405
f9630fa6
L		 4062020-06-09 H.J. Lu <hongjiu.lu@intel.com>
407
408 * i386-dis.c (prefix_table): Fix a typo in comments.
409
73239888
JB		 4102020-06-09 Jan Beulich <jbeulich@suse.com>
411
412 * i386-dis.c (rex_ignored): Delete.
413 (ckprefix): Drop rex_ignored initialization.
414 (get_valid_dis386): Drop setting of rex_ignored.
415 (print_insn): Drop checking of rex_ignored. Don't record data
416 size prefix as used with VEX-and-alike encodings.
417
18897deb
JB		 4182020-06-09 Jan Beulich <jbeulich@suse.com>
419
420 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
421 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
422 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
423 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
424 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
425 VEX_0F12, and VEX_0F16.
426 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
427 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
428 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
429 from movlps and movhlps. New MOD_0F12_PREFIX_2,
430 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
431 MOD_VEX_0F16_PREFIX_2 entries.
432
97e6786a
JB		 4332020-06-09 Jan Beulich <jbeulich@suse.com>
434
435 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
436 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
437 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
438 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
439 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
440 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
441 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
442 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
443 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
444 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
445 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
446 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
447 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
448 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
449 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
450 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
451 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
452 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
453 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
454 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
455 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
456 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
457 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
458 EVEX_W_0FC6_P_2): Delete.
459 (print_insn): Add EVEX.W vs embedded prefix consistency check
460 to prefix validation.
461 * i386-dis-evex.h (evex_table): Don't further descend for
462 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
463 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
464 and 0F2B.
465 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
466 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
467 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
468 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
469 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
470 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
471 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
472 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
473 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
474 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
475 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
476 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
477 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
478 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
479 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
480 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
481 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
482 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
483 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
484 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
485 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
486 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
487 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
488 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
489 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
490 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
491 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
492
bf926894
JB		 4932020-06-09 Jan Beulich <jbeulich@suse.com>
494
495 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
496 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
497 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
498 vmovmskpX.
499 (print_insn): Drop pointless check against bad_opcode. Split
500 prefix validation into legacy and VEX-and-alike parts.
501 (putop): Re-work 'X' macro handling.
502
a5aaedb9
JB		 5032020-06-09 Jan Beulich <jbeulich@suse.com>
504
505 * i386-dis.c (MOD_0F51): Rename to ...
506 (MOD_0F50): ... this.
507
26417f19
AC		 5082020-06-08 Alex Coplan <alex.coplan@arm.com>
509
510 * arm-dis.c (arm_opcodes): Add dfb.
511 (thumb32_opcodes): Add dfb.
512
8a6fb3f9
JB		 5132020-06-08 Jan Beulich <jbeulich@suse.com>
514
515 * i386-opc.h (reg_entry): Const-qualify reg_name field.
516
1424c35d
AM		 5172020-06-06 Alan Modra <amodra@gmail.com>
518
519 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
520
d3d1cc7b
AM		 5212020-06-05 Alan Modra <amodra@gmail.com>
522
523 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
524 size is large enough.
525
d8740be1
JM		 5262020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
527
528 * disassemble.c (disassemble_init_for_target): Set endian_code for
529 bpf targets.
530 * bpf-desc.c: Regenerate.
531 * bpf-opc.c: Likewise.
532 * bpf-dis.c: Likewise.
533
e9bffec9
JM		 5342020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
535
536 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
537 (cgen_put_insn_value): Likewise.
538 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
539 * cgen-dis.in (print_insn): Likewise.
540 * cgen-ibld.in (insert_1): Likewise.
541 (insert_1): Likewise.
542 (insert_insn_normal): Likewise.
543 (extract_1): Likewise.
544 * bpf-dis.c: Regenerate.
545 * bpf-ibld.c: Likewise.
546 * bpf-ibld.c: Likewise.
547 * cgen-dis.in: Likewise.
548 * cgen-ibld.in: Likewise.
549 * cgen-opc.c: Likewise.
550 * epiphany-dis.c: Likewise.
551 * epiphany-ibld.c: Likewise.
552 * fr30-dis.c: Likewise.
553 * fr30-ibld.c: Likewise.
554 * frv-dis.c: Likewise.
555 * frv-ibld.c: Likewise.
556 * ip2k-dis.c: Likewise.
557 * ip2k-ibld.c: Likewise.
558 * iq2000-dis.c: Likewise.
559 * iq2000-ibld.c: Likewise.
560 * lm32-dis.c: Likewise.
561 * lm32-ibld.c: Likewise.
562 * m32c-dis.c: Likewise.
563 * m32c-ibld.c: Likewise.
564 * m32r-dis.c: Likewise.
565 * m32r-ibld.c: Likewise.
566 * mep-dis.c: Likewise.
567 * mep-ibld.c: Likewise.
568 * mt-dis.c: Likewise.
569 * mt-ibld.c: Likewise.
570 * or1k-dis.c: Likewise.
571 * or1k-ibld.c: Likewise.
572 * xc16x-dis.c: Likewise.
573 * xc16x-ibld.c: Likewise.
574 * xstormy16-dis.c: Likewise.
575 * xstormy16-ibld.c: Likewise.
576
b3db6d07
JM		 5772020-06-04 Jose E. Marchesi <jemarch@gnu.org>
578
579 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
580 (print_insn_): Handle instruction endian.
581 * bpf-dis.c: Regenerate.
582 * bpf-desc.c: Regenerate.
583 * epiphany-dis.c: Likewise.
584 * epiphany-desc.c: Likewise.
585 * fr30-dis.c: Likewise.
586 * fr30-desc.c: Likewise.
587 * frv-dis.c: Likewise.
588 * frv-desc.c: Likewise.
589 * ip2k-dis.c: Likewise.
590 * ip2k-desc.c: Likewise.
591 * iq2000-dis.c: Likewise.
592 * iq2000-desc.c: Likewise.
593 * lm32-dis.c: Likewise.
594 * lm32-desc.c: Likewise.
595 * m32c-dis.c: Likewise.
596 * m32c-desc.c: Likewise.
597 * m32r-dis.c: Likewise.
598 * m32r-desc.c: Likewise.
599 * mep-dis.c: Likewise.
600 * mep-desc.c: Likewise.
601 * mt-dis.c: Likewise.
602 * mt-desc.c: Likewise.
603 * or1k-dis.c: Likewise.
604 * or1k-desc.c: Likewise.
605 * xc16x-dis.c: Likewise.
606 * xc16x-desc.c: Likewise.
607 * xstormy16-dis.c: Likewise.
608 * xstormy16-desc.c: Likewise.
609
4ee4189f
NC		 6102020-06-03 Nick Clifton <nickc@redhat.com>
611
612 * po/sr.po: Updated Serbian translation.
613
44730156
NC		 6142020-06-03 Nelson Chu <nelson.chu@sifive.com>
615
616 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
617 (riscv_get_priv_spec_class): Likewise.
618
3c3d0376
AM		 6192020-06-01 Alan Modra <amodra@gmail.com>
620
621 * bpf-desc.c: Regenerate.
622
78c1c354
JM		 6232020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
624 David Faust <david.faust@oracle.com>
625
626 * bpf-desc.c: Regenerate.
627 * bpf-opc.h: Likewise.
628 * bpf-opc.c: Likewise.
629 * bpf-dis.c: Likewise.
630
efcf5fb5
AM		 6312020-05-28 Alan Modra <amodra@gmail.com>
632
633 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
634 values.
635
ab382d64
AM		 6362020-05-28 Alan Modra <amodra@gmail.com>
637
638 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
639 immediates.
640 (print_insn_ns32k): Revert last change.
641
151f5de4
NC		 6422020-05-28 Nick Clifton <nickc@redhat.com>
643
644 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
645 static.
646
25e1eca8
SL		 6472020-05-26 Sandra Loosemore <sandra@codesourcery.com>
648
649 Fix extraction of signed constants in nios2 disassembler (again).
650
651 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
652 extractions of signed fields.
653
57b17940
SSF		 6542020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
655
656 * s390-opc.txt: Relocate vector load/store instructions with
657 additional alignment parameter and change architecture level
658 constraint from z14 to z13.
659
d96bf37b
AM		 6602020-05-21 Alan Modra <amodra@gmail.com>
661
662 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
663 * sparc-dis.c: Likewise.
664 * tic4x-dis.c: Likewise.
665 * xtensa-dis.c: Likewise.
666 * bpf-desc.c: Regenerate.
667 * epiphany-desc.c: Regenerate.
668 * fr30-desc.c: Regenerate.
669 * frv-desc.c: Regenerate.
670 * ip2k-desc.c: Regenerate.
671 * iq2000-desc.c: Regenerate.
672 * lm32-desc.c: Regenerate.
673 * m32c-desc.c: Regenerate.
674 * m32r-desc.c: Regenerate.
675 * mep-asm.c: Regenerate.
676 * mep-desc.c: Regenerate.
677 * mt-desc.c: Regenerate.
678 * or1k-desc.c: Regenerate.
679 * xc16x-desc.c: Regenerate.
680 * xstormy16-desc.c: Regenerate.
681
8f595e9b
NC		 6822020-05-20 Nelson Chu <nelson.chu@sifive.com>
683
684 * riscv-opc.c (riscv_ext_version_table): The table used to store
685 all information about the supported spec and the corresponding ISA
686 versions. Currently, only Zicsr is supported to verify the
687 correctness of Z sub extension settings. Others will be supported
688 in the future patches.
689 (struct isa_spec_t, isa_specs): List for all supported ISA spec
690 classes and the corresponding strings.
691 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
692 spec class by giving a ISA spec string.
693 * riscv-opc.c (struct priv_spec_t): New structure.
694 (struct priv_spec_t priv_specs): List for all supported privilege spec
695 classes and the corresponding strings.
696 (riscv_get_priv_spec_class): New function. Get the corresponding
697 privilege spec class by giving a spec string.
698 (riscv_get_priv_spec_name): New function. Get the corresponding
699 privilege spec string by giving a CSR version class.
700 * riscv-dis.c: Updated since DECLARE_CSR is changed.
701 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
702 according to the chosen version. Build a hash table riscv_csr_hash to
703 store the valid CSR for the chosen pirv verison. Dump the direct
704 CSR address rather than it's name if it is invalid.
705 (parse_riscv_dis_option_without_args): New function. Parse the options
706 without arguments.
707 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
708 parse the options without arguments first, and then handle the options
709 with arguments. Add the new option -Mpriv-spec, which has argument.
710 * riscv-dis.c (print_riscv_disassembler_options): Add description
711 about the new OBJDUMP option.
712
3d205eb4
PB		 7132020-05-19 Peter Bergner <bergner@linux.ibm.com>
714
715 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
716 WC values on POWER10 sync, dcbf and wait instructions.
717 (insert_pl, extract_pl): New functions.
718 (L2OPT, LS, WC): Use insert_ls and extract_ls.
719 (LS3): New , 3-bit L for sync.
720 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
721 (SC2, PL): New, 2-bit SC and PL for sync and wait.
722 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
723 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
724 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
725 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
726 <wait>: Enable PL operand on POWER10.
727 <dcbf>: Enable L3OPT operand on POWER10.
728 <sync>: Enable SC2 operand on POWER10.
729
a501eb44
SH		 7302020-05-19 Stafford Horne <shorne@gmail.com>
731
732 PR 25184
733 * or1k-asm.c: Regenerate.
734 * or1k-desc.c: Regenerate.
735 * or1k-desc.h: Regenerate.
736 * or1k-dis.c: Regenerate.
737 * or1k-ibld.c: Regenerate.
738 * or1k-opc.c: Regenerate.
739 * or1k-opc.h: Regenerate.
740 * or1k-opinst.c: Regenerate.
741
3b646889
AM		 7422020-05-11 Alan Modra <amodra@gmail.com>
743
744 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
745 xsmaxcqp, xsmincqp.
746
9cc4ce88
AM		 7472020-05-11 Alan Modra <amodra@gmail.com>
748
749 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
750 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
751
5d57bc3f
AM		 7522020-05-11 Alan Modra <amodra@gmail.com>
753
754 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
755
66ef5847
AM		 7562020-05-11 Alan Modra <amodra@gmail.com>
757
758 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
759 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
760
4f3e9537
PB		 7612020-05-11 Peter Bergner <bergner@linux.ibm.com>
762
763 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
764 mnemonics.
765
ec40e91c
AM		 7662020-05-11 Alan Modra <amodra@gmail.com>
767
768 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
769 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
770 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
771 (prefix_opcodes): Add xxeval.
772
d7e97a76
AM		 7732020-05-11 Alan Modra <amodra@gmail.com>
774
775 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
776 xxgenpcvwm, xxgenpcvdm.
777
fdefed7c
AM		 7782020-05-11 Alan Modra <amodra@gmail.com>
779
780 * ppc-opc.c (MP, VXVAM_MASK): Define.
781 (VXVAPS_MASK): Use VXVA_MASK.
782 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
783 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
784 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
785 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
786
aa3c112f
AM		 7872020-05-11 Alan Modra <amodra@gmail.com>
788 Peter Bergner <bergner@linux.ibm.com>
789
790 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
791 New functions.
792 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
793 YMSK2, XA6a, XA6ap, XB6a entries.
794 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
795 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
796 (PPCVSX4): Define.
797 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
798 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
799 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
800 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
801 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
802 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
803 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
804 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
805 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
806 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
807 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
808 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
809 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
810 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
811
6edbfd3b
AM		 8122020-05-11 Alan Modra <amodra@gmail.com>
813
814 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
815 (insert_xts, extract_xts): New functions.
816 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
817 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
818 (VXRC_MASK, VXSH_MASK): Define.
819 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
820 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
821 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
822 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
823 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
824 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
825 xxblendvh, xxblendvw, xxblendvd, xxpermx.
826
c7d7aea2
AM		 8272020-05-11 Alan Modra <amodra@gmail.com>
828
829 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
830 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
831 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
832 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
833 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
834
94ba9882
AM		 8352020-05-11 Alan Modra <amodra@gmail.com>
836
837 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
838 (XTP, DQXP, DQXP_MASK): Define.
839 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
840 (prefix_opcodes): Add plxvp and pstxvp.
841
f4791f1a
AM		 8422020-05-11 Alan Modra <amodra@gmail.com>
843
844 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
845 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
846 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
847
3ff0a5ba
PB		 8482020-05-11 Peter Bergner <bergner@linux.ibm.com>
849
850 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
851
afef4fe9
PB		 8522020-05-11 Peter Bergner <bergner@linux.ibm.com>
853
854 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
855 (L1OPT): Define.
856 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
857
1224c05d
PB		 8582020-05-11 Peter Bergner <bergner@linux.ibm.com>
859
860 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
861
6bbb0c05
AM		 8622020-05-11 Alan Modra <amodra@gmail.com>
863
864 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
865
7c1f4227
AM		 8662020-05-11 Alan Modra <amodra@gmail.com>
867
868 * ppc-dis.c (ppc_opts): Add "power10" entry.
869 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
870 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
871
73199c2b
NC		 8722020-05-11 Nick Clifton <nickc@redhat.com>
873
874 * po/fr.po: Updated French translation.
875
09c1e68a
AC		 8762020-04-30 Alex Coplan <alex.coplan@arm.com>
877
878 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
879 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
880 (operand_general_constraint_met_p): validate
881 AARCH64_OPND_UNDEFINED.
882 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
883 for FLD_imm16_2.
884 * aarch64-asm-2.c: Regenerated.
885 * aarch64-dis-2.c: Regenerated.
886 * aarch64-opc-2.c: Regenerated.
887
9654d51a
NC		 8882020-04-29 Nick Clifton <nickc@redhat.com>
889
890 PR 22699
891 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
892 and SETRC insns.
893
c2e71e57
NC		 8942020-04-29 Nick Clifton <nickc@redhat.com>
895
896 * po/sv.po: Updated Swedish translation.
897
5c936ef5
NC		 8982020-04-29 Nick Clifton <nickc@redhat.com>
899
900 PR 22699
901 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
902 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
903 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
904 IMM0_8U case.
905
bb2a1453
AS		 9062020-04-21 Andreas Schwab <schwab@linux-m68k.org>
907
908 PR 25848
909 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
910 cmpi only on m68020up and cpu32.
911
c2e5c986
SD		 9122020-04-20 Sudakshina Das <sudi.das@arm.com>
913
914 * aarch64-asm.c (aarch64_ins_none): New.
915 * aarch64-asm.h (ins_none): New declaration.
916 * aarch64-dis.c (aarch64_ext_none): New.
917 * aarch64-dis.h (ext_none): New declaration.
918 * aarch64-opc.c (aarch64_print_operand): Update case for
919 AARCH64_OPND_BARRIER_PSB.
920 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
921 (AARCH64_OPERANDS): Update inserter/extracter for
922 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
923 * aarch64-asm-2.c: Regenerated.
924 * aarch64-dis-2.c: Regenerated.
925 * aarch64-opc-2.c: Regenerated.
926
8a6e1d1d
SD		 9272020-04-20 Sudakshina Das <sudi.das@arm.com>
928
929 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
930 (aarch64_feature_ras, RAS): Likewise.
931 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
932 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
933 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
934 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
935 * aarch64-asm-2.c: Regenerated.
936 * aarch64-dis-2.c: Regenerated.
937 * aarch64-opc-2.c: Regenerated.
938
e409955d
FS		 9392020-04-17 Fredrik Strupe <fredrik@strupe.net>
940
941 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
942 (print_insn_neon): Support disassembly of conditional
943 instructions.
944
c54a9b56
DF		 9452020-02-16 David Faust <david.faust@oracle.com>
946
947 * bpf-desc.c: Regenerate.
948 * bpf-desc.h: Likewise.
949 * bpf-opc.c: Regenerate.
950 * bpf-opc.h: Likewise.
951
bb651e8b
CL		 9522020-04-07 Lili Cui <lili.cui@intel.com>
953
954 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
955 (prefix_table): New instructions (see prefixes above).
956 (rm_table): Likewise
957 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
958 CPU_ANY_TSXLDTRK_FLAGS.
959 (cpu_flags): Add CpuTSXLDTRK.
960 * i386-opc.h (enum): Add CpuTSXLDTRK.
961 (i386_cpu_flags): Add cputsxldtrk.
962 * i386-opc.tbl: Add XSUSPLDTRK insns.
963 * i386-init.h: Regenerate.
964 * i386-tbl.h: Likewise.
965
4b27d27c
L		 9662020-04-02 Lili Cui <lili.cui@intel.com>
967
968 * i386-dis.c (prefix_table): New instructions serialize.
969 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
970 CPU_ANY_SERIALIZE_FLAGS.
971 (cpu_flags): Add CpuSERIALIZE.
972 * i386-opc.h (enum): Add CpuSERIALIZE.
973 (i386_cpu_flags): Add cpuserialize.
974 * i386-opc.tbl: Add SERIALIZE insns.
975 * i386-init.h: Regenerate.
976 * i386-tbl.h: Likewise.
977
832a5807
AM		 9782020-03-26 Alan Modra <amodra@gmail.com>
979
980 * disassemble.h (opcodes_assert): Declare.
981 (OPCODES_ASSERT): Define.
982 * disassemble.c: Don't include assert.h. Include opintl.h.
983 (opcodes_assert): New function.
984 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
985 (bfd_h8_disassemble): Reduce size of data array. Correctly
986 calculate maxlen. Omit insn decoding when insn length exceeds
987 maxlen. Exit from nibble loop when looking for E, before
988 accessing next data byte. Move processing of E outside loop.
989 Replace tests of maxlen in loop with assertions.
990
4c4addbe
AM		 9912020-03-26 Alan Modra <amodra@gmail.com>
992
993 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
994
a18cd0ca
AM		 9952020-03-25 Alan Modra <amodra@gmail.com>
996
997 * z80-dis.c (suffix): Init mybuf.
998
57cb32b3
AM		 9992020-03-22 Alan Modra <amodra@gmail.com>
1000
1001 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1002 successflly read from section.
1003
beea5cc1
AM		 10042020-03-22 Alan Modra <amodra@gmail.com>
1005
1006 * arc-dis.c (find_format): Use ISO C string concatenation rather
1007 than line continuation within a string. Don't access needs_limm
1008 before testing opcode != NULL.
1009
03704c77
AM		 10102020-03-22 Alan Modra <amodra@gmail.com>
1011
1012 * ns32k-dis.c (print_insn_arg): Update comment.
1013 (print_insn_ns32k): Reduce size of index_offset array, and
1014 initialize, passing -1 to print_insn_arg for args that are not
1015 an index. Don't exit arg loop early. Abort on bad arg number.
1016
d1023b5d
AM		 10172020-03-22 Alan Modra <amodra@gmail.com>
1018
1019 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1020 * s12z-opc.c: Formatting.
1021 (operands_f): Return an int.
1022 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1023 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1024 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1025 (exg_sex_discrim): Likewise.
1026 (create_immediate_operand, create_bitfield_operand),
1027 (create_register_operand_with_size, create_register_all_operand),
1028 (create_register_all16_operand, create_simple_memory_operand),
1029 (create_memory_operand, create_memory_auto_operand): Don't
1030 segfault on malloc failure.
1031 (z_ext24_decode): Return an int status, negative on fail, zero
1032 on success.
1033 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1034 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1035 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1036 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1037 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1038 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1039 (loop_primitive_decode, shift_decode, psh_pul_decode),
1040 (bit_field_decode): Similarly.
1041 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1042 to return value, update callers.
1043 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1044 Don't segfault on NULL operand.
1045 (decode_operation): Return OP_INVALID on first fail.
1046 (decode_s12z): Check all reads, returning -1 on fail.
1047
340f3ac8
AM		 10482020-03-20 Alan Modra <amodra@gmail.com>
1049
1050 * metag-dis.c (print_insn_metag): Don't ignore status from
1051 read_memory_func.
1052
fe90ae8a
AM		 10532020-03-20 Alan Modra <amodra@gmail.com>
1054
1055 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1056 Initialize parts of buffer not written when handling a possible
1057 2-byte insn at end of section. Don't attempt decoding of such
1058 an insn by the 4-byte machinery.
1059
833d919c
AM		 10602020-03-20 Alan Modra <amodra@gmail.com>
1061
1062 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1063 partially filled buffer. Prevent lookup of 4-byte insns when
1064 only VLE 2-byte insns are possible due to section size. Print
1065 ".word" rather than ".long" for 2-byte leftovers.
1066
327ef784
NC		 10672020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1068
1069 PR 25641
1070 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1071
1673df32
JB		 10722020-03-13 Jan Beulich <jbeulich@suse.com>
1073
1074 * i386-dis.c (X86_64_0D): Rename to ...
1075 (X86_64_0E): ... this.
1076
384f3689
L		 10772020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1078
1079 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1080 * Makefile.in: Regenerated.
1081
865e2027
JB		 10822020-03-09 Jan Beulich <jbeulich@suse.com>
1083
1084 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1085 3-operand pseudos.
1086 * i386-tbl.h: Re-generate.
1087
2f13234b
JB		 10882020-03-09 Jan Beulich <jbeulich@suse.com>
1089
1090 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1091 vprot*, vpsha*, and vpshl*.
1092 * i386-tbl.h: Re-generate.
1093
3fabc179
JB		 10942020-03-09 Jan Beulich <jbeulich@suse.com>
1095
1096 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1097 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1098 * i386-tbl.h: Re-generate.
1099
3677e4c1
JB		 11002020-03-09 Jan Beulich <jbeulich@suse.com>
1101
1102 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1103 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1104 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1105 * i386-tbl.h: Re-generate.
1106
4c4898e8
JB		 11072020-03-09 Jan Beulich <jbeulich@suse.com>
1108
1109 * i386-gen.c (struct template_arg, struct template_instance,
1110 struct template_param, struct template, templates,
1111 parse_template, expand_templates): New.
1112 (process_i386_opcodes): Various local variables moved to
1113 expand_templates. Call parse_template and expand_templates.
1114 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1115 * i386-tbl.h: Re-generate.
1116
bc49bfd8
JB		 11172020-03-06 Jan Beulich <jbeulich@suse.com>
1118
1119 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1120 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1121 register and memory source templates. Replace VexW= by VexW*
1122 where applicable.
1123 * i386-tbl.h: Re-generate.
1124
4873e243
JB		 11252020-03-06 Jan Beulich <jbeulich@suse.com>
1126
1127 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1128 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1129 * i386-tbl.h: Re-generate.
1130
672a349b
JB		 11312020-03-06 Jan Beulich <jbeulich@suse.com>
1132
1133 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1134 * i386-tbl.h: Re-generate.
1135
4ed21b58
JB		 11362020-03-06 Jan Beulich <jbeulich@suse.com>
1137
1138 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1139 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1140 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1141 VexW0 on SSE2AVX variants.
1142 (vmovq): Drop NoRex64 from XMM/XMM variants.
1143 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1144 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1145 applicable use VexW0.
1146 * i386-tbl.h: Re-generate.
1147
643bb870
JB		 11482020-03-06 Jan Beulich <jbeulich@suse.com>
1149
1150 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1151 * i386-opc.h (Rex64): Delete.
1152 (struct i386_opcode_modifier): Remove rex64 field.
1153 * i386-opc.tbl (crc32): Drop Rex64.
1154 Replace Rex64 with Size64 everywhere else.
1155 * i386-tbl.h: Re-generate.
1156
a23b33b3
JB		 11572020-03-06 Jan Beulich <jbeulich@suse.com>
1158
1159 * i386-dis.c (OP_E_memory): Exclude recording of used address
1160 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1161 addressed memory operands for MPX insns.
1162
a0497384
JB		 11632020-03-06 Jan Beulich <jbeulich@suse.com>
1164
1165 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1166 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1167 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1168 (ptwrite): Split into non-64-bit and 64-bit forms.
1169 * i386-tbl.h: Re-generate.
1170
b630c145
JB		 11712020-03-06 Jan Beulich <jbeulich@suse.com>
1172
1173 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1174 template.
1175 * i386-tbl.h: Re-generate.
1176
a847e322
JB		 11772020-03-04 Jan Beulich <jbeulich@suse.com>
1178
1179 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1180 (prefix_table): Move vmmcall here. Add vmgexit.
1181 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1182 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1183 (cpu_flags): Add CpuSEV_ES entry.
1184 * i386-opc.h (CpuSEV_ES): New.
1185 (union i386_cpu_flags): Add cpusev_es field.
1186 * i386-opc.tbl (vmgexit): New.
1187 * i386-init.h, i386-tbl.h: Re-generate.
1188
3cd7f3e3
L		 11892020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1190
1191 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1192 with MnemonicSize.
1193 * i386-opc.h (IGNORESIZE): New.
1194 (DEFAULTSIZE): Likewise.
1195 (IgnoreSize): Removed.
1196 (DefaultSize): Likewise.
1197 (MnemonicSize): New.
1198 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1199 mnemonicsize.
1200 * i386-opc.tbl (IgnoreSize): New.
1201 (DefaultSize): Likewise.
1202 * i386-tbl.h: Regenerated.
1203
b8ba1385
SB		 12042020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1205
1206 PR 25627
1207 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1208 instructions.
1209
10d97a0f
L		 12102020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1211
1212 PR gas/25622
1213 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1214 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1215 * i386-tbl.h: Regenerated.
1216
dc1e8a47
AM		 12172020-02-26 Alan Modra <amodra@gmail.com>
1218
1219 * aarch64-asm.c: Indent labels correctly.
1220 * aarch64-dis.c: Likewise.
1221 * aarch64-gen.c: Likewise.
1222 * aarch64-opc.c: Likewise.
1223 * alpha-dis.c: Likewise.
1224 * i386-dis.c: Likewise.
1225 * nds32-asm.c: Likewise.
1226 * nfp-dis.c: Likewise.
1227 * visium-dis.c: Likewise.
1228
265b4673
CZ		 12292020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1230
1231 * arc-regs.h (int_vector_base): Make it available for all ARC
1232 CPUs.
1233
bd0cf5a6
NC		 12342020-02-20 Nelson Chu <nelson.chu@sifive.com>
1235
1236 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1237 changed.
1238
fa164239
JW		 12392020-02-19 Nelson Chu <nelson.chu@sifive.com>
1240
1241 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1242 c.mv/c.li if rs1 is zero.
1243
272a84b1
L		 12442020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1245
1246 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1247 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1248 CPU_POPCNT_FLAGS.
1249 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1250 * i386-opc.h (CpuABM): Removed.
1251 (CpuPOPCNT): New.
1252 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1253 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1254 popcnt. Remove CpuABM from lzcnt.
1255 * i386-init.h: Regenerated.
1256 * i386-tbl.h: Likewise.
1257
1f730c46
JB		 12582020-02-17 Jan Beulich <jbeulich@suse.com>
1259
1260 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1261 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1262 VexW1 instead of open-coding them.
1263 * i386-tbl.h: Re-generate.
1264
c8f8eebc
JB		 12652020-02-17 Jan Beulich <jbeulich@suse.com>
1266
1267 * i386-opc.tbl (AddrPrefixOpReg): Define.
1268 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1269 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1270 templates. Drop NoRex64.
1271 * i386-tbl.h: Re-generate.
1272
b9915cbc
JB		 12732020-02-17 Jan Beulich <jbeulich@suse.com>
1274
1275 PR gas/6518
1276 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1277 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1278 into Intel syntax instance (with Unpsecified) and AT&T one
1279 (without).
1280 (vcvtneps2bf16): Likewise, along with folding the two so far
1281 separate ones.
1282 * i386-tbl.h: Re-generate.
1283
ce504911
L		 12842020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1285
1286 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1287 CPU_ANY_SSE4A_FLAGS.
1288
dabec65d
AM		 12892020-02-17 Alan Modra <amodra@gmail.com>
1290
1291 * i386-gen.c (cpu_flag_init): Correct last change.
1292
af5c13b0
L		 12932020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1294
1295 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1296 CPU_ANY_SSE4_FLAGS.
1297
6867aac0
L		 12982020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1299
1300 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1301 (movzx): Likewise.
1302
65fca059
JB		 13032020-02-14 Jan Beulich <jbeulich@suse.com>
1304
1305 PR gas/25438
1306 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1307 destination for Cpu64-only variant.
1308 (movzx): Fold patterns.
1309 * i386-tbl.h: Re-generate.
1310
7deea9aa
JB		 13112020-02-13 Jan Beulich <jbeulich@suse.com>
1312
1313 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1314 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1315 CPU_ANY_SSE4_FLAGS entry.
1316 * i386-init.h: Re-generate.
1317
6c0946d0
JB		 13182020-02-12 Jan Beulich <jbeulich@suse.com>
1319
1320 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1321 with Unspecified, making the present one AT&T syntax only.
1322 * i386-tbl.h: Re-generate.
1323
ddb56fe6
JB		 13242020-02-12 Jan Beulich <jbeulich@suse.com>
1325
1326 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1327 * i386-tbl.h: Re-generate.
1328
5990e377
JB		 13292020-02-12 Jan Beulich <jbeulich@suse.com>
1330
1331 PR gas/24546
1332 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1333 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1334 Amd64 and Intel64 templates.
1335 (call, jmp): Likewise for far indirect variants. Dro
1336 Unspecified.
1337 * i386-tbl.h: Re-generate.
1338
50128d0c
JB		 13392020-02-11 Jan Beulich <jbeulich@suse.com>
1340
1341 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1342 * i386-opc.h (ShortForm): Delete.
1343 (struct i386_opcode_modifier): Remove shortform field.
1344 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1345 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1346 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1347 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1348 Drop ShortForm.
1349 * i386-tbl.h: Re-generate.
1350
1e05b5c4
JB		 13512020-02-11 Jan Beulich <jbeulich@suse.com>
1352
1353 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1354 fucompi): Drop ShortForm from operand-less templates.
1355 * i386-tbl.h: Re-generate.
1356
2f5dd314
AM		 13572020-02-11 Alan Modra <amodra@gmail.com>
1358
1359 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1360 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1361 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1362 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1363 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1364
5aae9ae9
MM		 13652020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1366
1367 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1368 (cde_opcodes): Add VCX* instructions.
1369
4934a27c
MM		 13702020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1371 Matthew Malcomson <matthew.malcomson@arm.com>
1372
1373 * arm-dis.c (struct cdeopcode32): New.
1374 (CDE_OPCODE): New macro.
1375 (cde_opcodes): New disassembly table.
1376 (regnames): New option to table.
1377 (cde_coprocs): New global variable.
1378 (print_insn_cde): New
1379 (print_insn_thumb32): Use print_insn_cde.
1380 (parse_arm_disassembler_options): Parse coprocN args.
1381
4b5aaf5f
L		 13822020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1383
1384 PR gas/25516
1385 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1386 with ISA64.
1387 * i386-opc.h (AMD64): Removed.
1388 (Intel64): Likewose.
1389 (AMD64): New.
1390 (INTEL64): Likewise.
1391 (INTEL64ONLY): Likewise.
1392 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1393 * i386-opc.tbl (Amd64): New.
1394 (Intel64): Likewise.
1395 (Intel64Only): Likewise.
1396 Replace AMD64 with Amd64. Update sysenter/sysenter with
1397 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1398 * i386-tbl.h: Regenerated.
1399
9fc0b501
SB		 14002020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1401
1402 PR 25469
1403 * z80-dis.c: Add support for GBZ80 opcodes.
1404
c5d7be0c
AM		 14052020-02-04 Alan Modra <amodra@gmail.com>
1406
1407 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1408
44e4546f
AM		 14092020-02-03 Alan Modra <amodra@gmail.com>
1410
1411 * m32c-ibld.c: Regenerate.
1412
b2b1453a
AM		 14132020-02-01 Alan Modra <amodra@gmail.com>
1414
1415 * frv-ibld.c: Regenerate.
1416
4102be5c
JB		 14172020-01-31 Jan Beulich <jbeulich@suse.com>
1418
1419 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1420 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1421 (OP_E_memory): Replace xmm_mdq_mode case label by
1422 vex_scalar_w_dq_mode one.
1423 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1424
825bd36c
JB		 14252020-01-31 Jan Beulich <jbeulich@suse.com>
1426
1427 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1428 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1429 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1430 (intel_operand_size): Drop vex_w_dq_mode case label.
1431
c3036ed0
RS		 14322020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1433
1434 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1435 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1436
0c115f84
AM		 14372020-01-30 Alan Modra <amodra@gmail.com>
1438
1439 * m32c-ibld.c: Regenerate.
1440
bd434cc4
JM		 14412020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1442
1443 * bpf-opc.c: Regenerate.
1444
aeab2b26
JB		 14452020-01-30 Jan Beulich <jbeulich@suse.com>
1446
1447 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1448 (dis386): Use them to replace C2/C3 table entries.
1449 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1450 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1451 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1452 * i386-tbl.h: Re-generate.
1453
62b3f548
JB		 14542020-01-30 Jan Beulich <jbeulich@suse.com>
1455
1456 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1457 forms.
1458 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1459 DefaultSize.
1460 * i386-tbl.h: Re-generate.
1461
1bd8ae10
AM		 14622020-01-30 Alan Modra <amodra@gmail.com>
1463
1464 * tic4x-dis.c (tic4x_dp): Make unsigned.
1465
bc31405e
L		 14662020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1467 Jan Beulich <jbeulich@suse.com>
1468
1469 PR binutils/25445
1470 * i386-dis.c (MOVSXD_Fixup): New function.
1471 (movsxd_mode): New enum.
1472 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1473 (intel_operand_size): Handle movsxd_mode.
1474 (OP_E_register): Likewise.
1475 (OP_G): Likewise.
1476 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1477 register on movsxd. Add movsxd with 16-bit destination register
1478 for AMD64 and Intel64 ISAs.
1479 * i386-tbl.h: Regenerated.
1480
7568c93b
TC		 14812020-01-27 Tamar Christina <tamar.christina@arm.com>
1482
1483 PR 25403
1484 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1485 * aarch64-asm-2.c: Regenerate
1486 * aarch64-dis-2.c: Likewise.
1487 * aarch64-opc-2.c: Likewise.
1488
c006a730
JB		 14892020-01-21 Jan Beulich <jbeulich@suse.com>
1490
1491 * i386-opc.tbl (sysret): Drop DefaultSize.
1492 * i386-tbl.h: Re-generate.
1493
c906a69a
JB		 14942020-01-21 Jan Beulich <jbeulich@suse.com>
1495
1496 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1497 Dword.
1498 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1499 * i386-tbl.h: Re-generate.
1500
26916852
NC		 15012020-01-20 Nick Clifton <nickc@redhat.com>
1502
1503 * po/de.po: Updated German translation.
1504 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1505 * po/uk.po: Updated Ukranian translation.
1506
4d6cbb64
AM		 15072020-01-20 Alan Modra <amodra@gmail.com>
1508
1509 * hppa-dis.c (fput_const): Remove useless cast.
1510
2bddb71a
AM		 15112020-01-20 Alan Modra <amodra@gmail.com>
1512
1513 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1514
1b1bb2c6
NC		 15152020-01-18 Nick Clifton <nickc@redhat.com>
1516
1517 * configure: Regenerate.
1518 * po/opcodes.pot: Regenerate.
1519
ae774686
NC		 15202020-01-18 Nick Clifton <nickc@redhat.com>
1521
1522 Binutils 2.34 branch created.
1523
07f1f3aa
CB		 15242020-01-17 Christian Biesinger <cbiesinger@google.com>
1525
1526 * opintl.h: Fix spelling error (seperate).
1527
42e04b36
L		 15282020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1529
1530 * i386-opc.tbl: Add {vex} pseudo prefix.
1531 * i386-tbl.h: Regenerated.
1532
2da2eaf4
AV		 15332020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1534
1535 PR 25376
1536 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1537 (neon_opcodes): Likewise.
1538 (select_arm_features): Make sure we enable MVE bits when selecting
1539 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1540 any architecture.
1541
d0849eed
JB		 15422020-01-16 Jan Beulich <jbeulich@suse.com>
1543
1544 * i386-opc.tbl: Drop stale comment from XOP section.
1545
9cf70a44
JB		 15462020-01-16 Jan Beulich <jbeulich@suse.com>
1547
1548 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1549 (extractps): Add VexWIG to SSE2AVX forms.
1550 * i386-tbl.h: Re-generate.
1551
4814632e
JB		 15522020-01-16 Jan Beulich <jbeulich@suse.com>
1553
1554 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1555 Size64 from and use VexW1 on SSE2AVX forms.
1556 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1557 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1558 * i386-tbl.h: Re-generate.
1559
aad09917
AM		 15602020-01-15 Alan Modra <amodra@gmail.com>
1561
1562 * tic4x-dis.c (tic4x_version): Make unsigned long.
1563 (optab, optab_special, registernames): New file scope vars.
1564 (tic4x_print_register): Set up registernames rather than
1565 malloc'd registertable.
1566 (tic4x_disassemble): Delete optable and optable_special. Use
1567 optab and optab_special instead. Throw away old optab,
1568 optab_special and registernames when info->mach changes.
1569
7a6bf3be
SB		 15702020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1571
1572 PR 25377
1573 * z80-dis.c (suffix): Use .db instruction to generate double
1574 prefix.
1575
ca1eaac0
AM		 15762020-01-14 Alan Modra <amodra@gmail.com>
1577
1578 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1579 values to unsigned before shifting.
1580
1d67fe3b
TT		 15812020-01-13 Thomas Troeger <tstroege@gmx.de>
1582
1583 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1584 flow instructions.
1585 (print_insn_thumb16, print_insn_thumb32): Likewise.
1586 (print_insn): Initialize the insn info.
1587 * i386-dis.c (print_insn): Initialize the insn info fields, and
1588 detect jumps.
1589
5e4f7e05
CZ		 15902012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1591
1592 * arc-opc.c (C_NE): Make it required.
1593
b9fe6b8a
CZ		 15942012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1595
1596 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1597 reserved register name.
1598
90dee485
AM		 15992020-01-13 Alan Modra <amodra@gmail.com>
1600
1601 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1602 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1603
febda64f
AM		 16042020-01-13 Alan Modra <amodra@gmail.com>
1605
1606 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1607 result of wasm_read_leb128 in a uint64_t and check that bits
1608 are not lost when copying to other locals. Use uint32_t for
1609 most locals. Use PRId64 when printing int64_t.
1610
df08b588
AM		 16112020-01-13 Alan Modra <amodra@gmail.com>
1612
1613 * score-dis.c: Formatting.
1614 * score7-dis.c: Formatting.
1615
b2c759ce
AM		 16162020-01-13 Alan Modra <amodra@gmail.com>
1617
1618 * score-dis.c (print_insn_score48): Use unsigned variables for
1619 unsigned values. Don't left shift negative values.
1620 (print_insn_score32): Likewise.
1621 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1622
5496abe1
AM		 16232020-01-13 Alan Modra <amodra@gmail.com>
1624
1625 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1626
202e762b
AM		 16272020-01-13 Alan Modra <amodra@gmail.com>
1628
1629 * fr30-ibld.c: Regenerate.
1630
7ef412cf
AM		 16312020-01-13 Alan Modra <amodra@gmail.com>
1632
1633 * xgate-dis.c (print_insn): Don't left shift signed value.
1634 (ripBits): Formatting, use 1u.
1635
7f578b95
AM		 16362020-01-10 Alan Modra <amodra@gmail.com>
1637
1638 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1639 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1640
441af85b
AM		 16412020-01-10 Alan Modra <amodra@gmail.com>
1642
1643 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1644 and XRREG value earlier to avoid a shift with negative exponent.
1645 * m10200-dis.c (disassemble): Similarly.
1646
bce58db4
NC		 16472020-01-09 Nick Clifton <nickc@redhat.com>
1648
1649 PR 25224
1650 * z80-dis.c (ld_ii_ii): Use correct cast.
1651
40c75bc8
SB		 16522020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1653
1654 PR 25224
1655 * z80-dis.c (ld_ii_ii): Use character constant when checking
1656 opcode byte value.
1657
d835a58b
JB		 16582020-01-09 Jan Beulich <jbeulich@suse.com>
1659
1660 * i386-dis.c (SEP_Fixup): New.
1661 (SEP): Define.
1662 (dis386_twobyte): Use it for sysenter/sysexit.
1663 (enum x86_64_isa): Change amd64 enumerator to value 1.
1664 (OP_J): Compare isa64 against intel64 instead of amd64.
1665 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1666 forms.
1667 * i386-tbl.h: Re-generate.
1668
030a2e78
AM		 16692020-01-08 Alan Modra <amodra@gmail.com>
1670
1671 * z8k-dis.c: Include libiberty.h
1672 (instr_data_s): Make max_fetched unsigned.
1673 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1674 Don't exceed byte_info bounds.
1675 (output_instr): Make num_bytes unsigned.
1676 (unpack_instr): Likewise for nibl_count and loop.
1677 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1678 idx unsigned.
1679 * z8k-opc.h: Regenerate.
1680
bb82aefe
SV		 16812020-01-07 Shahab Vahedi <shahab@synopsys.com>
1682
1683 * arc-tbl.h (llock): Use 'LLOCK' as class.
1684 (llockd): Likewise.
1685 (scond): Use 'SCOND' as class.
1686 (scondd): Likewise.
1687 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1688 (scondd): Likewise.
1689
cc6aa1a6
AM		 16902020-01-06 Alan Modra <amodra@gmail.com>
1691
1692 * m32c-ibld.c: Regenerate.
1693
660e62b1
AM		 16942020-01-06 Alan Modra <amodra@gmail.com>
1695
1696 PR 25344
1697 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1698 Peek at next byte to prevent recursion on repeated prefix bytes.
1699 Ensure uninitialised "mybuf" is not accessed.
1700 (print_insn_z80): Don't zero n_fetch and n_used here,..
1701 (print_insn_z80_buf): ..do it here instead.
1702
c9ae58fe
AM		 17032020-01-04 Alan Modra <amodra@gmail.com>
1704
1705 * m32r-ibld.c: Regenerate.
1706
5f57d4ec
AM		 17072020-01-04 Alan Modra <amodra@gmail.com>
1708
1709 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1710
2c5c1196
AM		 17112020-01-04 Alan Modra <amodra@gmail.com>
1712
1713 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1714
2e98c6c5
AM		 17152020-01-04 Alan Modra <amodra@gmail.com>
1716
1717 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1718
567dfba2
JB		 17192020-01-03 Jan Beulich <jbeulich@suse.com>
1720
5437a02a
JB		 1721 * aarch64-tbl.h (aarch64_opcode_table): Use
1722 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1723
17242020-01-03 Jan Beulich <jbeulich@suse.com>
1725
1726 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1727 forms of SUDOT and USDOT.
1728
8c45011a
JB		 17292020-01-03 Jan Beulich <jbeulich@suse.com>
1730
5437a02a 1731 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1732 uzip{1,2}.
1733 * opcodes/aarch64-dis-2.c: Re-generate.
1734
f4950f76
JB		 17352020-01-03 Jan Beulich <jbeulich@suse.com>
1736
5437a02a 1737 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1738 FMMLA encoding.
1739 * opcodes/aarch64-dis-2.c: Re-generate.
1740
6655dba2
SB		 17412020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1742
1743 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1744
b14ce8bf
AM		 17452020-01-01 Alan Modra <amodra@gmail.com>
1746
1747 Update year range in copyright notice of all files.
1748
0b114740 1749For older changes see ChangeLog-2019
3499769a 1750\f
0b114740 1751Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1752
1753Copying and distribution of this file, with or without modification,
1754are permitted in any medium without royalty provided the copyright
1755notice and this notice are preserved.
1756
1757Local Variables:
1758mode: change-log
1759left-margin: 8
1760fill-column: 74
1761version-control: never
1762End:
GDB Binutils - Deliverables
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