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x86: drop stray CheckRegSize uses
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
93b71a26
JB		 12017-12-15 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov,
4 movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror,
5 sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto,
6 stos, sub, test, xor): Drop CheckRegSize from variants not
7 allowing for two (or more) register operands.
8 * i386-tbl.h: Re-generate.
9
25982ee0
JW		 102017-12-13 Jim Wilson <jimw@sifive.com>
11
12 PR 22599
13 * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
14
024d185c
DD		 152017-12-13 Dimitar Dimitrov <dimitar@dinux.eu>
16
17 * disassemble.c: Enable disassembler_needs_relocs for PRU.
18
4c5ae11b
RL		 192017-12-11 Petr Pavlu <petr.pavlu@arm.com>
20 Renlin Li <renlin.li@arm.com>
21
22 * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
23 (get_sym_code_type): Here.
24
f143cb5f
AM		 252017-12-03 Alan Modra <amodra@gmail.com>
26
27 * ppc-opc.c (extract_li20): Rewrite.
28
0f873fd5
PB		 292017-12-01 Peter Bergner <bergner@vnet.ibm.com>
30
31 * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
32 (operand_value_powerpc): Update return and argument type.
33 <value, top>: Update type.
34 (skip_optional_operands): Update argument type.
35 (lookup_powerpc): Likewise.
36 (lookup_vle): Likewise.
37 <table_opcd, table_mask, insn2>: Update type.
38 (lookup_spe2): Update argument type.
39 <table_opcd, table_mask, insn2>: Update type.
40 (print_insn_powerpc) <insn, value>: Update type.
41 Use PPC_INT_FMT for printing instructions and operands.
42 * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
43 insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
44 insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
45 extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
46 extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
47 insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
48 extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
49 insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
50 extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
51 insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
52 extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
53 insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
54 extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
55 insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
56 extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
57 insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
58 extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
59 insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
60 extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
61 extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
62 extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
63 insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
64 extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
65 insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
66 extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
67 extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
68 (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
69 BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
70 DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
71 SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
72 VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
73 VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
74 VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
75 XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
76 XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
77 XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
78 XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
79
7ac20022
JB		 802017-11-29 Jan Beulich <jbeulich@suse.com>
81
82 * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
83 New.
84 (output_cpu_flags): Update active_cpu_flags.
85 (process_i386_opcode_modifier): Update active_isstring.
86 (output_operand_type): Rename "macro" parameter to "stage",
87 changing its type.
88 (process_i386_operand_type): Likewise. Track presence of
89 BaseIndex and emit DispN accordingly.
90 (output_i386_opcode, process_i386_registers,
91 process_i386_initializers): Adjust calls to
92 process_i386_operand_type() for its changed parameter type.
93 * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
94 all insns operands having BaseIndex set.
95 * i386-tbl.h: Re-generate.
96
b5014f7a
JB		 972017-11-29 Jan Beulich <jbeulich@suse.com>
98
99 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
100 entry.
101 (operand_types): Remove Vec_Disp8 entry.
102 * i386-opc.h (Vec_Disp8): Delete.
103 (union i386_operand_type): Remove vec_disp8.
104 (i386-opc.tbl): Remove Vec_Disp8.
105 * i386-init.h, i386-tbl.h: Re-generate.
106
ca39c2f4
SS		 1072017-11-29 Stefan Stroe <stroestefan@gmail.com>
108
109 * po/Make-in (datadir): Define as @datadir@.
110 (localedir): Define as @localedir@.
111 (gnulocaledir, gettextsrcdir): Use @datarootdir@.
112
64973b0a
NC		 1132017-11-27 Nick Clifton <nickc@redhat.com>
114
115 * po/zh_CN.po: Updated simplified Chinese translation.
116
ac465521
JB		 1172017-11-24 Jan Beulich <jbeulich@suse.com>
118
119 * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
120 "df" groups.
121
be7d1531
IT		 1222017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
123
124 * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
125 * i386-tbl.h: Regenerate.
126
65f3ed04
JB		 1272017-11-23 Jan Beulich <jbeulich@suse.com>
128
129 * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
130 the 16-bit addressing case.
131
66f1eba0
JB		 1322017-11-23 Jan Beulich <jbeulich@suse.com>
133
134 * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
135 (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
136 * i386-opc.tbl (ud1, ud2b): Add operands.
137 (ud0): New.
138 * i386-tbl.h: Re-generate.
139
94b98370
IT		 1402017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
141
142 * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
143 * i386-tbl.h: Regenerate.
144
6f19e86d
IT		 1452017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
146
147 * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
148 * i386-tbl.h: Regenerate.
149
dc958481 1502017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
151
152 *arc-opc (insert_rhv2): Check h-regs range.
153
50d2740d 1542017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
155
156 * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
157 * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
158
d0f7791c
TC		 1592017-11-16 Tamar Christina <tamar.christina@arm.com>
160
161 * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
162 and AARCH64_FEATURE_F16.
163
e9dbdd80
TC		 1642017-11-16 Tamar Christina <tamar.christina@arm.com>
165
166 * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
167 (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
168 (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
169 (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
170 (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
171 (ldapur, ldapursw, stlur): New.
172 * aarch64-dis-2.c: Regenerate.
173
5f847646
JB		 1742017-11-16 Jan Beulich <jbeulich@suse.com>
175
176 (get_valid_dis386): Never flag bad opcode when
177 vex.register_specifier is beyond 7. Always store all four
178 bits of it. Move 16-/32-bit override in EVEX handling after
179 all to be overridden bits have been set.
180 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
181 Use rex to determine GPR register set.
182 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
183 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
184
390a6789
JB		 1852017-11-15 Jan Beulich <jbeulich@suse.com>
186
187 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
188 determine GPR register set.
189
3a2430e0
JB		 1902017-11-15 Jan Beulich <jbeulich@suse.com>
191
192 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
193 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
194 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
195 pass.
196 (OP_REG_VexI4): Drop low 4 bits check.
197
0645f0a2
JB		 1982017-11-15 Jan Beulich <jbeulich@suse.com>
199
200 * i386-reg.tbl (axl): Remove Acc and Byte.
201 * i386-tbl.h: Re-generate.
202
be92cb14
JB		 2032017-11-14 Jan Beulich <jbeulich@suse.com>
204
205 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
206 (vex_len_table): Use VPCOM.
207
2645e1d0
JB		 2082017-11-14 Jan Beulich <jbeulich@suse.com>
209
210 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
211 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
212 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
213 vpcmpw): Move up.
214 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
215 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
216 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
217 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
218 vpcmpnltuw): New.
219 * i386-tbl.h: Re-generate.
220
df145ef6
JB		 2212017-11-14 Jan Beulich <jbeulich@suse.com>
222
223 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
224 smov, ssca, stos, ssto, xlat): Drop Disp*.
225 * i386-tbl.h: Re-generate.
226
897e603c
JB		 2272017-11-13 Jan Beulich <jbeulich@suse.com>
228
229 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
230 xsaveopt64): Add No_qSuf.
231 * i386-tbl.h: Re-generate.
232
793a1948
TC		 2332017-11-09 Tamar Christina <tamar.christina@arm.com>
234
235 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
236 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
237 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
238 sder32_el2, vncr_el2.
239 (aarch64_sys_reg_supported_p): Likewise.
240 (aarch64_pstatefields): Add dit register.
241 (aarch64_pstatefield_supported_p): Likewise.
242 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
243 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
244 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
245 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
246 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
247 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
248 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
249
1a7ed57c
TC		 2502017-11-09 Tamar Christina <tamar.christina@arm.com>
251
252 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
253 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
254 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
255 (QL_STLW, QL_STLX): New.
256
f42f1a1d
TC		 2572017-11-09 Tamar Christina <tamar.christina@arm.com>
258
259 * aarch64-asm.h (ins_addr_offset): New.
260 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
261 (aarch64_ins_addr_offset): New.
262 * aarch64-asm-2.c: Regenerate.
263 * aarch64-dis.h (ext_addr_offset): New.
264 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
265 (aarch64_ext_addr_offset): New.
266 * aarch64-dis-2.c: Regenerate.
267 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
268 FLD_imm4_2 and FLD_SM3_imm2.
269 * aarch64-opc.c (fields): Add FLD_imm6_2,
270 FLD_imm4_2 and FLD_SM3_imm2.
271 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
272 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
273 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
274 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
275 * aarch64-tbl.h
276 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
277
b6b9ca0c
TC		 2782017-11-09 Tamar Christina <tamar.christina@arm.com>
279
280 * aarch64-tbl.h
281 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
282 (aarch64_feature_sm4, aarch64_feature_sha3): New.
283 (aarch64_feature_fp_16_v8_2): New.
284 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
285 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
286 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
287
c0e7cef7
NC		 2882017-11-08 Tamar Christina <tamar.christina@arm.com>
289
290 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
291 (aarch64_feature_sha2, aarch64_feature_aes): New.
292 (SHA2, AES): New.
293 (AES_INSN, SHA2_INSN): New.
294 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
295 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
296 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
297 Change to SHA2_INS.
298
dec41383
JW		 2992017-11-08 Jiong Wang <jiong.wang@arm.com>
300 Tamar Christina <tamar.christina@arm.com>
301
302 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
303 FP16 instructions, including vfmal.f16 and vfmsl.f16.
304
52eab766
AB		 3052017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
306
307 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
308
6003e27e
AM		 3092017-11-07 Alan Modra <amodra@gmail.com>
310
311 * opintl.h: Formatting, comment fixes.
312 (gettext, ngettext): Redefine when ENABLE_NLS.
313 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
314 (_): Define using gettext.
315 (textdomain, bindtextdomain): Use safer "do nothing".
316
fdddd290 3172017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
318
319 * arc-dis.c (print_hex): New variable.
320 (parse_option): Check for hex option.
321 (print_insn_arc): Use hexadecimal representation for short
322 immediate values when requested.
323 (print_arc_disassembler_options): Add hex option to the list.
324
3334eba7 3252017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
326
327 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
328 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
329 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
330 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
331 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
332 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
333 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
334 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
335 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
336 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
337 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
338 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
339 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
340 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
341 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
342 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
343 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
344 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
345 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
346 Changed opcodes.
347 (prealloc, prefetch*): Place them before ld instruction.
348 * arc-opc.c (skip_this_opcode): Add ARITH class.
349
e5d70d6b
AM		 3502017-10-25 Alan Modra <amodra@gmail.com>
351
352 PR 22348
353 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
354 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
355 (imm4flag, size_changed): Likewise.
356 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
357 (words, allWords, processing_argument_number): Likewise.
358 (cst4flag, size_changed): Likewise.
359 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
360 (crx_cst4_maps): Rename from cst4_maps.
361 (crx_no_op_insn): Rename from no_op_insn.
362
63a25ea0
AW		 3632017-10-24 Andrew Waterman <andrew@sifive.com>
364
365 * riscv-opc.c (match_c_addi16sp) : New function.
366 (match_c_addi4spn): New function.
367 (match_c_lui): Don't allow 0-immediate encodings.
368 (riscv_opcodes) <addi>: Use the above functions.
369 <add>: Likewise.
370 <c.addi4spn>: Likewise.
371 <c.addi16sp>: Likewise.
372
fe4e2a3c
IT		 3732017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
374
375 * i386-init.h: Regenerate
376 * i386-tbl.h: Likewise
377
2739ef6d
IT		 3782017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
379
380 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
381 (enum): Add EVEX_W_0F3854_P_2.
382 * i386-dis-evex.h (evex_table): Updated.
383 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
384 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
385 (cpu_flags): Add CpuAVX512_BITALG.
386 * i386-opc.h (enum): Add CpuAVX512_BITALG.
387 (i386_cpu_flags): Add cpuavx512_bitalg..
388 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
389 * i386-init.h: Regenerate.
390 * i386-tbl.h: Likewise.
391
3922017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
393
394 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
395 * i386-dis-evex.h (evex_table): Updated.
396 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
397 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
398 (cpu_flags): Add CpuAVX512_VNNI.
399 * i386-opc.h (enum): Add CpuAVX512_VNNI.
400 (i386_cpu_flags): Add cpuavx512_vnni.
401 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
402 * i386-init.h: Regenerate.
403 * i386-tbl.h: Likewise.
404
4052017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
406
407 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
408 (enum): Remove VEX_LEN_0F3A44_P_2.
409 (vex_len_table): Ditto.
410 (enum): Remove VEX_W_0F3A44_P_2.
411 (vew_w_table): Ditto.
412 (prefix_table): Adjust instructions (see prefixes above).
413 * i386-dis-evex.h (evex_table):
414 Add new instructions (see prefixes above).
415 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
416 (bitfield_cpu_flags): Ditto.
417 * i386-opc.h (enum): Ditto.
418 (i386_cpu_flags): Ditto.
419 (CpuUnused): Comment out to avoid zero-width field problem.
420 * i386-opc.tbl (vpclmulqdq): New instruction.
421 * i386-init.h: Regenerate.
422 * i386-tbl.h: Ditto.
423
4242017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
425
426 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
427 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
428 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
429 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
430 (vex_len_table): Ditto.
431 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
432 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
433 (vew_w_table): Ditto.
434 (prefix_table): Adjust instructions (see prefixes above).
435 * i386-dis-evex.h (evex_table):
436 Add new instructions (see prefixes above).
437 * i386-gen.c (cpu_flag_init): Add VAES.
438 (bitfield_cpu_flags): Ditto.
439 * i386-opc.h (enum): Ditto.
440 (i386_cpu_flags): Ditto.
441 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
442 * i386-init.h: Regenerate.
443 * i386-tbl.h: Ditto.
444
4452017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
446
447 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
448 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
449 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
450 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
451 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
452 (prefix_table): Updated (see prefixes above).
453 (three_byte_table): Likewise.
454 (vex_w_table): Likewise.
455 * i386-dis-evex.h: Likewise.
456 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
457 (cpu_flags): Add CpuGFNI.
458 * i386-opc.h (enum): Add CpuGFNI.
459 (i386_cpu_flags): Add cpugfni.
460 * i386-opc.tbl: Add Intel GFNI instructions.
461 * i386-init.h: Regenerate.
462 * i386-tbl.h: Likewise.
463
4642017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
465
466 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
467 Define EXbScalar and EXwScalar for OP_EX.
468 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
469 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
470 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
471 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
472 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
473 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
474 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
475 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
476 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
477 (OP_E_memory): Likewise.
478 * i386-dis-evex.h: Updated.
479 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
480 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
481 (cpu_flags): Add CpuAVX512_VBMI2.
482 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
483 (i386_cpu_flags): Add cpuavx512_vbmi2.
484 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
485 * i386-init.h: Regenerate.
486 * i386-tbl.h: Likewise.
487
2a6969e1
EB		 4882017-10-18 Eric Botcazou <ebotcazou@adacore.com>
489
490 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
491
3b4b0a62
JB		 4922017-10-12 James Bowman <james.bowman@ftdichip.com>
493
494 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
495 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
496 K15. Add jmpix pattern.
497
8e464506
AK		 4982017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
499
500 * s390-opc.txt (prno, tpei, irbm): New instructions added.
501
ee6767da
AK		 5022017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
503
504 * s390-opc.c (INSTR_SI_RD): New macro.
505 (INSTR_S_RD): Adjust example instruction.
506 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
507 SI_RD.
508
d2e6c9a3
AF		 5092017-10-01 Alexander Fedotov <alfedotov@gmail.com>
510
511 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
512 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
513 VLE multimple load/store instructions. Old e_ldm* variants are
514 kept as aliases.
515 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
516
8e43602e
NC		 5172017-09-27 Nick Clifton <nickc@redhat.com>
518
519 PR 22179
520 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
521 names for the fmv.x.s and fmv.s.x instructions respectively.
522
58a0b827
NC		 5232017-09-26 do <do@nerilex.org>
524
525 PR 22123
526 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
527 be used on CPUs that have emacs support.
528
57a024f4
SDJ		 5292017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
530
531 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
532
4ec521f2
KLC		 5332017-09-09 Kamil Rytarowski <n54@gmx.com>
534
535 * nds32-asm.c: Rename __BIT() to N32_BIT().
536 * nds32-asm.h: Likewise.
537 * nds32-dis.c: Likewise.
538
4e9ac44a
L		 5392017-09-09 H.J. Lu <hongjiu.lu@intel.com>
540
541 * i386-dis.c (last_active_prefix): Removed.
542 (ckprefix): Don't set last_active_prefix.
543 (NOTRACK_Fixup): Don't check last_active_prefix.
544
b55f3386
NC		 5452017-08-31 Nick Clifton <nickc@redhat.com>
546
547 * po/fr.po: Updated French translation.
548
59e8523b
JB		 5492017-08-31 James Bowman <james.bowman@ftdichip.com>
550
551 * ft32-dis.c (print_insn_ft32): Correct display of non-address
552 fields.
553
74081948
AF		 5542017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
555 Edmar Wienskoski <edmar.wienskoski@nxp.com>
556
557 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
558 PPC_OPCODE_EFS2 flag to "e200z4" entry.
559 New entries efs2 and spe2.
560 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
561 (SPE2_OPCD_SEGS): New macro.
562 (spe2_opcd_indices): New.
563 (disassemble_init_powerpc): Handle SPE2 opcodes.
564 (lookup_spe2): New function.
565 (print_insn_powerpc): call lookup_spe2.
566 * ppc-opc.c (insert_evuimm1_ex0): New function.
567 (extract_evuimm1_ex0): Likewise.
568 (insert_evuimm_lt8): Likewise.
569 (extract_evuimm_lt8): Likewise.
570 (insert_off_spe2): Likewise.
571 (extract_off_spe2): Likewise.
572 (insert_Ddd): Likewise.
573 (extract_Ddd): Likewise.
574 (DD): New operand.
575 (EVUIMM_LT8): Likewise.
576 (EVUIMM_LT16): Adjust.
577 (MMMM): New operand.
578 (EVUIMM_1): Likewise.
579 (EVUIMM_1_EX0): Likewise.
580 (EVUIMM_2): Adjust.
581 (NNN): New operand.
582 (VX_OFF_SPE2): Likewise.
583 (BBB): Likewise.
584 (DDD): Likewise.
585 (VX_MASK_DDD): New mask.
586 (HH): New operand.
587 (VX_RA_CONST): New macro.
588 (VX_RA_CONST_MASK): Likewise.
589 (VX_RB_CONST): Likewise.
590 (VX_RB_CONST_MASK): Likewise.
591 (VX_OFF_SPE2_MASK): Likewise.
592 (VX_SPE_CRFD): Likewise.
593 (VX_SPE_CRFD_MASK VX): Likewise.
594 (VX_SPE2_CLR): Likewise.
595 (VX_SPE2_CLR_MASK): Likewise.
596 (VX_SPE2_SPLATB): Likewise.
597 (VX_SPE2_SPLATB_MASK): Likewise.
598 (VX_SPE2_OCTET): Likewise.
599 (VX_SPE2_OCTET_MASK): Likewise.
600 (VX_SPE2_DDHH): Likewise.
601 (VX_SPE2_DDHH_MASK): Likewise.
602 (VX_SPE2_HH): Likewise.
603 (VX_SPE2_HH_MASK): Likewise.
604 (VX_SPE2_EVMAR): Likewise.
605 (VX_SPE2_EVMAR_MASK): Likewise.
606 (PPCSPE2): Likewise.
607 (PPCEFS2): Likewise.
608 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
609 (powerpc_macros): Map old SPE instructions have new names
610 with the same opcodes. Add SPE2 instructions which just are
611 mapped to SPE2.
612 (spe2_opcodes): Add SPE2 opcodes.
613
b80c7270
AM		 6142017-08-23 Alan Modra <amodra@gmail.com>
615
616 * ppc-opc.c: Formatting and comment fixes. Move insert and
617 extract functions earlier, deleting forward declarations.
618 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
619 RA_MASK.
620
67d888f5
PD		 6212017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
622
623 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
624
e3c2f928
AF		 6252017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
626 Edmar Wienskoski <edmar.wienskoski@nxp.com>
627
628 * ppc-opc.c (insert_evuimm2_ex0): New function.
629 (extract_evuimm2_ex0): Likewise.
630 (insert_evuimm4_ex0): Likewise.
631 (extract_evuimm4_ex0): Likewise.
632 (insert_evuimm8_ex0): Likewise.
633 (extract_evuimm8_ex0): Likewise.
634 (insert_evuimm_lt16): Likewise.
635 (extract_evuimm_lt16): Likewise.
636 (insert_rD_rS_even): Likewise.
637 (extract_rD_rS_even): Likewise.
638 (insert_off_lsp): Likewise.
639 (extract_off_lsp): Likewise.
640 (RD_EVEN): New operand.
641 (RS_EVEN): Likewise.
642 (RSQ): Adjust.
643 (EVUIMM_LT16): New operand.
644 (HTM_SI): Adjust.
645 (EVUIMM_2_EX0): New operand.
646 (EVUIMM_4): Adjust.
647 (EVUIMM_4_EX0): New operand.
648 (EVUIMM_8): Adjust.
649 (EVUIMM_8_EX0): New operand.
650 (WS): Adjust.
651 (VX_OFF): New operand.
652 (VX_LSP): New macro.
653 (VX_LSP_MASK): Likewise.
654 (VX_LSP_OFF_MASK): Likewise.
655 (PPC_OPCODE_LSP): Likewise.
656 (vle_opcodes): Add LSP opcodes.
657 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
658
cc4a945a
JW		 6592017-08-09 Jiong Wang <jiong.wang@arm.com>
660
661 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
662 register operands in CRC instructions.
663 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
664 comments.
665
b28b8b5e
L		 6662017-08-07 H.J. Lu <hongjiu.lu@intel.com>
667
668 * disassemble.c (disassembler): Mark big and mach with
669 ATTRIBUTE_UNUSED.
670
e347efc3
MR		 6712017-08-07 Maciej W. Rozycki <macro@imgtec.com>
672
673 * disassemble.c (disassembler): Remove arch/mach/endian
674 assertions.
675
7cbc739c
NC		 6762017-07-25 Nick Clifton <nickc@redhat.com>
677
678 PR 21739
679 * arc-opc.c (insert_rhv2): Use lower case first letter in error
680 message.
681 (insert_r0): Likewise.
682 (insert_r1): Likewise.
683 (insert_r2): Likewise.
684 (insert_r3): Likewise.
685 (insert_sp): Likewise.
686 (insert_gp): Likewise.
687 (insert_pcl): Likewise.
688 (insert_blink): Likewise.
689 (insert_ilink1): Likewise.
690 (insert_ilink2): Likewise.
691 (insert_ras): Likewise.
692 (insert_rbs): Likewise.
693 (insert_rcs): Likewise.
694 (insert_simm3s): Likewise.
695 (insert_rrange): Likewise.
696 (insert_r13el): Likewise.
697 (insert_fpel): Likewise.
698 (insert_blinkel): Likewise.
699 (insert_pclel): Likewise.
700 (insert_nps_bitop_size_2b): Likewise.
701 (insert_nps_imm_offset): Likewise.
702 (insert_nps_imm_entry): Likewise.
703 (insert_nps_size_16bit): Likewise.
704 (insert_nps_##NAME##_pos): Likewise.
705 (insert_nps_##NAME): Likewise.
706 (insert_nps_bitop_ins_ext): Likewise.
707 (insert_nps_##NAME): Likewise.
708 (insert_nps_min_hofs): Likewise.
709 (insert_nps_##NAME): Likewise.
710 (insert_nps_rbdouble_64): Likewise.
711 (insert_nps_misc_imm_offset): Likewise.
712 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
713 option description.
714
7684e580
JW		 7152017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
716 Jiong Wang <jiong.wang@arm.com>
717
718 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
719 correct the print.
720 * aarch64-dis-2.c: Regenerated.
721
47826cdb
AK		 7222017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
723
724 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
725 table.
726
2d2dbad0
NC		 7272017-07-20 Nick Clifton <nickc@redhat.com>
728
729 * po/de.po: Updated German translation.
730
70b448ba 7312017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
732
733 * arc-regs.h (sec_stat): New aux register.
734 (aux_kernel_sp): Likewise.
735 (aux_sec_u_sp): Likewise.
736 (aux_sec_k_sp): Likewise.
737 (sec_vecbase_build): Likewise.
738 (nsc_table_top): Likewise.
739 (nsc_table_base): Likewise.
740 (ersec_stat): Likewise.
741 (aux_sec_except): Likewise.
742
7179e0e6
CZ		 7432017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
744
745 * arc-opc.c (extract_uimm12_20): New function.
746 (UIMM12_20): New operand.
747 (SIMM3_5_S): Adjust.
748 * arc-tbl.h (sjli): Add new instruction.
749
684d5a10
JEM		 7502017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
751 John Eric Martin <John.Martin@emmicro-us.com>
752
753 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
754 (UIMM3_23): Adjust accordingly.
755 * arc-regs.h: Add/correct jli_base register.
756 * arc-tbl.h (jli_s): Likewise.
757
de194d85
YC		 7582017-07-18 Nick Clifton <nickc@redhat.com>
759
760 PR 21775
761 * aarch64-opc.c: Fix spelling typos.
762 * i386-dis.c: Likewise.
763
0f6329bd
RB		 7642017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
765
766 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
767 max_addr_offset and octets variables to size_t.
768
429d795d
AM		 7692017-07-12 Alan Modra <amodra@gmail.com>
770
771 * po/da.po: Update from translationproject.org/latest/opcodes/.
772 * po/de.po: Likewise.
773 * po/es.po: Likewise.
774 * po/fi.po: Likewise.
775 * po/fr.po: Likewise.
776 * po/id.po: Likewise.
777 * po/it.po: Likewise.
778 * po/nl.po: Likewise.
779 * po/pt_BR.po: Likewise.
780 * po/ro.po: Likewise.
781 * po/sv.po: Likewise.
782 * po/tr.po: Likewise.
783 * po/uk.po: Likewise.
784 * po/vi.po: Likewise.
785 * po/zh_CN.po: Likewise.
786
4162bb66
AM		 7872017-07-11 Yao Qi <yao.qi@linaro.org>
788 Alan Modra <amodra@gmail.com>
789
790 * cgen.sh: Mark generated files read-only.
791 * epiphany-asm.c: Regenerate.
792 * epiphany-desc.c: Regenerate.
793 * epiphany-desc.h: Regenerate.
794 * epiphany-dis.c: Regenerate.
795 * epiphany-ibld.c: Regenerate.
796 * epiphany-opc.c: Regenerate.
797 * epiphany-opc.h: Regenerate.
798 * fr30-asm.c: Regenerate.
799 * fr30-desc.c: Regenerate.
800 * fr30-desc.h: Regenerate.
801 * fr30-dis.c: Regenerate.
802 * fr30-ibld.c: Regenerate.
803 * fr30-opc.c: Regenerate.
804 * fr30-opc.h: Regenerate.
805 * frv-asm.c: Regenerate.
806 * frv-desc.c: Regenerate.
807 * frv-desc.h: Regenerate.
808 * frv-dis.c: Regenerate.
809 * frv-ibld.c: Regenerate.
810 * frv-opc.c: Regenerate.
811 * frv-opc.h: Regenerate.
812 * ip2k-asm.c: Regenerate.
813 * ip2k-desc.c: Regenerate.
814 * ip2k-desc.h: Regenerate.
815 * ip2k-dis.c: Regenerate.
816 * ip2k-ibld.c: Regenerate.
817 * ip2k-opc.c: Regenerate.
818 * ip2k-opc.h: Regenerate.
819 * iq2000-asm.c: Regenerate.
820 * iq2000-desc.c: Regenerate.
821 * iq2000-desc.h: Regenerate.
822 * iq2000-dis.c: Regenerate.
823 * iq2000-ibld.c: Regenerate.
824 * iq2000-opc.c: Regenerate.
825 * iq2000-opc.h: Regenerate.
826 * lm32-asm.c: Regenerate.
827 * lm32-desc.c: Regenerate.
828 * lm32-desc.h: Regenerate.
829 * lm32-dis.c: Regenerate.
830 * lm32-ibld.c: Regenerate.
831 * lm32-opc.c: Regenerate.
832 * lm32-opc.h: Regenerate.
833 * lm32-opinst.c: Regenerate.
834 * m32c-asm.c: Regenerate.
835 * m32c-desc.c: Regenerate.
836 * m32c-desc.h: Regenerate.
837 * m32c-dis.c: Regenerate.
838 * m32c-ibld.c: Regenerate.
839 * m32c-opc.c: Regenerate.
840 * m32c-opc.h: Regenerate.
841 * m32r-asm.c: Regenerate.
842 * m32r-desc.c: Regenerate.
843 * m32r-desc.h: Regenerate.
844 * m32r-dis.c: Regenerate.
845 * m32r-ibld.c: Regenerate.
846 * m32r-opc.c: Regenerate.
847 * m32r-opc.h: Regenerate.
848 * m32r-opinst.c: Regenerate.
849 * mep-asm.c: Regenerate.
850 * mep-desc.c: Regenerate.
851 * mep-desc.h: Regenerate.
852 * mep-dis.c: Regenerate.
853 * mep-ibld.c: Regenerate.
854 * mep-opc.c: Regenerate.
855 * mep-opc.h: Regenerate.
856 * mt-asm.c: Regenerate.
857 * mt-desc.c: Regenerate.
858 * mt-desc.h: Regenerate.
859 * mt-dis.c: Regenerate.
860 * mt-ibld.c: Regenerate.
861 * mt-opc.c: Regenerate.
862 * mt-opc.h: Regenerate.
863 * or1k-asm.c: Regenerate.
864 * or1k-desc.c: Regenerate.
865 * or1k-desc.h: Regenerate.
866 * or1k-dis.c: Regenerate.
867 * or1k-ibld.c: Regenerate.
868 * or1k-opc.c: Regenerate.
869 * or1k-opc.h: Regenerate.
870 * or1k-opinst.c: Regenerate.
871 * xc16x-asm.c: Regenerate.
872 * xc16x-desc.c: Regenerate.
873 * xc16x-desc.h: Regenerate.
874 * xc16x-dis.c: Regenerate.
875 * xc16x-ibld.c: Regenerate.
876 * xc16x-opc.c: Regenerate.
877 * xc16x-opc.h: Regenerate.
878 * xstormy16-asm.c: Regenerate.
879 * xstormy16-desc.c: Regenerate.
880 * xstormy16-desc.h: Regenerate.
881 * xstormy16-dis.c: Regenerate.
882 * xstormy16-ibld.c: Regenerate.
883 * xstormy16-opc.c: Regenerate.
884 * xstormy16-opc.h: Regenerate.
885
7639175c
AM		 8862017-07-07 Alan Modra <amodra@gmail.com>
887
888 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
889 * m32c-dis.c: Regenerate.
890 * mep-dis.c: Regenerate.
891
e4bdd679
BP		 8922017-07-05 Borislav Petkov <bp@suse.de>
893
894 * i386-dis.c: Enable ModRM.reg /6 aliases.
895
60c96dbf
RR		 8962017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
897
898 * opcodes/arm-dis.c: Support MVFR2 in disassembly
899 with vmrs and vmsr.
900
0d702cfe
TG		 9012017-07-04 Tristan Gingold <gingold@adacore.com>
902
903 * configure: Regenerate.
904
15e6ed8c
TG		 9052017-07-03 Tristan Gingold <gingold@adacore.com>
906
907 * po/opcodes.pot: Regenerate.
908
b1d3c886
MR		 9092017-06-30 Maciej W. Rozycki <macro@imgtec.com>
910
911 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
912 entries to the MSA ASE instruction block.
913
909b4e3d
MR		 9142017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
915 Maciej W. Rozycki <macro@imgtec.com>
916
917 * micromips-opc.c (XPA, XPAVZ): New macros.
918 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
919 "mthgc0".
920
f5b2fd52
MR		 9212017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
922 Maciej W. Rozycki <macro@imgtec.com>
923
924 * micromips-opc.c (I36): New macro.
925 (micromips_opcodes): Add "eretnc".
926
9785fc2a
MR		 9272017-06-30 Maciej W. Rozycki <macro@imgtec.com>
928 Andrew Bennett <andrew.bennett@imgtec.com>
929
930 * mips-dis.c (mips_calculate_combination_ases): Handle the
931 ASE_XPA_VIRT flag.
932 (parse_mips_ase_option): New function.
933 (parse_mips_dis_option): Factor out ASE option handling to the
934 new function. Call `mips_calculate_combination_ases'.
935 * mips-opc.c (XPAVZ): New macro.
936 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
937 "mfhgc0", "mthc0" and "mthgc0".
938
60804c53
MR		 9392017-06-29 Maciej W. Rozycki <macro@imgtec.com>
940
941 * mips-dis.c (mips_calculate_combination_ases): New function.
942 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
943 calculation to the new function.
944 (set_default_mips_dis_options): Call the new function.
945
2e74f9dd
AK		 9462017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
947
948 * arc-dis.c (parse_disassembler_options): Use
949 FOR_EACH_DISASSEMBLER_OPTION.
950
e1e94c49
AK		 9512017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
952
953 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
954 disassembler option strings.
955 (parse_cpu_option): Likewise.
956
65a55fbb
TC		 9572017-06-28 Tamar Christina <tamar.christina@arm.com>
958
959 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
960 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
961 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
962 (aarch64_feature_dotprod, DOT_INSN): New.
963 (udot, sdot): New.
964 * aarch64-dis-2.c: Regenerated.
965
c604a79a
JW		 9662017-06-28 Jiong Wang <jiong.wang@arm.com>
967
968 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
969
38bf472a
MR		 9702017-06-28 Maciej W. Rozycki <macro@imgtec.com>
971 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 972 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 973
974 * mips-formats.h (INT_BIAS): New macro.
975 (INT_ADJ): Redefine in INT_BIAS terms.
976 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
977 (mips_print_save_restore): New function.
978 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
979 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
980 call.
981 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
982 (print_mips16_insn_arg): Call `mips_print_save_restore' for
983 OP_SAVE_RESTORE_LIST handling, factored out from here.
984 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
985 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
986 (mips_builtin_opcodes): Add "restore" and "save" entries.
987 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
988 (IAMR2): New macro.
989 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
990
9bdfdbf9
AW		 9912017-06-23 Andrew Waterman <andrew@sifive.com>
992
993 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
994 alias; do not mark SLTI instruction as an alias.
995
2234eee6
L		 9962017-06-21 H.J. Lu <hongjiu.lu@intel.com>
997
998 * i386-dis.c (RM_0FAE_REG_5): Removed.
999 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1000 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
1001 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
1002 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
1003 PREFIX_MOD_3_0F01_REG_5_RM_0.
1004 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
1005 PREFIX_MOD_3_0FAE_REG_5.
1006 (mod_table): Update MOD_0FAE_REG_5.
1007 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
1008 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
1009 * i386-tbl.h: Regenerated.
1010
c2f76402
L		 10112017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1012
1013 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
1014 * i386-opc.tbl: Likewise.
1015 * i386-tbl.h: Regenerated.
1016
9fef80d6
L		 10172017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1018
1019 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
1020 and "jmp{&|}".
1021 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
1022 prefix.
1023
0f6d864d
NC		 10242017-06-19 Nick Clifton <nickc@redhat.com>
1025
1026 PR binutils/21614
1027 * score-dis.c (score_opcodes): Add sentinel.
1028
e197589b
AM		 10292017-06-16 Alan Modra <amodra@gmail.com>
1030
1031 * rx-decode.c: Regenerate.
1032
0d96e4df
L		 10332017-06-15 H.J. Lu <hongjiu.lu@intel.com>
1034
1035 PR binutils/21594
1036 * i386-dis.c (OP_E_register): Check valid bnd register.
1037 (OP_G): Likewise.
1038
cd3ea7c6
NC		 10392017-06-15 Nick Clifton <nickc@redhat.com>
1040
1041 PR binutils/21595
1042 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1043 range value.
1044
63323b5b
NC		 10452017-06-15 Nick Clifton <nickc@redhat.com>
1046
1047 PR binutils/21588
1048 * rl78-decode.opc (OP_BUF_LEN): Define.
1049 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1050 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1051 array.
1052 * rl78-decode.c: Regenerate.
1053
08c7881b
NC		 10542017-06-15 Nick Clifton <nickc@redhat.com>
1055
1056 PR binutils/21586
1057 * bfin-dis.c (gregs): Clip index to prevent overflow.
1058 (regs): Likewise.
1059 (regs_lo): Likewise.
1060 (regs_hi): Likewise.
1061
e64519d1
NC		 10622017-06-14 Nick Clifton <nickc@redhat.com>
1063
1064 PR binutils/21576
1065 * score7-dis.c (score_opcodes): Add sentinel.
1066
6394c606
YQ		 10672017-06-14 Yao Qi <yao.qi@linaro.org>
1068
1069 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1070 * arm-dis.c: Likewise.
1071 * ia64-dis.c: Likewise.
1072 * mips-dis.c: Likewise.
1073 * spu-dis.c: Likewise.
1074 * disassemble.h (print_insn_aarch64): New declaration, moved from
1075 include/dis-asm.h.
1076 (print_insn_big_arm, print_insn_big_mips): Likewise.
1077 (print_insn_i386, print_insn_ia64): Likewise.
1078 (print_insn_little_arm, print_insn_little_mips): Likewise.
1079
db5fa770
NC		 10802017-06-14 Nick Clifton <nickc@redhat.com>
1081
1082 PR binutils/21587
1083 * rx-decode.opc: Include libiberty.h
1084 (GET_SCALE): New macro - validates access to SCALE array.
1085 (GET_PSCALE): New macro - validates access to PSCALE array.
1086 (DIs, SIs, S2Is, rx_disp): Use new macros.
1087 * rx-decode.c: Regenerate.
1088
05c966f3
AV		 10892017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
1090
1091 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1092
10045478
AK		 10932017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
1094
1095 * arc-dis.c (enforced_isa_mask): Declare.
1096 (cpu_types): Likewise.
1097 (parse_cpu_option): New function.
1098 (parse_disassembler_options): Use it.
1099 (print_insn_arc): Use enforced_isa_mask.
1100 (print_arc_disassembler_options): Document new options.
1101
88c1242d
YQ		 11022017-05-24 Yao Qi <yao.qi@linaro.org>
1103
1104 * alpha-dis.c: Include disassemble.h, don't include
1105 dis-asm.h.
1106 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1107 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1108 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1109 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1110 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1111 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1112 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1113 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1114 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1115 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1116 * moxie-dis.c, msp430-dis.c, mt-dis.c:
1117 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1118 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1119 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1120 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1121 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1122 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1123 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1124 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1125 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1126 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1127 * z80-dis.c, z8k-dis.c: Likewise.
1128 * disassemble.h: New file.
1129
ab20fa4a
YQ		 11302017-05-24 Yao Qi <yao.qi@linaro.org>
1131
1132 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1133 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1134
003ca0fd
YQ		 11352017-05-24 Yao Qi <yao.qi@linaro.org>
1136
1137 * disassemble.c (disassembler): Add arguments a, big and mach.
1138 Use them.
1139
04ef582a
L		 11402017-05-22 H.J. Lu <hongjiu.lu@intel.com>
1141
1142 * i386-dis.c (NOTRACK_Fixup): New.
1143 (NOTRACK): Likewise.
1144 (NOTRACK_PREFIX): Likewise.
1145 (last_active_prefix): Likewise.
1146 (reg_table): Use NOTRACK on indirect call and jmp.
1147 (ckprefix): Set last_active_prefix.
1148 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1149 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1150 * i386-opc.h (NoTrackPrefixOk): New.
1151 (i386_opcode_modifier): Add notrackprefixok.
1152 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1153 Add notrack.
1154 * i386-tbl.h: Regenerated.
1155
64517994
JM		 11562017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1157
1158 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1159 (X_IMM2): Define.
1160 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1161 bfd_mach_sparc_v9m8.
1162 (print_insn_sparc): Handle new operand types.
1163 * sparc-opc.c (MASK_M8): Define.
1164 (v6): Add MASK_M8.
1165 (v6notlet): Likewise.
1166 (v7): Likewise.
1167 (v8): Likewise.
1168 (v9): Likewise.
1169 (v9a): Likewise.
1170 (v9b): Likewise.
1171 (v9c): Likewise.
1172 (v9d): Likewise.
1173 (v9e): Likewise.
1174 (v9v): Likewise.
1175 (v9m): Likewise.
1176 (v9andleon): Likewise.
1177 (m8): Define.
1178 (HWS_VM8): Define.
1179 (HWS2_VM8): Likewise.
1180 (sparc_opcode_archs): Add entry for "m8".
1181 (sparc_opcodes): Add OSA2017 and M8 instructions
1182 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1183 fpx{ll,ra,rl}64x,
1184 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1185 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1186 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1187 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1188 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1189 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1190 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1191 ASI_CORE_SELECT_COMMIT_NHT.
1192
535b785f
AM		 11932017-05-18 Alan Modra <amodra@gmail.com>
1194
1195 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1196 * aarch64-dis.c: Likewise.
1197 * aarch64-gen.c: Likewise.
1198 * aarch64-opc.c: Likewise.
1199
25499ac7
MR		 12002017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1201 Matthew Fortune <matthew.fortune@imgtec.com>
1202
1203 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1204 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1205 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1206 (print_insn_arg) <OP_REG28>: Add handler.
1207 (validate_insn_args) <OP_REG28>: Handle.
1208 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1209 32-bit encoding and 9-bit immediates.
1210 (print_insn_mips16): Handle MIPS16 instructions that require
1211 32-bit encoding and MFC0/MTC0 operand decoding.
1212 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1213 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1214 (RD_C0, WR_C0, E2, E2MT): New macros.
1215 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1216 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1217 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1218 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1219 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1220 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1221 instructions, "swl", "swr", "sync" and its "sync_acquire",
1222 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1223 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1224 regular/extended entries for original MIPS16 ISA revision
1225 instructions whose extended forms are subdecoded in the MIPS16e2
1226 ISA revision: "li", "sll" and "srl".
1227
fdfb4752
MR		 12282017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1229
1230 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1231 reference in CP0 move operand decoding.
1232
a4f89915
MR		 12332017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1234
1235 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1236 type to hexadecimal.
1237 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1238
99e2d67a
MR		 12392017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1240
1241 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1242 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1243 "sync_rmb" and "sync_wmb" as aliases.
1244 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1245 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1246
53a346d8
CZ		 12472017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1248
1249 * arc-dis.c (parse_option): Update quarkse_em option..
1250 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1251 QUARKSE1.
1252 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1253
f91d48de
KC		 12542017-05-03 Kito Cheng <kito.cheng@gmail.com>
1255
1256 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1257
43e379d7
MC		 12582017-05-01 Michael Clark <michaeljclark@mac.com>
1259
1260 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1261 register.
1262
a4ddc54e
MR		 12632017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1264
1265 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1266 and branches and not synthetic data instructions.
1267
fe50e98c
BE		 12682017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1269
1270 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1271
126124cc
CZ		 12722017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1273
1274 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1275 * arc-opc.c (insert_r13el): New function.
1276 (R13_EL): Define.
1277 * arc-tbl.h: Add new enter/leave variants.
1278
be6a24d8
CZ		 12792017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1280
1281 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1282
0348fd79
MR		 12832017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1284
1285 * mips-dis.c (print_mips_disassembler_options): Add
1286 `no-aliases'.
1287
6e3d1f07
MR		 12882017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1289
1290 * mips16-opc.c (AL): New macro.
1291 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1292 of "ld" and "lw" as aliases.
1293
957f6b39
TC		 12942017-04-24 Tamar Christina <tamar.christina@arm.com>
1295
1296 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1297 arguments.
1298
a8cc8a54
AM		 12992017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1300 Alan Modra <amodra@gmail.com>
1301
1302 * ppc-opc.c (ELEV): Define.
1303 (vle_opcodes): Add se_rfgi and e_sc.
1304 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1305 for E200Z4.
1306
3ab87b68
JM		 13072017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1308
1309 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1310
792f174f
NC		 13112017-04-21 Nick Clifton <nickc@redhat.com>
1312
1313 PR binutils/21380
1314 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1315 LD3R and LD4R.
1316
42742084
AM		 13172017-04-13 Alan Modra <amodra@gmail.com>
1318
1319 * epiphany-desc.c: Regenerate.
1320 * fr30-desc.c: Regenerate.
1321 * frv-desc.c: Regenerate.
1322 * ip2k-desc.c: Regenerate.
1323 * iq2000-desc.c: Regenerate.
1324 * lm32-desc.c: Regenerate.
1325 * m32c-desc.c: Regenerate.
1326 * m32r-desc.c: Regenerate.
1327 * mep-desc.c: Regenerate.
1328 * mt-desc.c: Regenerate.
1329 * or1k-desc.c: Regenerate.
1330 * xc16x-desc.c: Regenerate.
1331 * xstormy16-desc.c: Regenerate.
1332
9a85b496
AM		 13332017-04-11 Alan Modra <amodra@gmail.com>
1334
ef85eab0 1335 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 1336 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1337 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 1338 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1339 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 1340 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1341 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 1342 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 1343 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 1344
62adc510
AM		 13452017-04-10 Alan Modra <amodra@gmail.com>
1346
1347 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1348 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1349 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1350 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1351
aa808707
PC		 13522017-04-09 Pip Cet <pipcet@gmail.com>
1353
1354 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1355 appropriate floating-point precision directly.
1356
ac8f0f72
AM		 13572017-04-07 Alan Modra <amodra@gmail.com>
1358
1359 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1360 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1361 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1362 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1363 vector instructions with E6500 not PPCVEC2.
1364
62ecb94c
PC		 13652017-04-06 Pip Cet <pipcet@gmail.com>
1366
1367 * Makefile.am: Add wasm32-dis.c.
1368 * configure.ac: Add wasm32-dis.c to wasm32 target.
1369 * disassemble.c: Add wasm32 disassembler code.
1370 * wasm32-dis.c: New file.
1371 * Makefile.in: Regenerate.
1372 * configure: Regenerate.
1373 * po/POTFILES.in: Regenerate.
1374 * po/opcodes.pot: Regenerate.
1375
f995bbe8
PA		 13762017-04-05 Pedro Alves <palves@redhat.com>
1377
1378 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1379 * arm-dis.c (parse_arm_disassembler_options): Constify.
1380 * ppc-dis.c (powerpc_init_dialect): Constify local.
1381 * vax-dis.c (parse_disassembler_options): Constify.
1382
b5292032
PD		 13832017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1384
1385 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1386 RISCV_GP_SYMBOL.
1387
f96bd6c2
PC		 13882017-03-30 Pip Cet <pipcet@gmail.com>
1389
1390 * configure.ac: Add (empty) bfd_wasm32_arch target.
1391 * configure: Regenerate
1392 * po/opcodes.pot: Regenerate.
1393
f7c514a3
JM		 13942017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1395
1396 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1397 OSA2015.
1398 * opcodes/sparc-opc.c (asi_table): New ASIs.
1399
52be03fd
AM		 14002017-03-29 Alan Modra <amodra@gmail.com>
1401
1402 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1403 "raw" option.
1404 (lookup_powerpc): Don't special case -1 dialect. Handle
1405 PPC_OPCODE_RAW.
1406 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1407 lookup_powerpc call, pass it on second.
1408
9b753937
AM		 14092017-03-27 Alan Modra <amodra@gmail.com>
1410
1411 PR 21303
1412 * ppc-dis.c (struct ppc_mopt): Comment.
1413 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1414
c0c31e91
RZ		 14152017-03-27 Rinat Zelig <rinat@mellanox.com>
1416
1417 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1418 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1419 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1420 (insert_nps_misc_imm_offset): New function.
1421 (extract_nps_misc imm_offset): New function.
1422 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1423 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1424
2253c8f0
AK		 14252017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1426
1427 * s390-mkopc.c (main): Remove vx2 check.
1428 * s390-opc.txt: Remove vx2 instruction flags.
1429
645d3342
RZ		 14302017-03-21 Rinat Zelig <rinat@mellanox.com>
1431
1432 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1433 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1434 (insert_nps_imm_offset): New function.
1435 (extract_nps_imm_offset): New function.
1436 (insert_nps_imm_entry): New function.
1437 (extract_nps_imm_entry): New function.
1438
4b94dd2d
AM		 14392017-03-17 Alan Modra <amodra@gmail.com>
1440
1441 PR 21248
1442 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1443 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1444 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1445
b416fe87
KC		 14462017-03-14 Kito Cheng <kito.cheng@gmail.com>
1447
1448 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1449 <c.andi>: Likewise.
1450 <c.addiw> Likewise.
1451
03b039a5
KC		 14522017-03-14 Kito Cheng <kito.cheng@gmail.com>
1453
1454 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1455
2c232b83
AW		 14562017-03-13 Andrew Waterman <andrew@sifive.com>
1457
1458 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1459 <srl> Likewise.
1460 <srai> Likewise.
1461 <sra> Likewise.
1462
86fa6981
L		 14632017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1464
1465 * i386-gen.c (opcode_modifiers): Replace S with Load.
1466 * i386-opc.h (S): Removed.
1467 (Load): New.
1468 (i386_opcode_modifier): Replace s with load.
1469 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1470 and {evex}. Replace S with Load.
1471 * i386-tbl.h: Regenerated.
1472
c1fe188b
L		 14732017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1474
1475 * i386-opc.tbl: Use CpuCET on rdsspq.
1476 * i386-tbl.h: Regenerated.
1477
4b8b687e
PB		 14782017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1479
1480 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1481 <vsx>: Do not use PPC_OPCODE_VSX3;
1482
1437d063
PB		 14832017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1484
1485 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1486
603555e5
L		 14872017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1488
1489 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1490 (MOD_0F1E_PREFIX_1): Likewise.
1491 (MOD_0F38F5_PREFIX_2): Likewise.
1492 (MOD_0F38F6_PREFIX_0): Likewise.
1493 (RM_0F1E_MOD_3_REG_7): Likewise.
1494 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1495 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1496 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1497 (PREFIX_0F1E): Likewise.
1498 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1499 (PREFIX_0F38F5): Likewise.
1500 (dis386_twobyte): Use PREFIX_0F1E.
1501 (reg_table): Add REG_0F1E_MOD_3.
1502 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1503 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1504 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1505 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1506 (three_byte_table): Use PREFIX_0F38F5.
1507 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1508 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1509 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1510 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1511 PREFIX_MOD_3_0F01_REG_5_RM_2.
1512 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1513 (cpu_flags): Add CpuCET.
1514 * i386-opc.h (CpuCET): New enum.
1515 (CpuUnused): Commented out.
1516 (i386_cpu_flags): Add cpucet.
1517 * i386-opc.tbl: Add Intel CET instructions.
1518 * i386-init.h: Regenerated.
1519 * i386-tbl.h: Likewise.
1520
73f07bff
AM		 15212017-03-06 Alan Modra <amodra@gmail.com>
1522
1523 PR 21124
1524 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1525 (extract_raq, extract_ras, extract_rbx): New functions.
1526 (powerpc_operands): Use opposite corresponding insert function.
1527 (Q_MASK): Define.
1528 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1529 register restriction.
1530
65b48a81
PB		 15312017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1532
1533 * disassemble.c Include "safe-ctype.h".
1534 (disassemble_init_for_target): Handle s390 init.
1535 (remove_whitespace_and_extra_commas): New function.
1536 (disassembler_options_cmp): Likewise.
1537 * arm-dis.c: Include "libiberty.h".
1538 (NUM_ELEM): Delete.
1539 (regnames): Use long disassembler style names.
1540 Add force-thumb and no-force-thumb options.
1541 (NUM_ARM_REGNAMES): Rename from this...
1542 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1543 (get_arm_regname_num_options): Delete.
1544 (set_arm_regname_option): Likewise.
1545 (get_arm_regnames): Likewise.
1546 (parse_disassembler_options): Likewise.
1547 (parse_arm_disassembler_option): Rename from this...
1548 (parse_arm_disassembler_options): ...to this. Make static.
1549 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1550 (print_insn): Use parse_arm_disassembler_options.
1551 (disassembler_options_arm): New function.
1552 (print_arm_disassembler_options): Handle updated regnames.
1553 * ppc-dis.c: Include "libiberty.h".
1554 (ppc_opts): Add "32" and "64" entries.
1555 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1556 (powerpc_init_dialect): Add break to switch statement.
1557 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1558 (disassembler_options_powerpc): New function.
1559 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1560 Remove printing of "32" and "64".
1561 * s390-dis.c: Include "libiberty.h".
1562 (init_flag): Remove unneeded variable.
1563 (struct s390_options_t): New structure type.
1564 (options): New structure.
1565 (init_disasm): Rename from this...
1566 (disassemble_init_s390): ...to this. Add initializations for
1567 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1568 (print_insn_s390): Delete call to init_disasm.
1569 (disassembler_options_s390): New function.
1570 (print_s390_disassembler_options): Print using information from
1571 struct 'options'.
1572 * po/opcodes.pot: Regenerate.
1573
15c7c1d8
JB		 15742017-02-28 Jan Beulich <jbeulich@suse.com>
1575
1576 * i386-dis.c (PCMPESTR_Fixup): New.
1577 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1578 (prefix_table): Use PCMPESTR_Fixup.
1579 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1580 PCMPESTR_Fixup.
1581 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1582 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1583 Split 64-bit and non-64-bit variants.
1584 * opcodes/i386-tbl.h: Re-generate.
1585
582e12bf
RS		 15862017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1587
1588 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1589 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1590 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1591 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1592 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1593 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1594 (OP_SVE_V_HSD): New macros.
1595 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1596 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1597 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1598 (aarch64_opcode_table): Add new SVE instructions.
1599 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1600 for rotation operands. Add new SVE operands.
1601 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1602 (ins_sve_quad_index): Likewise.
1603 (ins_imm_rotate): Split into...
1604 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1605 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1606 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1607 functions.
1608 (aarch64_ins_sve_addr_ri_s4): New function.
1609 (aarch64_ins_sve_quad_index): Likewise.
1610 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1611 * aarch64-asm-2.c: Regenerate.
1612 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1613 (ext_sve_quad_index): Likewise.
1614 (ext_imm_rotate): Split into...
1615 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1616 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1617 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1618 functions.
1619 (aarch64_ext_sve_addr_ri_s4): New function.
1620 (aarch64_ext_sve_quad_index): Likewise.
1621 (aarch64_ext_sve_index): Allow quad indices.
1622 (do_misc_decoding): Likewise.
1623 * aarch64-dis-2.c: Regenerate.
1624 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1625 aarch64_field_kinds.
1626 (OPD_F_OD_MASK): Widen by one bit.
1627 (OPD_F_NO_ZR): Bump accordingly.
1628 (get_operand_field_width): New function.
1629 * aarch64-opc.c (fields): Add new SVE fields.
1630 (operand_general_constraint_met_p): Handle new SVE operands.
1631 (aarch64_print_operand): Likewise.
1632 * aarch64-opc-2.c: Regenerate.
1633
f482d304
RS		 16342017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1635
1636 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1637 (aarch64_feature_compnum): ...this.
1638 (SIMD_V8_3): Replace with...
1639 (COMPNUM): ...this.
1640 (CNUM_INSN): New macro.
1641 (aarch64_opcode_table): Use it for the complex number instructions.
1642
7db2c588
JB		 16432017-02-24 Jan Beulich <jbeulich@suse.com>
1644
1645 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1646
1e9d41d4
SL		 16472017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1648
1649 Add support for associating SPARC ASIs with an architecture level.
1650 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1651 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1652 decoding of SPARC ASIs.
1653
53c4d625
JB		 16542017-02-23 Jan Beulich <jbeulich@suse.com>
1655
1656 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1657 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1658
11648de5
JB		 16592017-02-21 Jan Beulich <jbeulich@suse.com>
1660
1661 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1662 1 (instead of to itself). Correct typo.
1663
f98d33be
AW		 16642017-02-14 Andrew Waterman <andrew@sifive.com>
1665
1666 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1667 pseudoinstructions.
1668
773fb663
RS		 16692017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1670
1671 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1672 (aarch64_sys_reg_supported_p): Handle them.
1673
cc07cda6
CZ		 16742017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1675
1676 * arc-opc.c (UIMM6_20R): Define.
1677 (SIMM12_20): Use above.
1678 (SIMM12_20R): Define.
1679 (SIMM3_5_S): Use above.
1680 (UIMM7_A32_11R_S): Define.
1681 (UIMM7_9_S): Use above.
1682 (UIMM3_13R_S): Define.
1683 (SIMM11_A32_7_S): Use above.
1684 (SIMM9_8R): Define.
1685 (UIMM10_A32_8_S): Use above.
1686 (UIMM8_8R_S): Define.
1687 (W6): Use above.
1688 (arc_relax_opcodes): Use all above defines.
1689
66a5a740
VG		 16902017-02-15 Vineet Gupta <vgupta@synopsys.com>
1691
1692 * arc-regs.h: Distinguish some of the registers different on
1693 ARC700 and HS38 cpus.
1694
7e0de605
AM		 16952017-02-14 Alan Modra <amodra@gmail.com>
1696
1697 PR 21118
1698 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1699 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1700
54064fdb
AM		 17012017-02-11 Stafford Horne <shorne@gmail.com>
1702 Alan Modra <amodra@gmail.com>
1703
1704 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1705 Use insn_bytes_value and insn_int_value directly instead. Don't
1706 free allocated memory until function exit.
1707
dce75bf9
NP		 17082017-02-10 Nicholas Piggin <npiggin@gmail.com>
1709
1710 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1711
1b7e3d2f
NC		 17122017-02-03 Nick Clifton <nickc@redhat.com>
1713
1714 PR 21096
1715 * aarch64-opc.c (print_register_list): Ensure that the register
1716 list index will fir into the tb buffer.
1717 (print_register_offset_address): Likewise.
1718 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1719
8ec5cf65
AD		 17202017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1721
1722 PR 21056
1723 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1724 instructions when the previous fetch packet ends with a 32-bit
1725 instruction.
1726
a1aa5e81
DD		 17272017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1728
1729 * pru-opc.c: Remove vague reference to a future GDB port.
1730
add3afb2
NC		 17312017-01-20 Nick Clifton <nickc@redhat.com>
1732
1733 * po/ga.po: Updated Irish translation.
1734
c13a63b0
SN		 17352017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1736
1737 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1738
9608051a
YQ		 17392017-01-13 Yao Qi <yao.qi@linaro.org>
1740
1741 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1742 if FETCH_DATA returns 0.
1743 (m68k_scan_mask): Likewise.
1744 (print_insn_m68k): Update code to handle -1 return value.
1745
f622ea96
YQ		 17462017-01-13 Yao Qi <yao.qi@linaro.org>
1747
1748 * m68k-dis.c (enum print_insn_arg_error): New.
1749 (NEXTBYTE): Replace -3 with
1750 PRINT_INSN_ARG_MEMORY_ERROR.
1751 (NEXTULONG): Likewise.
1752 (NEXTSINGLE): Likewise.
1753 (NEXTDOUBLE): Likewise.
1754 (NEXTDOUBLE): Likewise.
1755 (NEXTPACKED): Likewise.
1756 (FETCH_ARG): Likewise.
1757 (FETCH_DATA): Update comments.
1758 (print_insn_arg): Update comments. Replace magic numbers with
1759 enum.
1760 (match_insn_m68k): Likewise.
1761
620214f7
IT		 17622017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1763
1764 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1765 * i386-dis-evex.h (evex_table): Updated.
1766 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1767 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1768 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1769 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1770 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1771 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1772 * i386-init.h: Regenerate.
1773 * i386-tbl.h: Ditto.
1774
d95014a2
YQ		 17752017-01-12 Yao Qi <yao.qi@linaro.org>
1776
1777 * msp430-dis.c (msp430_singleoperand): Return -1 if
1778 msp430dis_opcode_signed returns false.
1779 (msp430_doubleoperand): Likewise.
1780 (msp430_branchinstr): Return -1 if
1781 msp430dis_opcode_unsigned returns false.
1782 (msp430x_calla_instr): Likewise.
1783 (print_insn_msp430): Likewise.
1784
0ae60c3e
NC		 17852017-01-05 Nick Clifton <nickc@redhat.com>
1786
1787 PR 20946
1788 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1789 could not be matched.
1790 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1791 NULL.
1792
d74d4880
SN		 17932017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1794
1795 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1796 (aarch64_opcode_table): Use RCPC_INSN.
1797
cc917fd9
KC		 17982017-01-03 Kito Cheng <kito.cheng@gmail.com>
1799
1800 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1801 extension.
1802 * riscv-opcodes/all-opcodes: Likewise.
1803
b52d3cfc
DP		 18042017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1805
1806 * riscv-dis.c (print_insn_args): Add fall through comment.
1807
f90c58d5
NC		 18082017-01-03 Nick Clifton <nickc@redhat.com>
1809
1810 * po/sr.po: New Serbian translation.
1811 * configure.ac (ALL_LINGUAS): Add sr.
1812 * configure: Regenerate.
1813
f47b0d4a
AM		 18142017-01-02 Alan Modra <amodra@gmail.com>
1815
1816 * epiphany-desc.h: Regenerate.
1817 * epiphany-opc.h: Regenerate.
1818 * fr30-desc.h: Regenerate.
1819 * fr30-opc.h: Regenerate.
1820 * frv-desc.h: Regenerate.
1821 * frv-opc.h: Regenerate.
1822 * ip2k-desc.h: Regenerate.
1823 * ip2k-opc.h: Regenerate.
1824 * iq2000-desc.h: Regenerate.
1825 * iq2000-opc.h: Regenerate.
1826 * lm32-desc.h: Regenerate.
1827 * lm32-opc.h: Regenerate.
1828 * m32c-desc.h: Regenerate.
1829 * m32c-opc.h: Regenerate.
1830 * m32r-desc.h: Regenerate.
1831 * m32r-opc.h: Regenerate.
1832 * mep-desc.h: Regenerate.
1833 * mep-opc.h: Regenerate.
1834 * mt-desc.h: Regenerate.
1835 * mt-opc.h: Regenerate.
1836 * or1k-desc.h: Regenerate.
1837 * or1k-opc.h: Regenerate.
1838 * xc16x-desc.h: Regenerate.
1839 * xc16x-opc.h: Regenerate.
1840 * xstormy16-desc.h: Regenerate.
1841 * xstormy16-opc.h: Regenerate.
1842
2571583a
AM		 18432017-01-02 Alan Modra <amodra@gmail.com>
1844
1845 Update year range in copyright notice of all files.
1846
5c1ad6b5 1847For older changes see ChangeLog-2016
3499769a 1848\f
5c1ad6b5 1849Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1850
1851Copying and distribution of this file, with or without modification,
1852are permitted in any medium without royalty provided the copyright
1853notice and this notice are preserved.
1854
1855Local Variables:
1856mode: change-log
1857left-margin: 8
1858fill-column: 74
1859version-control: never
1860End:
GDB Binutils - Deliverables
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