projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
opcodes/Changelog:
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
94dda8b7
ME		 12012-11-29 David Holsgrove <david.holsgrove@xilinx.com>
2
3 * microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to
4 INST_TYPE_R1_R2_SPECIAL
5 * microblaze-dis.c (print_insn_microblaze): Same.
6
776fc418
AM		 72012-11-23 Alan Modra <amodra@gmail.com>
8
9 * ppc-dis.c (ppc_parse_cpu): Add "sticky" param. Track bits
10 set from ppc_opts.sticky in it. Delete "retain_mask".
11 (powerpc_init_dialect): Choose default dialect from info->mach
12 before parsing -M options. Handle more bfd_mach_ppc variants.
13 Update common default to power7.
14
abe9f67d
ME		 152012-11-21 David Holsgrove <david.holsgrove@xilinx.com>
16
17 * microblaze-opc.h (op_code_struct): Add swapb, swaph Increase MAX_OPCODES.
18 * microblaze-opcm.h (microblaze_instr): Likewise
19
0db4b326
ME		 202012-11-21 Edgar E. Iglesias <edgar.iglesias@gmail.com>
21
22 * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
23 * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
24
9b30cccc
L		 252012-11-20 Kirill Yukhin <kirill.yukhin@intel.com>
26 H.J. Lu <hongjiu.lu@intel.com>
27
28 PR gas/14859
29 * i386-opc.tbl: Fix opcode for 64-bit jecxz.
30 * i386-tbl.h: Regenerated.
31
0b7fe784
AK		 322012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
33
34 * s390-opc.txt: Fix srstu and strag opcodes.
35
d3da7741
ME		 362012-11-14 David Holsgrove <david.holsgrove@xilinx.com>
37
38 * microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
39 update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
40 and increase MAX_OPCODES.
41 (op_code_struct): add mbar and sleep
42 * microblaze-opcm.h (microblaze_instr): add mbar
43 Define IMM_MBAR and IMM5_MBAR_MASK
44 * microblaze-dis.c: Add get_field_imm5_mbar
45 (print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE
46
ed8ec0ec
ME		 472012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
48
49 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add clz insn
50 * microblaze-opcm.h (microblaze_instr): add clz
51
e692c217
ME		 522012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
53
54 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur,
55 lhur, lwr, sbr, shr, swr
56 * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
57 swr
58
de863c74
NC		 592012-11-09 Nick Clifton <nickc@redhat.com>
60
61 * configure.in: Add bfd_v850_rh850_arch.
62 * configure: Regenerate.
63 * disassemble.c (disassembler): Likewise.
64
5bb3703f
L		 652012-11-09 H.J. Lu <hongjiu.lu@intel.com>
66
67 * aarch64-opc.h (gen_mask): Remove trailing redundant `;'.
68 * ia64-gen.c (fetch_insn_class): Likewise.
69
6febeb74
AM		 702012-11-08 Alan Modra <amodra@gmail.com>
71
72 * po/POTFILES.in: Regenerate.
73
d17dce55
AM		 742012-11-05 Alan Modra <amodra@gmail.com>
75
76 * configure.in: Apply 2012-09-10 change to config.in here.
77
aac129d7
AK		 782012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
79
80 * s390-mkopc.c: Accept empty lines in s390-opc.txt.
d17dce55
AM		 81 * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2
82 and RRF_RMRR.
aac129d7
AK		 83 * s390-opc.txt: Add new instructions. New instruction type for lptea.
84
747a4ac1
CG		 852012-10-26 Christian Groessler <chris@groessler.org>
86
87 * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb,
88 trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove
89 non-existing opcode trtrb.
90 * z8k-opc.h: Regenerate.
91
62082a42
AM		 922012-10-26 Alan Modra <amodra@gmail.com>
93
94 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
95
6c067bbb
RM		 962012-10-24 Roland McGrath <mcgrathr@google.com>
97
98 * i386-dis.c (ckprefix): When bailing out for fwait with prefixes,
99 set rex_used to rex.
100
ab4437c3
PB		 1012012-10-22 Peter Bergner <bergner@vnet.ibm.com>
102
103 * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
104
9a176a4a
TT		 1052012-10-18 Tom Tromey <tromey@redhat.com>
106
107 * tic54x-dis.c (print_instruction): Don't use K&R style.
108 (print_parallel_instruction, sprint_dual_address)
109 (sprint_indirect_address, sprint_direct_address, sprint_mmr)
110 (sprint_cc2, sprint_condition): Likewise.
111
4ad3b7ef
KT		 1122012-10-18 Kai Tietz <ktietz@redhat.com>
113
114 * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
115 value with a default.
116 (do_special_encoding): Likewise.
117 (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
118 variables with default.
119 * arc-dis.c (write_comments_): Don't use strncat due
120 size of state->commentBuffer pointer isn't predictable.
121
b7a54b55
YZ		 1222012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
123
124 * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
125 rmr_el3; remove daifset and daifclr.
126
9b61754a
YZ		 1272012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
128
129 * aarch64-opc.c (operand_general_constraint_met_p): Change to check
130 the alignment of addr.offset.imm instead of that of shifter.amount for
131 operand type AARCH64_OPND_ADDR_UIMM12.
132
f8ece37f
RE		 1332012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
134
135 * arm-dis.c: Use preferred form of vrint instruction variants
136 for disassembly.
137
5e5c50d3
NE		 1382012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
139
140 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
141 * i386-init.h: Regenerated.
142
c7a5aa9c
PB		 1432012-10-05 Peter Bergner <bergner@vnet.ibm.com>
144
145 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
146 * ppc-opc.c (VBA): New define.
147 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
148 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
149
04ee5257
NC		 1502012-10-04 Nick Clifton <nickc@redhat.com>
151
152 * v850-dis.c (disassemble): Place square parentheses around second
153 register operand of clr1, not1, set1 and tst1 instructions.
154
cfc72779
AK		 1552012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
156
157 * s390-mkopc.c: Support new option zEC12.
158 * s390-opc.c: Add new instruction formats.
159 * s390-opc.txt: Add new instructions for zEC12.
160
1415a2a7
AG		 1612012-09-27 Anthony Green <green@moxielogic.com>
162
163 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
164 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
165
160a30bb
L		 1662012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
167
04ee5257
NC		 168 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
169 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
160a30bb
L		 170 and CPU_BTVER2_FLAGS.
171 * i386-init.h: Regenerated.
172
60aa667e
L		 1732012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
174
175 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
176 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
177 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
178 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
179 (cpu_flags): Add CpuCX16.
180 * i386-opc.h (CpuCX16): New.
181 (i386_cpu_flags): Add cpucx16.
182 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
183 * i386-tbl.h: Regenerate.
184 * i386-init.h: Likewise.
185
4b8c8c02
RE		 1862012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
187
60aa667e 188 * arm-dis.c: Changed ldra and strl-form mnemonics
4b8c8c02
RE		 189 to lda and stl-form.
190
83ea18d0
MR		 1912012-09-18 Chao-ying Fu <fu@mips.com>
192
193 * micromips-opc.c (micromips_opcodes): Correct the encoding of
194 the "swxc1" instruction.
195
062f38fa
RE		 1962012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
197
198 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
199 the parameter 'inst'.
200 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
201 (convert_mov_to_movewide): Change to assert (0) when
202 aarch64_wide_constant_p returns FALSE.
203
b132a67d
DE		 2042012-09-14 David Edelsohn <dje.gcc@gmail.com>
205
206 * configure: Regenerate.
207
1f9b75dd
AG		 2082012-09-14 Anthony Green <green@moxielogic.com>
209
210 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
211 the address after the branch instruction.
212
e202fa84
AG		 2132012-09-13 Anthony Green <green@moxielogic.com>
214
215 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
216
00716ab1
AM		 2172012-09-10 Matthias Klose <doko@ubuntu.com>
218
219 * config.in: Disable sanity check for kfreebsd.
220
6d2920c8
L		 2212012-09-10 H.J. Lu <hongjiu.lu@intel.com>
222
223 * configure: Regenerated.
224
b3e14eda
L		 2252012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
226
227 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
228 * ia64-gen.c: Promote completer index type to longlong.
229 (irf_operand): Add new register recognition.
230 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
231 (lookup_specifier): Add new resource recognition.
232 (insert_bit_table_ent): Relax abort condition according to the
233 changed completer index type.
234 (print_dis_table): Fix printf format for completer index.
235 * ia64-ic.tbl: Add a new instruction class.
236 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
237 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
238 * ia64-opc.h: Define short names for new operand types.
239 * ia64-raw.tbl: Add new RAW resource for DAHR register.
240 * ia64-waw.tbl: Add new WAW resource for DAHR register.
241 * ia64-asmtab.c: Regenerate.
242
382c72e9
PB		 2432012-08-29 Peter Bergner <bergner@vnet.ibm.com>
244
245 * ppc-opc.c (VXASHB_MASK): New define.
246 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
247
fb048c26
PB		 2482012-08-28 Peter Bergner <bergner@vnet.ibm.com>
249
250 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
251 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
252 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
253 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
254 vupklsh>: Use VXVA_MASK.
255 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
256 <mfvscr>: Use VXVAVB_MASK.
257 <mtvscr>: Use VXVDVA_MASK.
258 <vspltb>: Use VXUIMM4_MASK.
259 <vsplth>: Use VXUIMM3_MASK.
260 <vspltw>: Use VXUIMM2_MASK.
261
3c9017d2
MGD		 2622012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
263
264 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
265
48adcd8e
MGD		 2662012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
267
268 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
269
4f51b4bd
MGD		 2702012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
271
272 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
273
91ff7894
MGD		 2742012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
275
276 * arm-dis.c (neon_opcodes): Add support for AES instructions.
277
c70a8987
MGD		 2782012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
279
280 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
281 conversions.
282
30bdf752
MGD		 2832012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
284
285 * arm-dis.c (coprocessor_opcodes): Add VRINT.
286 (neon_opcodes): Likewise.
287
7e8e6784
MGD		 2882012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
289
290 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
291 variants.
292 (neon_opcodes): Likewise.
293
73924fbc
MGD		 2942012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
295
296 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
297 (neon_opcodes): Likewise.
298
33399f07
MGD		 2992012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
300
301 * arm-dis.c (coprocessor_opcodes): Add VSEL.
302 (print_insn_coprocessor): Add new %<>c bitfield format
303 specifier.
304
9eb6c0f1
MGD		 3052012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
306
307 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
308 (thumb32_opcodes): Likewise.
309 (print_arm_insn): Add support for %<>T formatter.
310
8884b720
MGD		 3112012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
312
313 * arm-dis.c (arm_opcodes): Add HLT.
314 (thumb_opcodes): Likewise.
315
b79f7053
MGD		 3162012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
317
318 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
319
53c4b28b
MGD		 3202012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
321
322 * arm-dis.c (arm_opcodes): Add SEVL.
323 (thumb_opcodes): Likewise.
324 (thumb32_opcodes): Likewise.
325
e797f7e0
MGD		 3262012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
327
328 * arm-dis.c (data_barrier_option): New function.
329 (print_insn_arm): Use data_barrier_option.
330 (print_insn_thumb32): Use data_barrier_option.
331
e2efe87d
MGD		 3322012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
333
334 * arm-dis.c (COND_UNCOND): New constant.
335 (print_insn_coprocessor): Add support for %u format specifier.
336 (print_insn_neon): Likewise.
337
2c63854f
DM		 3382012-08-21 David S. Miller <davem@davemloft.net>
339
340 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
341 F3F4 macro.
342
e67ed0e8
AM		 3432012-08-20 Edmar Wienskoski <edmar@freescale.com>
344
345 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
346 vabsduh, vabsduw, mviwsplt.
347
7b458c12
L		 3482012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
349
350 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
351 CPU_BTVER2_FLAGS.
352
e67ed0e8 353 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 354
355 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
356 * i386-init.h: Regenerated.
357 * i386-tbl.h: Likewise.
358
eb80cb87
NC		 3592012-08-17 Nick Clifton <nickc@redhat.com>
360
361 * po/uk.po: New Ukranian translation.
362 * configure.in (ALL_LINGUAS): Add uk.
363 * configure: Regenerate.
364
8baf7b78
PB		 3652012-08-16 Peter Bergner <bergner@vnet.ibm.com>
366
367 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
368 RBX for the third operand.
369 <"lswi">: Use RAX for second and NBI for the third operand.
370
3d557b4c
DD		 3712012-08-15 DJ Delorie <dj@redhat.com>
372
373 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
374 operands, so that data addresses can be corrected when not
375 ES-overridden.
376 * rl78-decode.c: Regenerate.
377 * rl78-dis.c (print_insn_rl78): Make order of modifiers
378 irrelevent. When the 'e' specifier is used on an operand and no
379 ES prefix is provided, adjust address to make it absolute.
380
588925d0
PB		 3812012-08-15 Peter Bergner <bergner@vnet.ibm.com>
382
383 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
384
9f6a6cc0
PB		 3852012-08-15 Peter Bergner <bergner@vnet.ibm.com>
386
387 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
388
fc8c4fd1
MR		 3892012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
390
391 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
392 macros, use local variables for info struct member accesses,
393 update the type of the variable used to hold the instruction
394 word.
395 (print_insn_mips, print_mips16_insn_arg): Likewise.
396 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
397 local variables for info struct member accesses.
398 (print_insn_micromips): Add GET_OP_S local macro.
399 (_print_insn_mips): Update the type of the variable used to hold
400 the instruction word.
401
a06ea964 4022012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 403 Laurent Desnogues <laurent.desnogues@arm.com>
404 Jim MacArthur <jim.macarthur@arm.com>
405 Marcus Shawcroft <marcus.shawcroft@arm.com>
406 Nigel Stephens <nigel.stephens@arm.com>
407 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
408 Richard Earnshaw <rearnsha@arm.com>
409 Sofiane Naci <sofiane.naci@arm.com>
410 Tejas Belagod <tejas.belagod@arm.com>
411 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 412
413 * Makefile.am: Add AArch64.
414 * Makefile.in: Regenerate.
415 * aarch64-asm.c: New file.
416 * aarch64-asm.h: New file.
417 * aarch64-dis.c: New file.
418 * aarch64-dis.h: New file.
419 * aarch64-gen.c: New file.
420 * aarch64-opc.c: New file.
421 * aarch64-opc.h: New file.
422 * aarch64-tbl.h: New file.
423 * configure.in: Add AArch64.
424 * configure: Regenerate.
425 * disassemble.c: Add AArch64.
426 * aarch64-asm-2.c: New file (automatically generated).
427 * aarch64-dis-2.c: New file (automatically generated).
428 * aarch64-opc-2.c: New file (automatically generated).
429 * po/POTFILES.in: Regenerate.
430
35d0a169
MR		 4312012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
432
433 * micromips-opc.c (micromips_opcodes): Update comment.
434 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
435 instructions for IOCT as appropriate.
436 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
437 opcode_is_member.
438 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
439 the result of a check for the -Wno-missing-field-initializers
440 GCC option.
441 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
442 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
443 compilation.
444 (mips16-opc.lo): Likewise.
445 (micromips-opc.lo): Likewise.
446 * aclocal.m4: Regenerate.
447 * configure: Regenerate.
448 * Makefile.in: Regenerate.
449
5c5acbbd
L		 4502012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
451
452 PR gas/14423
453 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
454 * i386-init.h: Regenerated.
455
3c892704
NC		 4562012-08-09 Nick Clifton <nickc@redhat.com>
457
458 * po/vi.po: Updated Vietnamese translation.
459
d7189fa5
RM		 4602012-08-07 Roland McGrath <mcgrathr@google.com>
461
462 * i386-dis.c (reg_table): Fill out REG_0F0D table with
463 AMD-reserved cases as "prefetch".
464 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
465 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
466 (reg_table): Use those under REG_0F18.
467 (mod_table): Add those cases as "nop/reserved".
468
4c692bc7
JB		 4692012-08-07 Jan Beulich <jbeulich@suse.com>
470
471 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
472
de882298
RM		 4732012-08-06 Roland McGrath <mcgrathr@google.com>
474
475 * i386-dis.c (print_insn): Print spaces between multiple excess
476 prefixes. Return actual number of excess prefixes consumed,
477 not always one.
478
479 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
480
7bb15c6f
RM		 4812012-08-06 Roland McGrath <mcgrathr@google.com>
482 Victor Khimenko <khim@google.com>
483 H.J. Lu <hongjiu.lu@intel.com>
484
485 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
486 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
487 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
488 (OP_E_register): Likewise.
489 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
490
3843081d
JBG		 4912012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
492
493 * configure.in: Formatting.
494 * configure: Regenerate.
495
48891606
AM		 4962012-08-01 Alan Modra <amodra@gmail.com>
497
498 * h8300-dis.c: Fix printf arg warnings.
499 * i960-dis.c: Likewise.
500 * mips-dis.c: Likewise.
501 * pdp11-dis.c: Likewise.
502 * sh-dis.c: Likewise.
503 * v850-dis.c: Likewise.
504 * configure.in: Formatting.
505 * configure: Regenerate.
506 * rl78-decode.c: Regenerate.
507 * po/POTFILES.in: Regenerate.
508
03f66e8a 5092012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 510 Catherine Moore <clm@codesourcery.com>
511 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 512
513 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
514 (DSP_VOLA): Likewise.
515 (D32, D33): Likewise.
516 (micromips_opcodes): Add DSP ASE instructions.
48891606 517 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 518 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
519
94948e64
JB		 5202012-07-31 Jan Beulich <jbeulich@suse.com>
521
522 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
523 instruction group. Mark as requiring AVX2.
524 * i386-tbl.h: Re-generate.
525
a6dc81d2
NC		 5262012-07-30 Nick Clifton <nickc@redhat.com>
527
528 * po/opcodes.pot: Updated template.
529 * po/es.po: Updated Spanish translation.
530 * po/fi.po: Updated Finnish translation.
531
c4dd807e
MF		 5322012-07-27 Mike Frysinger <vapier@gentoo.org>
533
534 * configure.in (BFD_VERSION): Run bfd/configure --version and
535 parse the output of that.
536 * configure: Regenerate.
537
03edbe3b
JL		 5382012-07-25 James Lemke <jwlemke@codesourcery.com>
539
540 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
541
63d08c68
NC		 5422012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
543 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 544
545 PR binutils/13135
546 * arm-dis.c: Add necessary casts for printing integer values.
547 Use %s when printing string values.
548 * hppa-dis.c: Likewise.
549 * m68k-dis.c: Likewise.
550 * microblaze-dis.c: Likewise.
551 * mips-dis.c: Likewise.
552 * sparc-dis.c: Likewise.
553
ff688e1f
L		 5542012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
555
556 PR binutils/14355
557 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
558 (VEX_LEN_0FXOP_08_CD): Likewise.
559 (VEX_LEN_0FXOP_08_CE): Likewise.
560 (VEX_LEN_0FXOP_08_CF): Likewise.
561 (VEX_LEN_0FXOP_08_EC): Likewise.
562 (VEX_LEN_0FXOP_08_ED): Likewise.
563 (VEX_LEN_0FXOP_08_EE): Likewise.
564 (VEX_LEN_0FXOP_08_EF): Likewise.
565 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
566 vpcomub, vpcomuw, vpcomud, vpcomuq.
567 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
568 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
569 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
570 VEX_LEN_0FXOP_08_EF.
571
e2e1fcde
L		 5722012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
573
574 * i386-dis.c (PREFIX_0F38F6): New.
575 (prefix_table): Add adcx, adox instructions.
576 (three_byte_table): Use PREFIX_0F38F6.
577 (mod_table): Add rdseed instruction.
578 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
579 (cpu_flags): Likewise.
580 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
581 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
582 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
583 prefetchw.
584 * i386-tbl.h: Regenerate.
585 * i386-init.h: Likewise.
586
8b99bf0b
TS		 5872012-07-05 Thomas Schwinge <thomas@codesourcery.com>
588
f4263ca2 589 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 590
416cf80a
SK		 5912012-07-05 Sean Keys <skeys@ipdatasys.com>
592
593 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 594 always be false due to overlapping operand masks.
595 * xgate-opc.c: Corrected 'com' opcode entry and
596 fixed spacing.
416cf80a 597
9fa0f14a
RM		 5982012-07-02 Roland McGrath <mcgrathr@google.com>
599
600 * i386-opc.tbl: Add RepPrefixOk to nop.
601 * i386-tbl.h: Regenerate.
602
4c6a93d3
NC		 6032012-06-28 Nick Clifton <nickc@redhat.com>
604
605 * po/vi.po: Updated Vietnamese translation.
606
29c048b6
RM		 6072012-06-22 Roland McGrath <mcgrathr@google.com>
608
fe13e45b
RM		 609 * i386-opc.tbl: Add RepPrefixOk to ret.
610 * i386-tbl.h: Regenerate.
611
29c048b6
RM		 612 * i386-opc.h (RepPrefixOk): New enum constant.
613 (i386_opcode_modifier): New bitfield 'repprefixok'.
614 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
615 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
616 instructions that have IsString.
617 * i386-tbl.h: Regenerate.
618
c7a8dbf9
AS		 6192012-06-11 Andreas Schwab <schwab@linux-m68k.org>
620
621 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
622 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
623 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
624 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
625 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
626 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
627 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
628 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
629 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
630
94caa966
AM		 6312012-05-19 Alan Modra <amodra@gmail.com>
632
633 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
634 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
635
5eb3690e
AM		 6362012-05-18 Alan Modra <amodra@gmail.com>
637
71fe7bab
AM		 638 * ia64-opc.c: Remove #include "ansidecl.h".
639 * z8kgen.c: Include sysdep.h first.
640
5eb3690e
AM		 641 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
642 * bfin-dis.c: Likewise.
643 * i860-dis.c: Likewise.
644 * ia64-dis.c: Likewise.
645 * ia64-gen.c: Likewise.
646 * m68hc11-dis.c: Likewise.
647 * mmix-dis.c: Likewise.
648 * msp430-dis.c: Likewise.
649 * or32-dis.c: Likewise.
650 * rl78-dis.c: Likewise.
651 * rx-dis.c: Likewise.
652 * tic4x-dis.c: Likewise.
653 * tilegx-opc.c: Likewise.
654 * tilepro-opc.c: Likewise.
655 * rx-decode.c: Regenerate.
656
a4ebc835
AM		 6572012-05-17 James Lemke <jwlemke@codesourcery.com>
658
659 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
660
98c76446
AM		 6612012-05-17 James Lemke <jwlemke@codesourcery.com>
662
663 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
664
df7b86aa
NC		 6652012-05-17 Daniel Richard G. <skunk@iskunk.org>
666 Nick Clifton <nickc@redhat.com>
667
668 PR 14072
669 * configure.in: Add check that sysdep.h has been included before
670 any system header files.
671 * configure: Regenerate.
672 * config.in: Regenerate.
673 * sysdep.h: Generate an error if included before config.h.
674 * alpha-opc.c: Include sysdep.h before any other header file.
675 * alpha-dis.c: Likewise.
676 * avr-dis.c: Likewise.
677 * cgen-opc.c: Likewise.
678 * cr16-dis.c: Likewise.
679 * cris-dis.c: Likewise.
680 * crx-dis.c: Likewise.
681 * d10v-dis.c: Likewise.
682 * d10v-opc.c: Likewise.
683 * d30v-dis.c: Likewise.
684 * d30v-opc.c: Likewise.
685 * h8500-dis.c: Likewise.
686 * i370-dis.c: Likewise.
687 * i370-opc.c: Likewise.
688 * m10200-dis.c: Likewise.
689 * m10300-dis.c: Likewise.
690 * micromips-opc.c: Likewise.
691 * mips-opc.c: Likewise.
692 * mips61-opc.c: Likewise.
693 * moxie-dis.c: Likewise.
694 * or32-opc.c: Likewise.
695 * pj-dis.c: Likewise.
696 * ppc-dis.c: Likewise.
697 * ppc-opc.c: Likewise.
698 * s390-dis.c: Likewise.
699 * sh-dis.c: Likewise.
700 * sh64-dis.c: Likewise.
701 * sparc-dis.c: Likewise.
702 * sparc-opc.c: Likewise.
703 * spu-dis.c: Likewise.
704 * tic30-dis.c: Likewise.
705 * tic54x-dis.c: Likewise.
706 * tic80-dis.c: Likewise.
707 * tic80-opc.c: Likewise.
708 * tilegx-dis.c: Likewise.
709 * tilepro-dis.c: Likewise.
710 * v850-dis.c: Likewise.
711 * v850-opc.c: Likewise.
712 * vax-dis.c: Likewise.
713 * w65-dis.c: Likewise.
714 * xgate-dis.c: Likewise.
715 * xtensa-dis.c: Likewise.
716 * rl78-decode.opc: Likewise.
717 * rl78-decode.c: Regenerate.
718 * rx-decode.opc: Likewise.
719 * rx-decode.c: Regenerate.
720
e1dad58d
AM		 7212012-05-17 Alan Modra <amodra@gmail.com>
722
723 * ppc_dis.c: Don't include elf/ppc.h.
724
101af531
NC		 7252012-05-16 Meador Inge <meadori@codesourcery.com>
726
727 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
728 to PUSH/POP {reg}.
729
6927f982
NC		 7302012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
731 Stephane Carrez <stcarrez@nerim.fr>
732
733 * configure.in: Add S12X and XGATE co-processor support to m68hc11
734 target.
735 * disassemble.c: Likewise.
736 * configure: Regenerate.
737 * m68hc11-dis.c: Make objdump output more consistent, use hex
738 instead of decimal and use 0x prefix for hex.
739 * m68hc11-opc.c: Add S12X and XGATE opcodes.
740
b9c361e0
JL		 7412012-05-14 James Lemke <jwlemke@codesourcery.com>
742
743 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
744 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
745 (vle_opcd_indices): New array.
746 (lookup_vle): New function.
747 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
748 (print_insn_powerpc): Likewise.
749 * ppc-opc.c: Likewise.
750
7512012-05-14 Catherine Moore <clm@codesourcery.com>
752 Maciej W. Rozycki <macro@codesourcery.com>
753 Rhonda Wittels <rhonda@codesourcery.com>
754 Nathan Froyd <froydnj@codesourcery.com>
755
756 * ppc-opc.c (insert_arx, extract_arx): New functions.
757 (insert_ary, extract_ary): New functions.
758 (insert_li20, extract_li20): New functions.
759 (insert_rx, extract_rx): New functions.
760 (insert_ry, extract_ry): New functions.
761 (insert_sci8, extract_sci8): New functions.
762 (insert_sci8n, extract_sci8n): New functions.
763 (insert_sd4h, extract_sd4h): New functions.
764 (insert_sd4w, extract_sd4w): New functions.
765 (insert_vlesi, extract_vlesi): New functions.
766 (insert_vlensi, extract_vlensi): New functions.
767 (insert_vleui, extract_vleui): New functions.
768 (insert_vleil, extract_vleil): New functions.
769 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
770 (BI16, BI32, BO32, B8): New.
771 (B15, B24, CRD32, CRS): New.
772 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
773 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
774 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
775 (SH6_MASK): Use PPC_OPSHIFT_INV.
776 (SI8, UI5, OIMM5, UI7, BO16): New.
777 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
778 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
779 (ALLOW8_SPRG): New.
780 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
781 (OPVUP, OPVUP_MASK OPVUP): New
782 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
783 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
784 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
785 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
786 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
787 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
788 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
789 (SE_IM5, SE_IM5_MASK): New.
790 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
791 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
792 (BO32DNZ, BO32DZ): New.
793 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
794 (PPCVLE): New.
795 (powerpc_opcodes): Add new VLE instructions. Update existing
796 instruction to include PPCVLE if supported.
797 * ppc-dis.c (ppc_opts): Add vle entry.
798 (get_powerpc_dialect): New function.
799 (powerpc_init_dialect): VLE support.
800 (print_insn_big_powerpc): Call get_powerpc_dialect.
801 (print_insn_little_powerpc): Likewise.
802 (operand_value_powerpc): Handle negative shift counts.
803 (print_insn_powerpc): Handle 2-byte instruction lengths.
804
208a4923
NC		 8052012-05-11 Daniel Richard G. <skunk@iskunk.org>
806
807 PR binutils/14028
808 * configure.in: Invoke ACX_HEADER_STRING.
809 * configure: Regenerate.
810 * config.in: Regenerate.
811 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
812 string.h and strings.h.
813
6750a3a7
NC		 8142012-05-11 Nick Clifton <nickc@redhat.com>
815
816 PR binutils/14006
817 * arm-dis.c (print_insn): Fix detection of instruction mode in
818 files containing multiple executable sections.
819
f6c1a2d5
NC		 8202012-05-03 Sean Keys <skeys@ipdatasys.com>
821
822 * Makefile.in, configure: regenerate
823 * disassemble.c (disassembler): Recognize ARCH_XGATE.
824 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
825 New functions.
826 * configure.in: Recognize xgate.
827 * xgate-dis.c, xgate-opc.c: New files for support of xgate
828 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
829 and opcode generation for xgate.
830
78e98aab
DD		 8312012-04-30 DJ Delorie <dj@redhat.com>
832
833 * rx-decode.opc (MOV): Do not sign-extend immediates which are
834 already the maximum bit size.
835 * rx-decode.c: Regenerate.
836
ec668d69
DM		 8372012-04-27 David S. Miller <davem@davemloft.net>
838
2e52845b
DM		 839 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
840 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
841
58004e23
DM		 842 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
843 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
844
698544e1
DM		 845 * sparc-opc.c (CBCOND): New define.
846 (CBCOND_XCC): Likewise.
847 (cbcond): New helper macro.
848 (sparc_opcodes): Add compare-and-branch instructions.
849
6cda1326
DM		 850 * sparc-dis.c (print_insn_sparc): Handle ')'.
851 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
852
ec668d69
DM		 853 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
854 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
855
2615994e
DM		 8562012-04-12 David S. Miller <davem@davemloft.net>
857
858 * sparc-dis.c (X_DISP10): Define.
859 (print_insn_sparc): Handle '='.
860
5de10af0
MF		 8612012-04-01 Mike Frysinger <vapier@gentoo.org>
862
863 * bfin-dis.c (fmtconst): Replace decimal handling with a single
864 sprintf call and the '*' field width.
865
55a36193
MK		 8662012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
867
868 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
869
d6688282
AM		 8702012-03-16 Alan Modra <amodra@gmail.com>
871
872 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
873 (powerpc_opcd_indices): Bump array size.
874 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
875 corresponding to unused opcodes to following entry.
876 (lookup_powerpc): New function, extracted and optimised from..
877 (print_insn_powerpc): ..here.
878
b240011a
AM		 8792012-03-15 Alan Modra <amodra@gmail.com>
880 James Lemke <jwlemke@codesourcery.com>
881
882 * disassemble.c (disassemble_init_for_target): Handle ppc init.
883 * ppc-dis.c (private): New var.
884 (powerpc_init_dialect): Don't return calloc failure, instead use
885 private.
886 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
887 (powerpc_opcd_indices): New array.
888 (disassemble_init_powerpc): New function.
889 (print_insn_big_powerpc): Don't init dialect here.
890 (print_insn_little_powerpc): Likewise.
891 (print_insn_powerpc): Start search using powerpc_opcd_indices.
892
aea77599
AM		 8932012-03-10 Edmar Wienskoski <edmar@freescale.com>
894
895 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
896 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
897 (PPCVEC2, PPCTMR, E6500): New short names.
898 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
899 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
900 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
901 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
902 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
903 optional operands on sync instruction for E6500 target.
904
5333187a
AK		 9052012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
906
907 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
908
a597d2d3
AM		 9092012-02-27 Alan Modra <amodra@gmail.com>
910
911 * mt-dis.c: Regenerate.
912
3f26eb3a
AM		 9132012-02-27 Alan Modra <amodra@gmail.com>
914
915 * v850-opc.c (extract_v8): Rearrange to make it obvious this
916 is the inverse of corresponding insert function.
917 (extract_d22, extract_u9, extract_r4): Likewise.
918 (extract_d9): Correct sign extension.
919 (extract_d16_15): Don't assume "long" is 32 bits, and don't
920 rely on implementation defined behaviour for shift right of
921 signed types.
922 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
923 (extract_d23): Likewise, and correct mask.
924
1f42f8b3
AM		 9252012-02-27 Alan Modra <amodra@gmail.com>
926
927 * crx-dis.c (print_arg): Mask constant to 32 bits.
928 * crx-opc.c (cst4_map): Use int array.
929
cdb06235
AM		 9302012-02-27 Alan Modra <amodra@gmail.com>
931
932 * arc-dis.c (BITS): Don't use shifts to mask off bits.
933 (FIELDD): Sign extend with xor,sub.
934
6f7be959
WL		 9352012-02-25 Walter Lee <walt@tilera.com>
936
937 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
938 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
939 TILEPRO_OPC_LW_TLS_SN.
940
82c2def5
L		 9412012-02-21 H.J. Lu <hongjiu.lu@intel.com>
942
943 * i386-opc.h (HLEPrefixNone): New.
944 (HLEPrefixLock): Likewise.
945 (HLEPrefixAny): Likewise.
946 (HLEPrefixRelease): Likewise.
947
42164a71
L		 9482012-02-08 H.J. Lu <hongjiu.lu@intel.com>
949
950 * i386-dis.c (HLE_Fixup1): New.
951 (HLE_Fixup2): Likewise.
952 (HLE_Fixup3): Likewise.
953 (Ebh1): Likewise.
954 (Evh1): Likewise.
955 (Ebh2): Likewise.
956 (Evh2): Likewise.
957 (Ebh3): Likewise.
958 (Evh3): Likewise.
959 (MOD_C6_REG_7): Likewise.
960 (MOD_C7_REG_7): Likewise.
961 (RM_C6_REG_7): Likewise.
962 (RM_C7_REG_7): Likewise.
963 (XACQUIRE_PREFIX): Likewise.
964 (XRELEASE_PREFIX): Likewise.
965 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
966 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
967 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
968 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
969 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
970 MOD_C6_REG_7 and MOD_C7_REG_7.
971 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
972 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
973 xtest.
974 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
975 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
976
977 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
978 CPU_RTM_FLAGS.
979 (cpu_flags): Add CpuHLE and CpuRTM.
980 (opcode_modifiers): Add HLEPrefixOk.
981
982 * i386-opc.h (CpuHLE): New.
983 (CpuRTM): Likewise.
984 (HLEPrefixOk): Likewise.
985 (i386_cpu_flags): Add cpuhle and cpurtm.
986 (i386_opcode_modifier): Add hleprefixok.
987
988 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
989 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
990 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
991 operand. Add xacquire, xrelease, xabort, xbegin, xend and
992 xtest.
993 * i386-init.h: Regenerated.
994 * i386-tbl.h: Likewise.
995
21abe33a
DD		 9962012-01-24 DJ Delorie <dj@redhat.com>
997
998 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
999 * rl78-decode.c: Regenerate.
1000
e20cc039
AM		 10012012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
1002
1003 PR binutils/10173
1004 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
1005
e143d25c
AS		 10062012-01-17 Andreas Schwab <schwab@linux-m68k.org>
1007
1008 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
1009 register and move them after pmove with PSR/PCSR register.
1010
8729a6f6
L		 10112012-01-13 H.J. Lu <hongjiu.lu@intel.com>
1012
1013 * i386-dis.c (mod_table): Add vmfunc.
1014
1015 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
1016 (cpu_flags): CpuVMFUNC.
1017
1018 * i386-opc.h (CpuVMFUNC): New.
1019 (i386_cpu_flags): Add cpuvmfunc.
1020
1021 * i386-opc.tbl: Add vmfunc.
1022 * i386-init.h: Regenerated.
1023 * i386-tbl.h: Likewise.
5011093d 1024
23e1d329 1025For older changes see ChangeLog-2011
252b5132
RH		 1026\f
1027Local Variables:
2f6d2f85
NC		 1028mode: change-log
1029left-margin: 8
1030fill-column: 74
252b5132
RH		 1031version-control: never
1032End:
GDB Binutils - Deliverables
This page took 0.632956 seconds and 4 git commands to generate.