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220abb21
AM		 12005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
2
3 * vax-dis.c (entry_mask_bit): New array.
4 (print_insn_vax): Decode function entry mask.
5
0e06657a
AH		 62005-03-07 Aldy Hernandez <aldyh@redhat.com>
7
8 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
9
06647dfd
AM		 102005-03-05 Alan Modra <amodra@bigpond.net.au>
11
12 * po/opcodes.pot: Regenerate.
13
82b829a7
RR		 142005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
15
220abb21 16 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 17 (dsmOneArcInst): Use the enum values for the decoding class.
18 Remove redundant case in the switch for decodingClass value 11.
82b829a7 19
c4a530c5
JB		 202005-03-02 Jan Beulich <jbeulich@novell.com>
21
22 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
23 accesses.
24 (OP_C): Consider lock prefix in non-64-bit modes.
25
47d8304e
AM		 262005-02-24 Alan Modra <amodra@bigpond.net.au>
27
28 * cris-dis.c (format_hex): Remove ineffective warning fix.
29 * crx-dis.c (make_instruction): Warning fix.
30 * frv-asm.c: Regenerate.
31
ec36c4a4
NC		 322005-02-23 Nick Clifton <nickc@redhat.com>
33
33b71eeb
NC		 34 * cgen-dis.in: Use bfd_byte for buffers that are passed to
35 read_memory.
06647dfd 36
33b71eeb 37 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 38
ec36c4a4
NC		 39 * crx-dis.c (make_instruction): Move argument structure into inner
40 scope and ensure that all of its fields are initialised before
41 they are used.
42
33b71eeb
NC		 43 * fr30-asm.c: Regenerate.
44 * fr30-dis.c: Regenerate.
45 * frv-asm.c: Regenerate.
46 * frv-dis.c: Regenerate.
47 * ip2k-asm.c: Regenerate.
48 * ip2k-dis.c: Regenerate.
49 * iq2000-asm.c: Regenerate.
50 * iq2000-dis.c: Regenerate.
51 * m32r-asm.c: Regenerate.
52 * m32r-dis.c: Regenerate.
53 * openrisc-asm.c: Regenerate.
54 * openrisc-dis.c: Regenerate.
55 * xstormy16-asm.c: Regenerate.
56 * xstormy16-dis.c: Regenerate.
57
53c9ebc5
AM		 582005-02-22 Alan Modra <amodra@bigpond.net.au>
59
60 * arc-ext.c: Warning fixes.
61 * arc-ext.h: Likewise.
62 * cgen-opc.c: Likewise.
63 * ia64-gen.c: Likewise.
64 * maxq-dis.c: Likewise.
65 * ns32k-dis.c: Likewise.
66 * w65-dis.c: Likewise.
67 * ia64-asmtab.c: Regenerate.
68
610ad19b
AM		 692005-02-22 Alan Modra <amodra@bigpond.net.au>
70
71 * fr30-desc.c: Regenerate.
72 * fr30-desc.h: Regenerate.
73 * fr30-opc.c: Regenerate.
74 * fr30-opc.h: Regenerate.
75 * frv-desc.c: Regenerate.
76 * frv-desc.h: Regenerate.
77 * frv-opc.c: Regenerate.
78 * frv-opc.h: Regenerate.
79 * ip2k-desc.c: Regenerate.
80 * ip2k-desc.h: Regenerate.
81 * ip2k-opc.c: Regenerate.
82 * ip2k-opc.h: Regenerate.
83 * iq2000-desc.c: Regenerate.
84 * iq2000-desc.h: Regenerate.
85 * iq2000-opc.c: Regenerate.
86 * iq2000-opc.h: Regenerate.
87 * m32r-desc.c: Regenerate.
88 * m32r-desc.h: Regenerate.
89 * m32r-opc.c: Regenerate.
90 * m32r-opc.h: Regenerate.
91 * m32r-opinst.c: Regenerate.
92 * openrisc-desc.c: Regenerate.
93 * openrisc-desc.h: Regenerate.
94 * openrisc-opc.c: Regenerate.
95 * openrisc-opc.h: Regenerate.
96 * xstormy16-desc.c: Regenerate.
97 * xstormy16-desc.h: Regenerate.
98 * xstormy16-opc.c: Regenerate.
99 * xstormy16-opc.h: Regenerate.
100
db9db6f2
AM		 1012005-02-21 Alan Modra <amodra@bigpond.net.au>
102
103 * Makefile.am: Run "make dep-am"
104 * Makefile.in: Regenerate.
105
bf143b25
NC		 1062005-02-15 Nick Clifton <nickc@redhat.com>
107
108 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
109 compile time warnings.
110 (print_keyword): Likewise.
111 (default_print_insn): Likewise.
112
113 * fr30-desc.c: Regenerated.
114 * fr30-desc.h: Regenerated.
115 * fr30-dis.c: Regenerated.
116 * fr30-opc.c: Regenerated.
117 * fr30-opc.h: Regenerated.
118 * frv-desc.c: Regenerated.
119 * frv-dis.c: Regenerated.
120 * frv-opc.c: Regenerated.
121 * ip2k-asm.c: Regenerated.
122 * ip2k-desc.c: Regenerated.
123 * ip2k-desc.h: Regenerated.
124 * ip2k-dis.c: Regenerated.
125 * ip2k-opc.c: Regenerated.
126 * ip2k-opc.h: Regenerated.
127 * iq2000-desc.c: Regenerated.
128 * iq2000-dis.c: Regenerated.
129 * iq2000-opc.c: Regenerated.
130 * m32r-asm.c: Regenerated.
131 * m32r-desc.c: Regenerated.
132 * m32r-desc.h: Regenerated.
133 * m32r-dis.c: Regenerated.
134 * m32r-opc.c: Regenerated.
135 * m32r-opc.h: Regenerated.
136 * m32r-opinst.c: Regenerated.
137 * openrisc-desc.c: Regenerated.
138 * openrisc-desc.h: Regenerated.
139 * openrisc-dis.c: Regenerated.
140 * openrisc-opc.c: Regenerated.
141 * openrisc-opc.h: Regenerated.
142 * xstormy16-desc.c: Regenerated.
143 * xstormy16-desc.h: Regenerated.
144 * xstormy16-dis.c: Regenerated.
145 * xstormy16-opc.c: Regenerated.
146 * xstormy16-opc.h: Regenerated.
147
d6098898
L		 1482005-02-14 H.J. Lu <hongjiu.lu@intel.com>
149
150 * dis-buf.c (perror_memory): Use sprintf_vma to print out
151 address.
152
5a84f3e0
NC		 1532005-02-11 Nick Clifton <nickc@redhat.com>
154
bc18c937
NC		 155 * iq2000-asm.c: Regenerate.
156
5a84f3e0
NC		 157 * frv-dis.c: Regenerate.
158
0a40490e
JB		 1592005-02-07 Jim Blandy <jimb@redhat.com>
160
161 * Makefile.am (CGEN): Load guile.scm before calling the main
162 application script.
163 * Makefile.in: Regenerated.
164 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
165 Simply pass the cgen-opc.scm path to ${cgen} as its first
166 argument; ${cgen} itself now contains the '-s', or whatever is
167 appropriate for the Scheme being used.
168
c46f8c51
AC		 1692005-01-31 Andrew Cagney <cagney@gnu.org>
170
171 * configure: Regenerate to track ../gettext.m4.
172
60b9a617
JB		 1732005-01-31 Jan Beulich <jbeulich@novell.com>
174
175 * ia64-gen.c (NELEMS): Define.
176 (shrink): Generate alias with missing second predicate register when
177 opcode has two outputs and these are both predicates.
178 * ia64-opc-i.c (FULL17): Define.
179 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
180 here to generate output template.
181 (TBITCM, TNATCM): Undefine after use.
182 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
183 first input. Add ld16 aliases without ar.csd as second output. Add
184 st16 aliases without ar.csd as second input. Add cmpxchg aliases
185 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
186 ar.ccv as third/fourth inputs. Consolidate through...
187 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
188 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
189 * ia64-asmtab.c: Regenerate.
190
a53bf506
AC		 1912005-01-27 Andrew Cagney <cagney@gnu.org>
192
193 * configure: Regenerate to track ../gettext.m4 change.
194
90219bd0
AO		 1952005-01-25 Alexandre Oliva <aoliva@redhat.com>
196
197 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
198 * frv-asm.c: Rebuilt.
199 * frv-desc.c: Rebuilt.
200 * frv-desc.h: Rebuilt.
201 * frv-dis.c: Rebuilt.
202 * frv-ibld.c: Rebuilt.
203 * frv-opc.c: Rebuilt.
204 * frv-opc.h: Rebuilt.
205
45181ed1
AC		 2062005-01-24 Andrew Cagney <cagney@gnu.org>
207
208 * configure: Regenerate, ../gettext.m4 was updated.
209
9e836e3d
FF		 2102005-01-21 Fred Fish <fnf@specifixinc.com>
211
212 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
213 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
214 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
215 * mips-dis.c: Ditto.
216
5e8cb021
AM		 2172005-01-20 Alan Modra <amodra@bigpond.net.au>
218
219 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
220
986e18a5
FF		 2212005-01-19 Fred Fish <fnf@specifixinc.com>
222
223 * mips-dis.c (no_aliases): New disassembly option flag.
224 (set_default_mips_dis_options): Init no_aliases to zero.
225 (parse_mips_dis_option): Handle no-aliases option.
226 (print_insn_mips): Ignore table entries that are aliases
227 if no_aliases is set.
228 (print_insn_mips16): Ditto.
229 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
230 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
231 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
232 * mips16-opc.c (mips16_opcodes): Ditto.
233
e38bc3b5
NC		 2342005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
235
236 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
237 (inheritance diagram): Add missing edge.
238 (arch_sh1_up): Rename arch_sh_up to match external name to make life
239 easier for the testsuite.
240 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
241 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 242 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 243 arch_sh2a_or_sh4_up child.
244 (sh_table): Do renaming as above.
245 Correct comment for ldc.l for gas testsuite to read.
246 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
247 Correct comments for movy.w and movy.l for gas testsuite to read.
248 Correct comments for fmov.d and fmov.s for gas testsuite to read.
249
9df48ba9
L		 2502005-01-12 H.J. Lu <hongjiu.lu@intel.com>
251
252 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
253
2033b4b9
L		 2542005-01-12 H.J. Lu <hongjiu.lu@intel.com>
255
256 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
257
0bcb06d2
AS		 2582005-01-10 Andreas Schwab <schwab@suse.de>
259
260 * disassemble.c (disassemble_init_for_target) <case
261 bfd_arch_ia64>: Set skip_zeroes to 16.
262 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
263
47add74d
TL		 2642004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
265
266 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
267
246f4c05
SS		 2682004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
269
270 * avr-dis.c: Prettyprint. Added printing of symbol names in all
271 memory references. Convert avr_operand() to C90 formatting.
272
0e1200e5
TL		 2732004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
274
275 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
276
89a649f7
TL		 2772004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
278
279 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
280 (no_op_insn): Initialize array with instructions that have no
281 operands.
282 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
283
6255809c
RE		 2842004-11-29 Richard Earnshaw <rearnsha@arm.com>
285
286 * arm-dis.c: Correct top-level comment.
287
2fbad815
RE		 2882004-11-27 Richard Earnshaw <rearnsha@arm.com>
289
290 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
291 architecuture defining the insn.
292 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 293 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
294 field.
2fbad815
RE		 295 Also include opcode/arm.h.
296 * Makefile.am (arm-dis.lo): Update dependency list.
297 * Makefile.in: Regenerate.
298
d81acc42
NC		 2992004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
300
301 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
302 reflect the change to the short immediate syntax.
303
ca4f2377
AM		 3042004-11-19 Alan Modra <amodra@bigpond.net.au>
305
5da8bf1b
AM		 306 * or32-opc.c (debug): Warning fix.
307 * po/POTFILES.in: Regenerate.
308
ca4f2377
AM		 309 * maxq-dis.c: Formatting.
310 (print_insn): Warning fix.
311
b7693d02
DJ		 3122004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
313
314 * arm-dis.c (WORD_ADDRESS): Define.
315 (print_insn): Use it. Correct big-endian end-of-section handling.
316
300dac7e
NC		 3172004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
318 Vineet Sharma <vineets@noida.hcltech.com>
319
320 * maxq-dis.c: New file.
321 * disassemble.c (ARCH_maxq): Define.
610ad19b 322 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 323 instructions..
324 * configure.in: Add case for bfd_maxq_arch.
325 * configure: Regenerate.
326 * Makefile.am: Add support for maxq-dis.c
327 * Makefile.in: Regenerate.
328 * aclocal.m4: Regenerate.
329
42048ee7
TL		 3302004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
331
332 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
333 mode.
334 * crx-dis.c: Likewise.
335
bd21e58e
HPN		 3362004-11-04 Hans-Peter Nilsson <hp@axis.com>
337
338 Generally, handle CRISv32.
339 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
340 (struct cris_disasm_data): New type.
341 (format_reg, format_hex, cris_constraint, print_flags)
342 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
343 callers changed.
344 (format_sup_reg, print_insn_crisv32_with_register_prefix)
345 (print_insn_crisv32_without_register_prefix)
346 (print_insn_crisv10_v32_with_register_prefix)
347 (print_insn_crisv10_v32_without_register_prefix)
348 (cris_parse_disassembler_options): New functions.
349 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
350 parameter. All callers changed.
351 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
352 failure.
353 (cris_constraint) <case 'Y', 'U'>: New cases.
354 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
355 for constraint 'n'.
356 (print_with_operands) <case 'Y'>: New case.
357 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
358 <case 'N', 'Y', 'Q'>: New cases.
359 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
360 (print_insn_cris_with_register_prefix)
361 (print_insn_cris_without_register_prefix): Call
362 cris_parse_disassembler_options.
363 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
364 for CRISv32 and the size of immediate operands. New v32-only
365 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
366 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
367 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
368 Change brp to be v3..v10.
369 (cris_support_regs): New vector.
370 (cris_opcodes): Update head comment. New format characters '[',
371 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
372 Add new opcodes for v32 and adjust existing opcodes to accommodate
373 differences to earlier variants.
374 (cris_cond15s): New vector.
375
9306ca4a
JB		 3762004-11-04 Jan Beulich <jbeulich@novell.com>
377
378 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
379 (indirEb): Remove.
380 (Mp): Use f_mode rather than none at all.
381 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
382 replaces what previously was x_mode; x_mode now means 128-bit SSE
383 operands.
384 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
385 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
386 pinsrw's second operand is Edqw.
387 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
388 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
389 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
390 mode when an operand size override is present or always suffixing.
391 More instructions will need to be added to this group.
392 (putop): Handle new macro chars 'C' (short/long suffix selector),
393 'I' (Intel mode override for following macro char), and 'J' (for
394 adding the 'l' prefix to far branches in AT&T mode). When an
395 alternative was specified in the template, honor macro character when
396 specified for Intel mode.
397 (OP_E): Handle new *_mode values. Correct pointer specifications for
398 memory operands. Consolidate output of index register.
399 (OP_G): Handle new *_mode values.
400 (OP_I): Handle const_1_mode.
401 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
402 respective opcode prefix bits have been consumed.
403 (OP_EM, OP_EX): Provide some default handling for generating pointer
404 specifications.
405
f39c96a9
TL		 4062004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
407
408 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
409 COP_INST macro.
410
812337be
TL		 4112004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
412
413 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
414 (getregliststring): Support HI/LO and user registers.
610ad19b 415 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 416 rearrangement done in CRX opcode header file.
417 (crx_regtab): Likewise.
418 (crx_optab): Likewise.
610ad19b 419 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 420 formats.
421 support new Co-Processor instruction 'cpi'.
422
4030fa5a
NC		 4232004-10-27 Nick Clifton <nickc@redhat.com>
424
425 * opcodes/iq2000-asm.c: Regenerate.
426 * opcodes/iq2000-desc.c: Regenerate.
427 * opcodes/iq2000-desc.h: Regenerate.
428 * opcodes/iq2000-dis.c: Regenerate.
429 * opcodes/iq2000-ibld.c: Regenerate.
430 * opcodes/iq2000-opc.c: Regenerate.
431 * opcodes/iq2000-opc.h: Regenerate.
432
fc3d45e8
TL		 4332004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
434
435 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
436 us4, us5 (respectively).
437 Remove unsupported 'popa' instruction.
438 Reverse operands order in store co-processor instructions.
439
3c55da70
AM		 4402004-10-15 Alan Modra <amodra@bigpond.net.au>
441
442 * Makefile.am: Run "make dep-am"
443 * Makefile.in: Regenerate.
444
7fa3d080
BW		 4452004-10-12 Bob Wilson <bob.wilson@acm.org>
446
447 * xtensa-dis.c: Use ISO C90 formatting.
448
e612bb4d
AM		 4492004-10-09 Alan Modra <amodra@bigpond.net.au>
450
451 * ppc-opc.c: Revert 2004-09-09 change.
452
43cd72b9
BW		 4532004-10-07 Bob Wilson <bob.wilson@acm.org>
454
455 * xtensa-dis.c (state_names): Delete.
456 (fetch_data): Use xtensa_isa_maxlength.
457 (print_xtensa_operand): Replace operand parameter with opcode/operand
458 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
459 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
460 instruction bundles. Use xmalloc instead of malloc.
461
bbac1f2a
NC		 4622004-10-07 David Gibson <david@gibson.dropbear.id.au>
463
464 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
465 initializers.
466
48c9f030
NC		 4672004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
468
469 * crx-opc.c (crx_instruction): Support Co-processor insns.
470 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
471 (getregliststring): Change function to use the above enum.
472 (print_arg): Handle CO-Processor insns.
473 (crx_cinvs): Add 'b' option to invalidate the branch-target
474 cache.
475
12c64a4e
AH		 4762004-10-06 Aldy Hernandez <aldyh@redhat.com>
477
478 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
479 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
480 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
481 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
482 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
483
14127cc4
NC		 4842004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
485
486 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
487 rather than add it.
488
0dd132b6
NC		 4892004-09-30 Paul Brook <paul@codesourcery.com>
490
491 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
492 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
493
3f85e526
L		 4942004-09-17 H.J. Lu <hongjiu.lu@intel.com>
495
496 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
497 (CONFIG_STATUS_DEPENDENCIES): New.
498 (Makefile): Removed.
499 (config.status): Likewise.
500 * Makefile.in: Regenerated.
501
8ae85421
AM		 5022004-09-17 Alan Modra <amodra@bigpond.net.au>
503
504 * Makefile.am: Run "make dep-am".
505 * Makefile.in: Regenerate.
506 * aclocal.m4: Regenerate.
507 * configure: Regenerate.
508 * po/POTFILES.in: Regenerate.
509 * po/opcodes.pot: Regenerate.
510
24443139
AS		 5112004-09-11 Andreas Schwab <schwab@suse.de>
512
513 * configure: Rebuild.
514
2a309db0
AM		 5152004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
516
517 * ppc-opc.c (L): Make this field not optional.
518
42851540
NC		 5192004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
520
521 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
522 Fix parameter to 'm[t|f]csr' insns.
523
979273e3
NN		 5242004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
525
526 * configure.in: Autoupdate to autoconf 2.59.
527 * aclocal.m4: Rebuild with aclocal 1.4p6.
528 * configure: Rebuild with autoconf 2.59.
529 * Makefile.in: Rebuild with automake 1.4p6 (picking up
530 bfd changes for autoconf 2.59 on the way).
531 * config.in: Rebuild with autoheader 2.59.
532
ac28a1cb
RS		 5332004-08-27 Richard Sandiford <rsandifo@redhat.com>
534
535 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
536
30d1c836
ML		 5372004-07-30 Michal Ludvig <mludvig@suse.cz>
538
539 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
540 (GRPPADLCK2): New define.
541 (twobyte_has_modrm): True for 0xA6.
542 (grps): GRPPADLCK2 for opcode 0xA6.
543
0b0ac059
AO		 5442004-07-29 Alexandre Oliva <aoliva@redhat.com>
545
546 Introduce SH2a support.
547 * sh-opc.h (arch_sh2a_base): Renumber.
548 (arch_sh2a_nofpu_base): Remove.
549 (arch_sh_base_mask): Adjust.
550 (arch_opann_mask): New.
551 (arch_sh2a, arch_sh2a_nofpu): Adjust.
552 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
553 (sh_table): Adjust whitespace.
554 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
555 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
556 instruction list throughout.
557 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
558 of arch_sh2a in instruction list throughout.
559 (arch_sh2e_up): Accomodate above changes.
560 (arch_sh2_up): Ditto.
561 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
562 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
563 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
564 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
565 * sh-opc.h (arch_sh2a_nofpu): New.
566 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
567 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
568 instruction.
569 2004-01-20 DJ Delorie <dj@redhat.com>
570 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
571 2003-12-29 DJ Delorie <dj@redhat.com>
572 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
573 sh_opcode_info, sh_table): Add sh2a support.
574 (arch_op32): New, to tag 32-bit opcodes.
575 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
576 2003-12-02 Michael Snyder <msnyder@redhat.com>
577 * sh-opc.h (arch_sh2a): Add.
578 * sh-dis.c (arch_sh2a): Handle.
579 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
580
670ec21d
NC		 5812004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
582
583 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
584
ed049af3
NC		 5852004-07-22 Nick Clifton <nickc@redhat.com>
586
587 PR/280
588 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
589 insns - this is done by objdump itself.
590 * h8500-dis.c (print_insn_h8500): Likewise.
591
20f0a1fc
NC		 5922004-07-21 Jan Beulich <jbeulich@novell.com>
593
594 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
595 regardless of address size prefix in effect.
596 (ptr_reg): Size or address registers does not depend on rex64, but
597 on the presence of an address size override.
598 (OP_MMX): Use rex.x only for xmm registers.
599 (OP_EM): Use rex.z only for xmm registers.
600
6f14957b
MR		 6012004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
602
603 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
604 move/branch operations to the bottom so that VR5400 multimedia
605 instructions take precedence in disassembly.
606
1586d91e
MR		 6072004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
608
609 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
610 ISA-specific "break" encoding.
611
982de27a
NC		 6122004-07-13 Elvis Chiang <elvisfb@gmail.com>
613
614 * arm-opc.h: Fix typo in comment.
615
4300ab10
AS		 6162004-07-11 Andreas Schwab <schwab@suse.de>
617
618 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
619
8577e690
AS		 6202004-07-09 Andreas Schwab <schwab@suse.de>
621
622 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
623
1fe1f39c
NC		 6242004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
625
626 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
627 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
628 (crx-dis.lo): New target.
629 (crx-opc.lo): Likewise.
630 * Makefile.in: Regenerate.
631 * configure.in: Handle bfd_crx_arch.
632 * configure: Regenerate.
633 * crx-dis.c: New file.
634 * crx-opc.c: New file.
635 * disassemble.c (ARCH_crx): Define.
636 (disassembler): Handle ARCH_crx.
637
7a33b495
JW		 6382004-06-29 James E Wilson <wilson@specifixinc.com>
639
640 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
641 * ia64-asmtab.c: Regnerate.
642
98e69875
AM		 6432004-06-28 Alan Modra <amodra@bigpond.net.au>
644
645 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
646 (extract_fxm): Don't test dialect.
647 (XFXFXM_MASK): Include the power4 bit.
648 (XFXM): Add p4 param.
649 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
650
a53b85e2
AO		 6512004-06-27 Alexandre Oliva <aoliva@redhat.com>
652
653 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
654 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
655
d0618d1c
AM		 6562004-06-26 Alan Modra <amodra@bigpond.net.au>
657
658 * ppc-opc.c (BH, XLBH_MASK): Define.
659 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
660
1d9f512f
AM		 6612004-06-24 Alan Modra <amodra@bigpond.net.au>
662
663 * i386-dis.c (x_mode): Comment.
664 (two_source_ops): File scope.
665 (float_mem): Correct fisttpll and fistpll.
666 (float_mem_mode): New table.
667 (dofloat): Use it.
668 (OP_E): Correct intel mode PTR output.
669 (ptr_reg): Use open_char and close_char.
670 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
671 operands. Set two_source_ops.
672
52886d70
AM		 6732004-06-15 Alan Modra <amodra@bigpond.net.au>
674
675 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
676 instead of _raw_size.
677
bad9ceea
JJ		 6782004-06-08 Jakub Jelinek <jakub@redhat.com>
679
680 * ia64-gen.c (in_iclass): Handle more postinc st
681 and ld variants.
682 * ia64-asmtab.c: Rebuilt.
683
0451f5df
MS		 6842004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
685
686 * s390-opc.txt: Correct architecture mask for some opcodes.
687 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
688 in the esa mode as well.
689
f6f9408f
JR		 6902004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
691
692 * sh-dis.c (target_arch): Make unsigned.
693 (print_insn_sh): Replace (most of) switch with a call to
694 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
695 * sh-opc.h: Redefine architecture flags values.
696 Add sh3-nommu architecture.
697 Reorganise <arch>_up macros so they make more visual sense.
698 (SH_MERGE_ARCH_SET): Define new macro.
699 (SH_VALID_BASE_ARCH_SET): Likewise.
700 (SH_VALID_MMU_ARCH_SET): Likewise.
701 (SH_VALID_CO_ARCH_SET): Likewise.
702 (SH_VALID_ARCH_SET): Likewise.
703 (SH_MERGE_ARCH_SET_VALID): Likewise.
704 (SH_ARCH_SET_HAS_FPU): Likewise.
705 (SH_ARCH_SET_HAS_DSP): Likewise.
706 (SH_ARCH_UNKNOWN_ARCH): Likewise.
707 (sh_get_arch_from_bfd_mach): Add prototype.
708 (sh_get_arch_up_from_bfd_mach): Likewise.
709 (sh_get_bfd_mach_from_arch_set): Likewise.
710 (sh_merge_bfd_arc): Likewise.
711
be8c092b
NC		 7122004-05-24 Peter Barada <peter@the-baradas.com>
713
714 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 715 into new match_insn_m68k function. Loop over canidate
716 matches and select first that completely matches.
be8c092b
NC		 717 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
718 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 719 to verify addressing for MAC/EMAC.
be8c092b
NC		 720 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
721 reigster halves since 'fpu' and 'spl' look misleading.
722 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
723 * m68k-opc.c: Rearragne mac/emac cases to use longest for
724 first, tighten up match masks.
725 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
726 'size' from special case code in print_insn_m68k to
727 determine decode size of insns.
728
a30e9cc4
AM		 7292004-05-19 Alan Modra <amodra@bigpond.net.au>
730
731 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
732 well as when -mpower4.
733
9598fbe5
NC		 7342004-05-13 Nick Clifton <nickc@redhat.com>
735
736 * po/fr.po: Updated French translation.
737
6b6e92f4
NC		 7382004-05-05 Peter Barada <peter@the-baradas.com>
739
740 * m68k-dis.c(print_insn_m68k): Add new chips, use core
741 variants in arch_mask. Only set m68881/68851 for 68k chips.
742 * m68k-op.c: Switch from ColdFire chips to core variants.
743
a404d431
AM		 7442004-05-05 Alan Modra <amodra@bigpond.net.au>
745
a30e9cc4 746 PR 147.
a404d431
AM		 747 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
748
f3806e43
BE		 7492004-04-29 Ben Elliston <bje@au.ibm.com>
750
520ceea4
BE		 751 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
752 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 753
1f1799d5
KK		 7542004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
755
756 * sh-dis.c (print_insn_sh): Print the value in constant pool
757 as a symbol if it looks like a symbol.
758
fd99574b
NC		 7592004-04-22 Peter Barada <peter@the-baradas.com>
760
761 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
762 appropriate ColdFire architectures.
763 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
764 mask addressing.
765 Add EMAC instructions, fix MAC instructions. Remove
766 macmw/macml/msacmw/msacml instructions since mask addressing now
767 supported.
768
b4781d44
JJ		 7692004-04-20 Jakub Jelinek <jakub@redhat.com>
770
771 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
772 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
773 suffix. Use fmov*x macros, create all 3 fpsize variants in one
774 macro. Adjust all users.
775
91809fda 7762004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 777
91809fda
NC		 778 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
779 separately.
780
f4453dfa
NC		 7812004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
782
783 * m32r-asm.c: Regenerate.
784
9b0de91a
SS		 7852004-03-29 Stan Shebs <shebs@apple.com>
786
787 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
788 used.
789
e20c0b3d
AM		 7902004-03-19 Alan Modra <amodra@bigpond.net.au>
791
792 * aclocal.m4: Regenerate.
793 * config.in: Regenerate.
794 * configure: Regenerate.
795 * po/POTFILES.in: Regenerate.
796 * po/opcodes.pot: Regenerate.
797
fdd12ef3
AM		 7982004-03-16 Alan Modra <amodra@bigpond.net.au>
799
800 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
801 PPC_OPERANDS_GPR_0.
802 * ppc-opc.c (RA0): Define.
803 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
804 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 805 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 806
2dc111b3 8072004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 808
809 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 810
7bfeee7b
AM		 8112004-03-15 Alan Modra <amodra@bigpond.net.au>
812
813 * sparc-dis.c (print_insn_sparc): Update getword prototype.
814
7ffdda93
ML		 8152004-03-12 Michal Ludvig <mludvig@suse.cz>
816
817 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 818 (grps): Delete GRPPLOCK entry.
7ffdda93 819
cc0ec051
AM		 8202004-03-12 Alan Modra <amodra@bigpond.net.au>
821
822 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
823 (M, Mp): Use OP_M.
824 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
825 (GRPPADLCK): Define.
826 (dis386): Use NOP_Fixup on "nop".
827 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
828 (twobyte_has_modrm): Set for 0xa7.
829 (padlock_table): Delete. Move to..
830 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
831 and clflush.
832 (print_insn): Revert PADLOCK_SPECIAL code.
833 (OP_E): Delete sfence, lfence, mfence checks.
834
4fd61dcb
JJ		 8352004-03-12 Jakub Jelinek <jakub@redhat.com>
836
837 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
838 (INVLPG_Fixup): New function.
839 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
840
0f10071e
ML		 8412004-03-12 Michal Ludvig <mludvig@suse.cz>
842
843 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
844 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
845 (padlock_table): New struct with PadLock instructions.
846 (print_insn): Handle PADLOCK_SPECIAL.
847
c02908d2
AM		 8482004-03-12 Alan Modra <amodra@bigpond.net.au>
849
850 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
851 (OP_E): Twiddle clflush to sfence here.
852
d5bb7600
NC		 8532004-03-08 Nick Clifton <nickc@redhat.com>
854
855 * po/de.po: Updated German translation.
856
ae51a426
JR		 8572003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
858
859 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
860 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
861 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
862 accordingly.
863
676a64f4
RS		 8642004-03-01 Richard Sandiford <rsandifo@redhat.com>
865
866 * frv-asm.c: Regenerate.
867 * frv-desc.c: Regenerate.
868 * frv-desc.h: Regenerate.
869 * frv-dis.c: Regenerate.
870 * frv-ibld.c: Regenerate.
871 * frv-opc.c: Regenerate.
872 * frv-opc.h: Regenerate.
873
c7a48b9a
RS		 8742004-03-01 Richard Sandiford <rsandifo@redhat.com>
875
876 * frv-desc.c, frv-opc.c: Regenerate.
877
8ae0baa2
RS		 8782004-03-01 Richard Sandiford <rsandifo@redhat.com>
879
880 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
881
ce11586c
JR		 8822004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
883
884 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
885 Also correct mistake in the comment.
886
6a5709a5
JR		 8872004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
888
889 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
890 ensure that double registers have even numbers.
891 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
892 that reserved instruction 0xfffd does not decode the same
893 as 0xfdfd (ftrv).
894 * sh-opc.h: Add REG_N_D nibble type and use it whereever
895 REG_N refers to a double register.
896 Add REG_N_B01 nibble type and use it instead of REG_NM
897 in ftrv.
898 Adjust the bit patterns in a few comments.
899
e5d2b64f 9002004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 901
902 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 903
1f04b05f
AH		 9042004-02-20 Aldy Hernandez <aldyh@redhat.com>
905
906 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
907
2f3b8700
AH		 9082004-02-20 Aldy Hernandez <aldyh@redhat.com>
909
910 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
911
f0b26da6 9122004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 913
914 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
915 mtivor32, mtivor33, mtivor34.
f0b26da6 916
23d59c56 9172004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 918
919 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 920
34920d91
NC		 9212004-02-10 Petko Manolov <petkan@nucleusys.com>
922
923 * arm-opc.h Maverick accumulator register opcode fixes.
924
44d86481
BE		 9252004-02-13 Ben Elliston <bje@wasabisystems.com>
926
927 * m32r-dis.c: Regenerate.
928
17707c23
MS		 9292004-01-27 Michael Snyder <msnyder@redhat.com>
930
931 * sh-opc.h (sh_table): "fsrra", not "fssra".
932
fe3a9bc4
NC		 9332004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
934
935 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
936 contraints.
937
ff24f124
JJ		 9382004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
939
940 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
941
a02a862a
AM		 9422004-01-19 Alan Modra <amodra@bigpond.net.au>
943
944 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
945 1. Don't print scale factor on AT&T mode when index missing.
946
d164ea7f
AO		 9472004-01-16 Alexandre Oliva <aoliva@redhat.com>
948
949 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
950 when loaded into XR registers.
951
cb10e79a
RS		 9522004-01-14 Richard Sandiford <rsandifo@redhat.com>
953
954 * frv-desc.h: Regenerate.
955 * frv-desc.c: Regenerate.
956 * frv-opc.c: Regenerate.
957
f532f3fa
MS		 9582004-01-13 Michael Snyder <msnyder@redhat.com>
959
960 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
961
e45d0630
PB		 9622004-01-09 Paul Brook <paul@codesourcery.com>
963
964 * arm-opc.h (arm_opcodes): Move generic mcrr after known
965 specific opcodes.
966
3ba7a1aa
DJ		 9672004-01-07 Daniel Jacobowitz <drow@mvista.com>
968
969 * Makefile.am (libopcodes_la_DEPENDENCIES)
970 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
971 comment about the problem.
972 * Makefile.in: Regenerate.
973
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AO		 9742004-01-06 Alexandre Oliva <aoliva@redhat.com>
975
976 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
977 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
978 cut&paste errors in shifting/truncating numerical operands.
979 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
980 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
981 (parse_uslo16): Likewise.
982 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
983 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
984 (parse_s12): Likewise.
985 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
986 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
987 (parse_uslo16): Likewise.
988 (parse_uhi16): Parse gothi and gotfuncdeschi.
989 (parse_d12): Parse got12 and gotfuncdesc12.
990 (parse_s12): Likewise.
991
3ab48931
NC		 9922004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
993
994 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
995 instruction which looks similar to an 'rla' instruction.
a0bd404e 996
c9e214e5 997For older changes see ChangeLog-0203
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999Local Variables:
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GDB Binutils - Deliverables
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