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[gdb/symtab] Fix partial unit psymtabs
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
384f3689
L		 12020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2
3 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
4 * Makefile.in: Regenerated.
5
865e2027
JB		 62020-03-09 Jan Beulich <jbeulich@suse.com>
7
8 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
9 3-operand pseudos.
10 * i386-tbl.h: Re-generate.
11
2f13234b
JB		 122020-03-09 Jan Beulich <jbeulich@suse.com>
13
14 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
15 vprot*, vpsha*, and vpshl*.
16 * i386-tbl.h: Re-generate.
17
3fabc179
JB		 182020-03-09 Jan Beulich <jbeulich@suse.com>
19
20 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
21 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
22 * i386-tbl.h: Re-generate.
23
3677e4c1
JB		 242020-03-09 Jan Beulich <jbeulich@suse.com>
25
26 * i386-gen.c (set_bitfield): Ignore zero-length field names.
27 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
28 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
29 * i386-tbl.h: Re-generate.
30
4c4898e8
JB		 312020-03-09 Jan Beulich <jbeulich@suse.com>
32
33 * i386-gen.c (struct template_arg, struct template_instance,
34 struct template_param, struct template, templates,
35 parse_template, expand_templates): New.
36 (process_i386_opcodes): Various local variables moved to
37 expand_templates. Call parse_template and expand_templates.
38 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
39 * i386-tbl.h: Re-generate.
40
bc49bfd8
JB		 412020-03-06 Jan Beulich <jbeulich@suse.com>
42
43 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
44 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
45 register and memory source templates. Replace VexW= by VexW*
46 where applicable.
47 * i386-tbl.h: Re-generate.
48
4873e243
JB		 492020-03-06 Jan Beulich <jbeulich@suse.com>
50
51 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
52 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
53 * i386-tbl.h: Re-generate.
54
672a349b
JB		 552020-03-06 Jan Beulich <jbeulich@suse.com>
56
57 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
58 * i386-tbl.h: Re-generate.
59
4ed21b58
JB		 602020-03-06 Jan Beulich <jbeulich@suse.com>
61
62 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
63 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
64 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
65 VexW0 on SSE2AVX variants.
66 (vmovq): Drop NoRex64 from XMM/XMM variants.
67 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
68 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
69 applicable use VexW0.
70 * i386-tbl.h: Re-generate.
71
643bb870
JB		 722020-03-06 Jan Beulich <jbeulich@suse.com>
73
74 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
75 * i386-opc.h (Rex64): Delete.
76 (struct i386_opcode_modifier): Remove rex64 field.
77 * i386-opc.tbl (crc32): Drop Rex64.
78 Replace Rex64 with Size64 everywhere else.
79 * i386-tbl.h: Re-generate.
80
a23b33b3
JB		 812020-03-06 Jan Beulich <jbeulich@suse.com>
82
83 * i386-dis.c (OP_E_memory): Exclude recording of used address
84 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
85 addressed memory operands for MPX insns.
86
a0497384
JB		 872020-03-06 Jan Beulich <jbeulich@suse.com>
88
89 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
90 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
91 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
92 (ptwrite): Split into non-64-bit and 64-bit forms.
93 * i386-tbl.h: Re-generate.
94
b630c145
JB		 952020-03-06 Jan Beulich <jbeulich@suse.com>
96
97 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
98 template.
99 * i386-tbl.h: Re-generate.
100
a847e322
JB		 1012020-03-04 Jan Beulich <jbeulich@suse.com>
102
103 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
104 (prefix_table): Move vmmcall here. Add vmgexit.
105 (rm_table): Replace vmmcall entry by prefix_table[] escape.
106 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
107 (cpu_flags): Add CpuSEV_ES entry.
108 * i386-opc.h (CpuSEV_ES): New.
109 (union i386_cpu_flags): Add cpusev_es field.
110 * i386-opc.tbl (vmgexit): New.
111 * i386-init.h, i386-tbl.h: Re-generate.
112
3cd7f3e3
L		 1132020-03-03 H.J. Lu <hongjiu.lu@intel.com>
114
115 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
116 with MnemonicSize.
117 * i386-opc.h (IGNORESIZE): New.
118 (DEFAULTSIZE): Likewise.
119 (IgnoreSize): Removed.
120 (DefaultSize): Likewise.
121 (MnemonicSize): New.
122 (i386_opcode_modifier): Replace ignoresize/defaultsize with
123 mnemonicsize.
124 * i386-opc.tbl (IgnoreSize): New.
125 (DefaultSize): Likewise.
126 * i386-tbl.h: Regenerated.
127
b8ba1385
SB		 1282020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
129
130 PR 25627
131 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
132 instructions.
133
10d97a0f
L		 1342020-03-03 H.J. Lu <hongjiu.lu@intel.com>
135
136 PR gas/25622
137 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
138 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
139 * i386-tbl.h: Regenerated.
140
dc1e8a47
AM		 1412020-02-26 Alan Modra <amodra@gmail.com>
142
143 * aarch64-asm.c: Indent labels correctly.
144 * aarch64-dis.c: Likewise.
145 * aarch64-gen.c: Likewise.
146 * aarch64-opc.c: Likewise.
147 * alpha-dis.c: Likewise.
148 * i386-dis.c: Likewise.
149 * nds32-asm.c: Likewise.
150 * nfp-dis.c: Likewise.
151 * visium-dis.c: Likewise.
152
265b4673
CZ		 1532020-02-25 Claudiu Zissulescu <claziss@gmail.com>
154
155 * arc-regs.h (int_vector_base): Make it available for all ARC
156 CPUs.
157
bd0cf5a6
NC		 1582020-02-20 Nelson Chu <nelson.chu@sifive.com>
159
160 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
161 changed.
162
fa164239
JW		 1632020-02-19 Nelson Chu <nelson.chu@sifive.com>
164
165 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
166 c.mv/c.li if rs1 is zero.
167
272a84b1
L		 1682020-02-17 H.J. Lu <hongjiu.lu@intel.com>
169
170 * i386-gen.c (cpu_flag_init): Replace CpuABM with
171 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
172 CPU_POPCNT_FLAGS.
173 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
174 * i386-opc.h (CpuABM): Removed.
175 (CpuPOPCNT): New.
176 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
177 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
178 popcnt. Remove CpuABM from lzcnt.
179 * i386-init.h: Regenerated.
180 * i386-tbl.h: Likewise.
181
1f730c46
JB		 1822020-02-17 Jan Beulich <jbeulich@suse.com>
183
184 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
185 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
186 VexW1 instead of open-coding them.
187 * i386-tbl.h: Re-generate.
188
c8f8eebc
JB		 1892020-02-17 Jan Beulich <jbeulich@suse.com>
190
191 * i386-opc.tbl (AddrPrefixOpReg): Define.
192 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
193 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
194 templates. Drop NoRex64.
195 * i386-tbl.h: Re-generate.
196
b9915cbc
JB		 1972020-02-17 Jan Beulich <jbeulich@suse.com>
198
199 PR gas/6518
200 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
201 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
202 into Intel syntax instance (with Unpsecified) and AT&T one
203 (without).
204 (vcvtneps2bf16): Likewise, along with folding the two so far
205 separate ones.
206 * i386-tbl.h: Re-generate.
207
ce504911
L		 2082020-02-16 H.J. Lu <hongjiu.lu@intel.com>
209
210 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
211 CPU_ANY_SSE4A_FLAGS.
212
dabec65d
AM		 2132020-02-17 Alan Modra <amodra@gmail.com>
214
215 * i386-gen.c (cpu_flag_init): Correct last change.
216
af5c13b0
L		 2172020-02-16 H.J. Lu <hongjiu.lu@intel.com>
218
219 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
220 CPU_ANY_SSE4_FLAGS.
221
6867aac0
L		 2222020-02-14 H.J. Lu <hongjiu.lu@intel.com>
223
224 * i386-opc.tbl (movsx): Remove Intel syntax comments.
225 (movzx): Likewise.
226
65fca059
JB		 2272020-02-14 Jan Beulich <jbeulich@suse.com>
228
229 PR gas/25438
230 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
231 destination for Cpu64-only variant.
232 (movzx): Fold patterns.
233 * i386-tbl.h: Re-generate.
234
7deea9aa
JB		 2352020-02-13 Jan Beulich <jbeulich@suse.com>
236
237 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
238 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
239 CPU_ANY_SSE4_FLAGS entry.
240 * i386-init.h: Re-generate.
241
6c0946d0
JB		 2422020-02-12 Jan Beulich <jbeulich@suse.com>
243
244 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
245 with Unspecified, making the present one AT&T syntax only.
246 * i386-tbl.h: Re-generate.
247
ddb56fe6
JB		 2482020-02-12 Jan Beulich <jbeulich@suse.com>
249
250 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
251 * i386-tbl.h: Re-generate.
252
5990e377
JB		 2532020-02-12 Jan Beulich <jbeulich@suse.com>
254
255 PR gas/24546
256 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
257 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
258 Amd64 and Intel64 templates.
259 (call, jmp): Likewise for far indirect variants. Dro
260 Unspecified.
261 * i386-tbl.h: Re-generate.
262
50128d0c
JB		 2632020-02-11 Jan Beulich <jbeulich@suse.com>
264
265 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
266 * i386-opc.h (ShortForm): Delete.
267 (struct i386_opcode_modifier): Remove shortform field.
268 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
269 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
270 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
271 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
272 Drop ShortForm.
273 * i386-tbl.h: Re-generate.
274
1e05b5c4
JB		 2752020-02-11 Jan Beulich <jbeulich@suse.com>
276
277 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
278 fucompi): Drop ShortForm from operand-less templates.
279 * i386-tbl.h: Re-generate.
280
2f5dd314
AM		 2812020-02-11 Alan Modra <amodra@gmail.com>
282
283 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
284 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
285 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
286 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
287 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
288
5aae9ae9
MM		 2892020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
290
291 * arm-dis.c (print_insn_cde): Define 'V' parse character.
292 (cde_opcodes): Add VCX* instructions.
293
4934a27c
MM		 2942020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
295 Matthew Malcomson <matthew.malcomson@arm.com>
296
297 * arm-dis.c (struct cdeopcode32): New.
298 (CDE_OPCODE): New macro.
299 (cde_opcodes): New disassembly table.
300 (regnames): New option to table.
301 (cde_coprocs): New global variable.
302 (print_insn_cde): New
303 (print_insn_thumb32): Use print_insn_cde.
304 (parse_arm_disassembler_options): Parse coprocN args.
305
4b5aaf5f
L		 3062020-02-10 H.J. Lu <hongjiu.lu@intel.com>
307
308 PR gas/25516
309 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
310 with ISA64.
311 * i386-opc.h (AMD64): Removed.
312 (Intel64): Likewose.
313 (AMD64): New.
314 (INTEL64): Likewise.
315 (INTEL64ONLY): Likewise.
316 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
317 * i386-opc.tbl (Amd64): New.
318 (Intel64): Likewise.
319 (Intel64Only): Likewise.
320 Replace AMD64 with Amd64. Update sysenter/sysenter with
321 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
322 * i386-tbl.h: Regenerated.
323
9fc0b501
SB		 3242020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
325
326 PR 25469
327 * z80-dis.c: Add support for GBZ80 opcodes.
328
c5d7be0c
AM		 3292020-02-04 Alan Modra <amodra@gmail.com>
330
331 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
332
44e4546f
AM		 3332020-02-03 Alan Modra <amodra@gmail.com>
334
335 * m32c-ibld.c: Regenerate.
336
b2b1453a
AM		 3372020-02-01 Alan Modra <amodra@gmail.com>
338
339 * frv-ibld.c: Regenerate.
340
4102be5c
JB		 3412020-01-31 Jan Beulich <jbeulich@suse.com>
342
343 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
344 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
345 (OP_E_memory): Replace xmm_mdq_mode case label by
346 vex_scalar_w_dq_mode one.
347 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
348
825bd36c
JB		 3492020-01-31 Jan Beulich <jbeulich@suse.com>
350
351 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
352 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
353 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
354 (intel_operand_size): Drop vex_w_dq_mode case label.
355
c3036ed0
RS		 3562020-01-31 Richard Sandiford <richard.sandiford@arm.com>
357
358 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
359 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
360
0c115f84
AM		 3612020-01-30 Alan Modra <amodra@gmail.com>
362
363 * m32c-ibld.c: Regenerate.
364
bd434cc4
JM		 3652020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
366
367 * bpf-opc.c: Regenerate.
368
aeab2b26
JB		 3692020-01-30 Jan Beulich <jbeulich@suse.com>
370
371 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
372 (dis386): Use them to replace C2/C3 table entries.
373 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
374 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
375 ones. Use Size64 instead of DefaultSize on Intel64 ones.
376 * i386-tbl.h: Re-generate.
377
62b3f548
JB		 3782020-01-30 Jan Beulich <jbeulich@suse.com>
379
380 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
381 forms.
382 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
383 DefaultSize.
384 * i386-tbl.h: Re-generate.
385
1bd8ae10
AM		 3862020-01-30 Alan Modra <amodra@gmail.com>
387
388 * tic4x-dis.c (tic4x_dp): Make unsigned.
389
bc31405e
L		 3902020-01-27 H.J. Lu <hongjiu.lu@intel.com>
391 Jan Beulich <jbeulich@suse.com>
392
393 PR binutils/25445
394 * i386-dis.c (MOVSXD_Fixup): New function.
395 (movsxd_mode): New enum.
396 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
397 (intel_operand_size): Handle movsxd_mode.
398 (OP_E_register): Likewise.
399 (OP_G): Likewise.
400 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
401 register on movsxd. Add movsxd with 16-bit destination register
402 for AMD64 and Intel64 ISAs.
403 * i386-tbl.h: Regenerated.
404
7568c93b
TC		 4052020-01-27 Tamar Christina <tamar.christina@arm.com>
406
407 PR 25403
408 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
409 * aarch64-asm-2.c: Regenerate
410 * aarch64-dis-2.c: Likewise.
411 * aarch64-opc-2.c: Likewise.
412
c006a730
JB		 4132020-01-21 Jan Beulich <jbeulich@suse.com>
414
415 * i386-opc.tbl (sysret): Drop DefaultSize.
416 * i386-tbl.h: Re-generate.
417
c906a69a
JB		 4182020-01-21 Jan Beulich <jbeulich@suse.com>
419
420 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
421 Dword.
422 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
423 * i386-tbl.h: Re-generate.
424
26916852
NC		 4252020-01-20 Nick Clifton <nickc@redhat.com>
426
427 * po/de.po: Updated German translation.
428 * po/pt_BR.po: Updated Brazilian Portuguese translation.
429 * po/uk.po: Updated Ukranian translation.
430
4d6cbb64
AM		 4312020-01-20 Alan Modra <amodra@gmail.com>
432
433 * hppa-dis.c (fput_const): Remove useless cast.
434
2bddb71a
AM		 4352020-01-20 Alan Modra <amodra@gmail.com>
436
437 * arm-dis.c (print_insn_arm): Wrap 'T' value.
438
1b1bb2c6
NC		 4392020-01-18 Nick Clifton <nickc@redhat.com>
440
441 * configure: Regenerate.
442 * po/opcodes.pot: Regenerate.
443
ae774686
NC		 4442020-01-18 Nick Clifton <nickc@redhat.com>
445
446 Binutils 2.34 branch created.
447
07f1f3aa
CB		 4482020-01-17 Christian Biesinger <cbiesinger@google.com>
449
450 * opintl.h: Fix spelling error (seperate).
451
42e04b36
L		 4522020-01-17 H.J. Lu <hongjiu.lu@intel.com>
453
454 * i386-opc.tbl: Add {vex} pseudo prefix.
455 * i386-tbl.h: Regenerated.
456
2da2eaf4
AV		 4572020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
458
459 PR 25376
460 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
461 (neon_opcodes): Likewise.
462 (select_arm_features): Make sure we enable MVE bits when selecting
463 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
464 any architecture.
465
d0849eed
JB		 4662020-01-16 Jan Beulich <jbeulich@suse.com>
467
468 * i386-opc.tbl: Drop stale comment from XOP section.
469
9cf70a44
JB		 4702020-01-16 Jan Beulich <jbeulich@suse.com>
471
472 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
473 (extractps): Add VexWIG to SSE2AVX forms.
474 * i386-tbl.h: Re-generate.
475
4814632e
JB		 4762020-01-16 Jan Beulich <jbeulich@suse.com>
477
478 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
479 Size64 from and use VexW1 on SSE2AVX forms.
480 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
481 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
482 * i386-tbl.h: Re-generate.
483
aad09917
AM		 4842020-01-15 Alan Modra <amodra@gmail.com>
485
486 * tic4x-dis.c (tic4x_version): Make unsigned long.
487 (optab, optab_special, registernames): New file scope vars.
488 (tic4x_print_register): Set up registernames rather than
489 malloc'd registertable.
490 (tic4x_disassemble): Delete optable and optable_special. Use
491 optab and optab_special instead. Throw away old optab,
492 optab_special and registernames when info->mach changes.
493
7a6bf3be
SB		 4942020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
495
496 PR 25377
497 * z80-dis.c (suffix): Use .db instruction to generate double
498 prefix.
499
ca1eaac0
AM		 5002020-01-14 Alan Modra <amodra@gmail.com>
501
502 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
503 values to unsigned before shifting.
504
1d67fe3b
TT		 5052020-01-13 Thomas Troeger <tstroege@gmx.de>
506
507 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
508 flow instructions.
509 (print_insn_thumb16, print_insn_thumb32): Likewise.
510 (print_insn): Initialize the insn info.
511 * i386-dis.c (print_insn): Initialize the insn info fields, and
512 detect jumps.
513
5e4f7e05
CZ		 5142012-01-13 Claudiu Zissulescu <claziss@gmail.com>
515
516 * arc-opc.c (C_NE): Make it required.
517
b9fe6b8a
CZ		 5182012-01-13 Claudiu Zissulescu <claziss@gmail.com>
519
520 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
521 reserved register name.
522
90dee485
AM		 5232020-01-13 Alan Modra <amodra@gmail.com>
524
525 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
526 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
527
febda64f
AM		 5282020-01-13 Alan Modra <amodra@gmail.com>
529
530 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
531 result of wasm_read_leb128 in a uint64_t and check that bits
532 are not lost when copying to other locals. Use uint32_t for
533 most locals. Use PRId64 when printing int64_t.
534
df08b588
AM		 5352020-01-13 Alan Modra <amodra@gmail.com>
536
537 * score-dis.c: Formatting.
538 * score7-dis.c: Formatting.
539
b2c759ce
AM		 5402020-01-13 Alan Modra <amodra@gmail.com>
541
542 * score-dis.c (print_insn_score48): Use unsigned variables for
543 unsigned values. Don't left shift negative values.
544 (print_insn_score32): Likewise.
545 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
546
5496abe1
AM		 5472020-01-13 Alan Modra <amodra@gmail.com>
548
549 * tic4x-dis.c (tic4x_print_register): Remove dead code.
550
202e762b
AM		 5512020-01-13 Alan Modra <amodra@gmail.com>
552
553 * fr30-ibld.c: Regenerate.
554
7ef412cf
AM		 5552020-01-13 Alan Modra <amodra@gmail.com>
556
557 * xgate-dis.c (print_insn): Don't left shift signed value.
558 (ripBits): Formatting, use 1u.
559
7f578b95
AM		 5602020-01-10 Alan Modra <amodra@gmail.com>
561
562 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
563 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
564
441af85b
AM		 5652020-01-10 Alan Modra <amodra@gmail.com>
566
567 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
568 and XRREG value earlier to avoid a shift with negative exponent.
569 * m10200-dis.c (disassemble): Similarly.
570
bce58db4
NC		 5712020-01-09 Nick Clifton <nickc@redhat.com>
572
573 PR 25224
574 * z80-dis.c (ld_ii_ii): Use correct cast.
575
40c75bc8
SB		 5762020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
577
578 PR 25224
579 * z80-dis.c (ld_ii_ii): Use character constant when checking
580 opcode byte value.
581
d835a58b
JB		 5822020-01-09 Jan Beulich <jbeulich@suse.com>
583
584 * i386-dis.c (SEP_Fixup): New.
585 (SEP): Define.
586 (dis386_twobyte): Use it for sysenter/sysexit.
587 (enum x86_64_isa): Change amd64 enumerator to value 1.
588 (OP_J): Compare isa64 against intel64 instead of amd64.
589 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
590 forms.
591 * i386-tbl.h: Re-generate.
592
030a2e78
AM		 5932020-01-08 Alan Modra <amodra@gmail.com>
594
595 * z8k-dis.c: Include libiberty.h
596 (instr_data_s): Make max_fetched unsigned.
597 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
598 Don't exceed byte_info bounds.
599 (output_instr): Make num_bytes unsigned.
600 (unpack_instr): Likewise for nibl_count and loop.
601 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
602 idx unsigned.
603 * z8k-opc.h: Regenerate.
604
bb82aefe
SV		 6052020-01-07 Shahab Vahedi <shahab@synopsys.com>
606
607 * arc-tbl.h (llock): Use 'LLOCK' as class.
608 (llockd): Likewise.
609 (scond): Use 'SCOND' as class.
610 (scondd): Likewise.
611 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
612 (scondd): Likewise.
613
cc6aa1a6
AM		 6142020-01-06 Alan Modra <amodra@gmail.com>
615
616 * m32c-ibld.c: Regenerate.
617
660e62b1
AM		 6182020-01-06 Alan Modra <amodra@gmail.com>
619
620 PR 25344
621 * z80-dis.c (suffix): Don't use a local struct buffer copy.
622 Peek at next byte to prevent recursion on repeated prefix bytes.
623 Ensure uninitialised "mybuf" is not accessed.
624 (print_insn_z80): Don't zero n_fetch and n_used here,..
625 (print_insn_z80_buf): ..do it here instead.
626
c9ae58fe
AM		 6272020-01-04 Alan Modra <amodra@gmail.com>
628
629 * m32r-ibld.c: Regenerate.
630
5f57d4ec
AM		 6312020-01-04 Alan Modra <amodra@gmail.com>
632
633 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
634
2c5c1196
AM		 6352020-01-04 Alan Modra <amodra@gmail.com>
636
637 * crx-dis.c (match_opcode): Avoid shift left of signed value.
638
2e98c6c5
AM		 6392020-01-04 Alan Modra <amodra@gmail.com>
640
641 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
642
567dfba2
JB		 6432020-01-03 Jan Beulich <jbeulich@suse.com>
644
5437a02a
JB		 645 * aarch64-tbl.h (aarch64_opcode_table): Use
646 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
647
6482020-01-03 Jan Beulich <jbeulich@suse.com>
649
650 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 651 forms of SUDOT and USDOT.
652
8c45011a
JB		 6532020-01-03 Jan Beulich <jbeulich@suse.com>
654
5437a02a 655 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 656 uzip{1,2}.
657 * opcodes/aarch64-dis-2.c: Re-generate.
658
f4950f76
JB		 6592020-01-03 Jan Beulich <jbeulich@suse.com>
660
5437a02a 661 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 662 FMMLA encoding.
663 * opcodes/aarch64-dis-2.c: Re-generate.
664
6655dba2
SB		 6652020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
666
667 * z80-dis.c: Add support for eZ80 and Z80 instructions.
668
b14ce8bf
AM		 6692020-01-01 Alan Modra <amodra@gmail.com>
670
671 Update year range in copyright notice of all files.
672
0b114740 673For older changes see ChangeLog-2019
3499769a 674\f
0b114740 675Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 676
677Copying and distribution of this file, with or without modification,
678are permitted in any medium without royalty provided the copyright
679notice and this notice are preserved.
680
681Local Variables:
682mode: change-log
683left-margin: 8
684fill-column: 74
685version-control: never
686End:
GDB Binutils - Deliverables
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