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98675402
RS		 12010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
2
3 * mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define.
4 (mips_builtin_opcodes): Add loongson3a specific instructions.
5 * mips-dis.c (print_insn_args): Handle the new arguments +a|b|c|z|Z.
6
a471ec3a
RS		 72010-12-11 Mingming Sun <mingm.sun@gmail.com>
8
9 * mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
10 fixed point instructions.
11
8b9a522f
MF		 122010-12-09 Mike Frysinger <vapier@gentoo.org>
13
14 * .gitignore: New file.
15
1de34e0a
AM		 162010-11-25 Alan Modra <amodra@gmail.com>
17
18 * po/es.po: Update.
19 * po/fr.po: Update.
20 * po/nl.po: Update.
21 * po/zh_CN.po: Update.
22
fd503541
NC		 232010-11-11 Mingming Sun <mingm.sun@gmail.com>
24
25 * mips-dis.c (mips_arch_choices): Add loongson3a.
26 * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
27 (mips_builtin_opcodes): Modify some instructions' membership from
1de34e0a 28 IL2F to IL2F|IL3A.
fd503541 29
8e295ce0
NC		 302010-11-10 Nick Clifton <nickc@redhat.com>
31
32 * po/fi.po: Updated Finnish translation.
33
2ee0aedf
TG		 342010-11-05 Tristan Gingold <gingold@adacore.com>
35
36 * po/opcodes.pot: Regenerate
37
af478898
MR		 382010-10-28 Maciej W. Rozycki <macro@codesourcery.com>
39
40 * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".
41
be7a250d
AK		 422010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
43
44 * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
45
d958d1a3
CF		 462010-10-25 Chao-ying Fu <fu@mips.com>
47
48 * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
49
c0621d88
NS		 502010-10-25 Nathan Sidwell <nathan@codesourcery.com>
51
52 * tic6x-dis.c: Add attribution.
53
a43817df
AM		 542010-10-22 Alan Modra <amodra@gmail.com>
55
56 * Makefile.am (CLEANFILES): Add stamp-lm32. Sort.
57 * Makefile.in: Regenerate.
58
704897fb
MR		 592010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
60
61 * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
62 macros before their corresponding MIPS III hardware instructions.
63
da98bb4c
L		 642010-10-16 H.J. Lu <hongjiu.lu@intel.com>
65
66 * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
67
68 * i386-init.h: Regenerated.
69
e1791cb8
MF		 702010-10-15 Mike Frysinger <vapier@gentoo.org>
71
72 * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M.
73
553d0a74
L		 742010-10-14 H.J. Lu <hongjiu.lu@intel.com>
75
76 * i386-opc.tbl: Remove CheckRegSize from movq.
77 * i386-tbl.h: Regenerated.
78
cfc08d49
L		 792010-10-14 H.J. Lu <hongjiu.lu@intel.com>
80
81 * i386-opc.tbl: Remove CheckRegSize from instructions with
82 0, 1 or fixed operands.
83 * i386-tbl.h: Regenerated.
84
56ffb741
L		 852010-10-14 H.J. Lu <hongjiu.lu@intel.com>
86
87 * i386-gen.c (opcode_modifiers): Add CheckRegSize.
88
89 * i386-opc.h (CheckRegSize): New.
90 (i386_opcode_modifier): Add checkregsize.
91
92 * i386-opc.tbl: Add CheckRegSize to instructions which
93 require register size check.
94 * i386-tbl.h: Regenerated.
95
1a2dab1f
AS		 962010-10-12 Andreas Schwab <schwab@linux-m68k.org>
97
98 * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
99
a3ec2691
AK		 1002010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
101
102 * s390-opc.c: Make the instruction masks for the load/store on
103 condition instructions to cover the condition code mask as well.
104 * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
105
d92fa646
JK		 1062010-10-11 Jan Kratochvil <jan.kratochvil@redhat.com>
107 Jiang Jilin <freephp@gmail.com>
108
109 * Makefile.am (libopcodes_a_SOURCES): New as empty.
110 * Makefile.in: Regenerate.
111
4469d2be
AM		 1122010-10-09 Matt Rice <ratmice@gmail.com>
113
114 * fr30-desc.h: Regenerate.
115 * frv-desc.h: Regenerate.
116 * ip2k-desc.h: Regenerate.
117 * iq2000-desc.h: Regenerate.
118 * lm32-desc.h: Regenerate.
119 * m32c-desc.h: Regenerate.
120 * m32r-desc.h: Regenerate.
121 * mep-desc.h: Regenerate.
122 * mep-opc.c: Regenerate.
123 * mt-desc.h: Regenerate.
124 * openrisc-desc.h: Regenerate.
125 * xc16x-desc.h: Regenerate.
126 * xstormy16-desc.h: Regenerate.
127
9ccb8af9
AM		 1282010-10-08 Pierre Muller <muller@ics.u-strasbg.fr>
129
130 Fix build with -DDEBUG=7
131 * frv-opc.c: Regenerate.
132 * or32-dis.c (DEBUG): Don't redefine.
133 (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
134 Adapt DEBUG code to some type changes throughout.
135 * or32-opc.c (or32_extract): Likewise.
136
5d4c71e1
BS		 1372010-10-07 Bernd Schmidt <bernds@codesourcery.com>
138
139 * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
140 in SPKERNEL instructions.
141
9ce00134
L		 1422010-10-02 H.J. Lu <hongjiu.lu@intel.com>
143
144 PR binutils/12076
145 * i386-dis.c (RMAL): Remove duplicate.
146
e7390eec
PM		 1472010-09-30 Pierre Muller <muller@ics.u-strasbg.fr>
148
149 * s390-mkopc.c (main): Exit with error 1 if sscanf fails
150 to parse all 6 parameters.
151
d2ae9c84
PM		 1522010-09-28 Pierre Muller <muller@ics.u-strasbg.fr>
153
154 * s390-mkopc.c (main): Change description array size to 80.
155 Add maximum length of 79 to description parsing.
156
3cac54d2
RW		 1572010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
158
159 * configure: Regenerate.
160
d9aee5d7
AK		 1612010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
162
163 * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
164 (main): Recognize the new CPU string.
165 * s390-opc.c: Add new instruction formats and masks.
166 * s390-opc.txt: Add new z196 instructions.
167
02cbf767
AK		 1682010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
169
170 * s390-dis.c (print_insn_s390): Pick instruction with most
171 specific mask.
172 * s390-opc.c: Add unused bits to the insn mask.
173 * s390-opc.txt: Reorder some instructions to prefer more recent
174 versions.
175
6844b2c2
MGD		 1762010-09-27 Tejas Belagod <tejas.belagod@arm.com>
177
178 * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
179 correction to unaligned PCs while printing comment.
180
90ec0d68
MGD		 1812010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
182
183 * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
184 (thumb32_opcodes): Likewise.
185 (banked_regname): New function.
186 (print_insn_arm): Add Virtualization Extensions support.
187 (print_insn_thumb32): Likewise.
188
eea54501
MGD		 1892010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
190
191 * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
192 ARM state.
193
f4c65163
MGD		 1942010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
195
196 * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
197 (thumb32_opcodes): Likewise.
198
60e5ef9f
MGD		 1992010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
200
201 * arm-dis.c (arm_opcodes): Add support for pldw.
202 (thumb32_opcodes): Likewise.
203
7a360e83
MF		 2042010-09-22 Robin Getz <robin.getz@analog.com>
205
206 * bfin-dis.c (fmtconst): Cast address to 32bits.
207
35fc57f3
MF		 2082010-09-22 Mike Frysinger <vapier@gentoo.org>
209
210 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
211
219b747a
MF		 2122010-09-22 Robin Getz <robin.getz@analog.com>
213
214 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
215 Reject P6/P7 to TESTSET.
216 (decode_PushPopReg_0): Check for parallel insns. Reject pushing
217 SP onto the stack.
218 (decode_PushPopMultiple_0): Check for parallel insns. Make sure
219 P/D fields match all the time.
220 (decode_CCflag_0): Check for parallel insns. Verify x/y fields
221 are 0 for accumulator compares.
222 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
223 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
224 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
225 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
226 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
227 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
228 insns.
229 (decode_dagMODim_0): Verify br field for IREG ops.
230 (decode_LDST_0): Reject preg load into same preg.
231 (_print_insn_bfin): Handle returns for ILLEGAL decodes.
232 (print_insn_bfin): Likewise.
233
775f1cf0
MF		 2342010-09-22 Mike Frysinger <vapier@gentoo.org>
235
236 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
237
0b7691fd
MF		 2382010-09-22 Robin Getz <robin.getz@analog.com>
239
240 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
241
b2459327
MF		 2422010-09-22 Mike Frysinger <vapier@gentoo.org>
243
244 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
245
50e2162a
MF		 2462010-09-22 Robin Getz <robin.getz@analog.com>
247
248 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
249 register values greater than 8.
250 (IS_RESERVEDREG, allreg, mostreg): New helpers.
251 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
252 (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
253 (decode_CC2dreg_0): Check valid CC register number.
254
a01eda85
MF		 2552010-09-22 Robin Getz <robin.getz@analog.com>
256
257 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
258
22215ae0
MF		 2592010-09-22 Robin Getz <robin.getz@analog.com>
260
261 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
262 (reg_names): Likewise.
263 (decode_statbits): Likewise; while reformatting to make manageable.
264
73a63ccf
MF		 2652010-09-22 Mike Frysinger <vapier@gentoo.org>
266
267 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
268 (decode_pseudoOChar_0): New function.
269 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
270
59a82d23
MF		 2712010-09-22 Robin Getz <robin.getz@analog.com>
272
273 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
274 LSHIFT instead of SHIFT.
275
528c6277
MF		 2762010-09-22 Mike Frysinger <vapier@gentoo.org>
277
278 * bfin-dis.c (constant_formats): Constify the whole structure.
279 (fmtconst): Add const to return value.
280 (reg_names): Mark const.
281 (decode_multfunc): Mark s0/s1 as const.
282 (decode_macfunc): Mark a/sop as const.
283
db472d6f
MGD		 2842010-09-17 Tejas Belagod <tejas.belagod@arm.com>
285
286 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
287
f6690563
MR		 2882010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
289
290 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
291 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
292
8901a3cd
PM		 2932010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
294
295 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
296 dlx_insn_type array.
297
d9e3625e
L		 2982010-08-31 H.J. Lu <hongjiu.lu@intel.com>
299
300 PR binutils/11960
301 * i386-dis.c (sIv): New.
302 (dis386): Replace Iq with sIv on "pushT".
303 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
4469d2be 304 (x86_64_table): Replace {T|}/{P|} with P.
d9e3625e
L		 305 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
306 (OP_sI): Update v_mode. Remove w_mode.
307
f383de66
NF		 3082010-08-27 Nathan Froyd <froydnj@codesourcery.com>
309
310 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
311 on E500 and E500MC.
312
1ab03f4b
L		 3132010-08-17 H.J. Lu <hongjiu.lu@intel.com>
314
315 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
316 prefetchw.
317
22109423
L		 3182010-08-06 Quentin Neill <quentin.neill@amd.com>
319
320 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
321 to processor flags for PENTIUMPRO processors and later.
322 * i386-opc.h (enum): Add CpuNop.
323 (i386_cpu_flags): Add cpunop bit.
324 * i386-opc.tbl: Change nop cpu_flags.
325 * i386-init.h: Regenerated.
326 * i386-tbl.h: Likewise.
327
b49dfb4a
L		 3282010-08-06 Quentin Neill <quentin.neill@amd.com>
329
330 * i386-opc.h (enum): Fix typos in comments.
331
6ca4eb77
AM		 3322010-08-06 Alan Modra <amodra@gmail.com>
333
334 * disassemble.c: Formatting.
335 (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
336
92d4d42e
L		 3372010-08-05 H.J. Lu <hongjiu.lu@intel.com>
338
339 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
340 * i386-tbl.h: Regenerated.
341
b414985b
L		 3422010-08-05 H.J. Lu <hongjiu.lu@intel.com>
343
344 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
345
346 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
347 * i386-tbl.h: Regenerated.
348
f9c7014e
DD		 3492010-07-29 DJ Delorie <dj@redhat.com>
350
351 * rx-decode.opc (SRR): New.
352 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
353 r0,r0) and NOP3 (max r0,r0) special cases.
354 * rx-decode.c: Regenerate.
6ca4eb77 355
592a252b
L		 3562010-07-28 H.J. Lu <hongjiu.lu@intel.com>
357
358 * i386-dis.c: Add 0F to VEX opcode enums.
359
3cf79a01
DD		 3602010-07-27 DJ Delorie <dj@redhat.com>
361
362 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
363 (rx_decode_opcode): Likewise.
364 * rx-decode.c: Regenerate.
365
1cd986c5
NC		 3662010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
367 Ina Pandit <ina.pandit@kpitcummins.com>
368
369 * v850-dis.c (v850_sreg_names): Updated structure for system
370 registers.
371 (float_cc_names): new structure for condition codes.
372 (print_value): Update the function that prints value.
373 (get_operand_value): New function to get the operand value.
374 (disassemble): Updated to handle the disassembly of instructions.
375 (print_insn_v850): Updated function to print instruction for different
376 families.
377 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
378 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
379 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
380 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
381 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
382 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
383 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
384 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
385 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
386 (v850_operands): Update with the relocation name. Also update
387 the instructions with specific set of processors.
388
52e7f43d
RE		 3892010-07-08 Tejas Belagod <tejas.belagod@arm.com>
390
391 * arm-dis.c (print_insn_arm): Add cases for printing more
392 symbolic operands.
393 (print_insn_thumb32): Likewise.
394
c680e7f6
MR		 3952010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
396
397 * mips-dis.c (print_insn_mips): Correct branch instruction type
398 determination.
399
9a2c7088
MR		 4002010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
401
402 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
403 type and delay slot determination.
404 (print_insn_mips16): Extend branch instruction type and delay
405 slot determination to cover all instructions.
406 * mips16-opc.c (BR): Remove macro.
407 (UBR, CBR): New macros.
408 (mips16_opcodes): Update branch annotation for "b", "beqz",
409 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
410 and "jrc".
411
d7d9a9f8
L		 4122010-07-05 H.J. Lu <hongjiu.lu@intel.com>
413
414 AVX Programming Reference (June, 2010)
415 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
416 * i386-opc.tbl: Likewise.
417 * i386-tbl.h: Regenerated.
418
77321f53
L		 4192010-07-05 H.J. Lu <hongjiu.lu@intel.com>
420
421 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
422
7102e95e
AS		 4232010-07-03 Andreas Schwab <schwab@linux-m68k.org>
424
425 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
426 ppc_cpu_t before inverting.
3a5530ea
AS		 427 (ppc_parse_cpu): Likewise.
428 (print_insn_powerpc): Likewise.
7102e95e 429
bdc70b4a
AM		 4302010-07-03 Alan Modra <amodra@gmail.com>
431
432 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
433 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
434 (PPC64, MFDEC2): Update.
435 (NON32, NO371): Define.
436 (powerpc_opcode): Update to not use old opcode flags, and avoid
437 -m601 duplicates.
438
21375995
DD		 4392010-07-03 DJ Delorie <dj@delorie.com>
440
441 * m32c-ibld.c: Regenerate.
442
81a0b7e2
AM		 4432010-07-03 Alan Modra <amodra@gmail.com>
444
445 * ppc-opc.c (PWR2COM): Define.
446 (PPCPWR2): Add PPC_OPCODE_COMMON.
447 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
448 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
449 "rac" from -mcom.
450
c7b8aa3a
L		 4512010-07-01 H.J. Lu <hongjiu.lu@intel.com>
452
453 AVX Programming Reference (June, 2010)
454 * i386-dis.c (PREFIX_0FAE_REG_0): New.
455 (PREFIX_0FAE_REG_1): Likewise.
456 (PREFIX_0FAE_REG_2): Likewise.
457 (PREFIX_0FAE_REG_3): Likewise.
458 (PREFIX_VEX_3813): Likewise.
459 (PREFIX_VEX_3A1D): Likewise.
460 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
461 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
462 PREFIX_VEX_3A1D.
463 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
464 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
465 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
466
467 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
468 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
469 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
470
471 * i386-opc.h (CpuXsaveopt): New.
77321f53 472 (CpuFSGSBase): Likewise.
c7b8aa3a
L		 473 (CpuRdRnd): Likewise.
474 (CpuF16C): Likewise.
475 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
476 cpuf16c.
477
478 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
479 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
a00eb5e8
L		 480 * i386-init.h: Regenerated.
481 * i386-tbl.h: Likewise.
c7b8aa3a 482
09a8ad8d
AM		 4832010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
484
485 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
486 and mtocrf on EFS.
487
360cfc9c
AM		 4882010-06-29 Alan Modra <amodra@gmail.com>
489
490 * maxq-dis.c: Delete file.
491 * Makefile.am: Remove references to maxq.
492 * configure.in: Likewise.
493 * disassemble.c: Likewise.
494 * Makefile.in: Regenerate.
495 * configure: Regenerate.
496 * po/POTFILES.in: Regenerate.
497
dc898d5e
AM		 4982010-06-29 Alan Modra <amodra@gmail.com>
499
500 * mep-dis.c: Regenerate.
501
8e560766
MGD		 5022010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
503
504 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
505
c7e2358a
AM		 5062010-06-27 Alan Modra <amodra@gmail.com>
507
508 * arc-dis.c (arc_sprintf): Delete set but unused variables.
509 (decodeInstr): Likewise.
510 * dlx-dis.c (print_insn_dlx): Likewise.
511 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
512 * maxq-dis.c (check_move, print_insn): Likewise.
513 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
514 * msp430-dis.c (msp430_branchinstr): Likewise.
515 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
516 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
517 * sparc-dis.c (print_insn_sparc): Likewise.
518 * fr30-asm.c: Regenerate.
519 * frv-asm.c: Regenerate.
520 * ip2k-asm.c: Regenerate.
521 * iq2000-asm.c: Regenerate.
522 * lm32-asm.c: Regenerate.
523 * m32c-asm.c: Regenerate.
524 * m32r-asm.c: Regenerate.
525 * mep-asm.c: Regenerate.
526 * mt-asm.c: Regenerate.
527 * openrisc-asm.c: Regenerate.
528 * xc16x-asm.c: Regenerate.
529 * xstormy16-asm.c: Regenerate.
530
6ffe3d99
NC		 5312010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
532
533 PR gas/11673
534 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
535
09ec0d17
NC		 5362010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
537
538 PR binutils/11676
539 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
540
e01d869a
AM		 5412010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
542
543 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
544 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
545 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
546 touch floating point regs and are enabled by COM, PPC or PPCCOM.
547 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
548 Treat lwsync as msync on e500.
549
1f4e4950
MGD		 5502010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
551
552 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
553
9d82ec38
MGD		 5542010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
555
e01d869a 556 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
9d82ec38
MGD		 557 constants is the same on 32-bit and 64-bit hosts.
558
c3a6ea62 5592010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
d8b24b95
NC		 560
561 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
562 .short directives so that they can be reassembled.
563
9db8dccb
CM		 5642010-05-26 Catherine Moore <clm@codesourcery.com>
565 David Ung <davidu@mips.com>
566
567 * mips-opc.c: Change membership to I1 for instructions ssnop and
568 ehb.
569
dfc8cf43
L		 5702010-05-26 H.J. Lu <hongjiu.lu@intel.com>
571
572 * i386-dis.c (sib): New.
573 (get_sib): Likewise.
574 (print_insn): Call get_sib.
575 OP_E_memory): Use sib.
576
f79e2745
CM		 5772010-05-26 Catherine Moore <clm@codesoourcery.com>
578
579 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
580 * mips-opc.c (I16): Remove.
581 (mips_builtin_op): Reclassify jalx.
582
51b5d4a8
AM		 5832010-05-19 Alan Modra <amodra@gmail.com>
584
585 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
586 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
587
85d4ac0b
AM		 5882010-05-13 Alan Modra <amodra@gmail.com>
589
590 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
591
4547cb56
NC		 5922010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
593
594 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
595 format.
596 (print_insn_thumb16): Add support for new %W format.
597
6540b386
TG		 5982010-05-07 Tristan Gingold <gingold@adacore.com>
599
600 * Makefile.in: Regenerate with automake 1.11.1.
601 * aclocal.m4: Ditto.
602
3e01a7fd
NC		 6032010-05-05 Nick Clifton <nickc@redhat.com>
604
605 * po/es.po: Updated Spanish translation.
606
9c9c98a5
NC		 6072010-04-22 Nick Clifton <nickc@redhat.com>
608
609 * po/opcodes.pot: Updated by the Translation project.
610 * po/vi.po: Updated Vietnamese translation.
611
f07af43e
L		 6122010-04-16 H.J. Lu <hongjiu.lu@intel.com>
613
614 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
615 bits in opcode.
616
3d540e93
NC		 6172010-04-09 Nick Clifton <nickc@redhat.com>
618
619 * i386-dis.c (print_insn): Remove unused variable op.
620 (OP_sI): Remove unused variable mask.
621
397841b5
AM		 6222010-04-07 Alan Modra <amodra@gmail.com>
623
624 * configure: Regenerate.
625
cee62821
PB		 6262010-04-06 Peter Bergner <bergner@vnet.ibm.com>
627
628 * ppc-opc.c (RBOPT): New define.
629 ("dccci"): Enable for PPCA2. Make operands optional.
630 ("iccci"): Likewise. Do not deprecate for PPC476.
631
accf4463
NC		 6322010-04-02 Masaki Muranaka <monaka@monami-software.com>
633
634 * cr16-opc.c (cr16_instruction): Fix typo in comment.
635
40b36596
JM		 6362010-03-25 Joseph Myers <joseph@codesourcery.com>
637
638 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
639 * Makefile.in: Regenerate.
640 * configure.in (bfd_tic6x_arch): New.
641 * configure: Regenerate.
642 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
643 (disassembler): Handle TI C6X.
644 * tic6x-dis.c: New.
645
1985c81c
MF		 6462010-03-24 Mike Frysinger <vapier@gentoo.org>
647
648 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
649
f66187fd
JM		 6502010-03-23 Joseph Myers <joseph@codesourcery.com>
651
652 * dis-buf.c (buffer_read_memory): Give error for reading just
653 before the start of memory.
654
ce7d077e
SP		 6552010-03-22 Sebastian Pop <sebastian.pop@amd.com>
656 Quentin Neill <quentin.neill@amd.com>
657
658 * i386-dis.c (OP_LWP_I): Removed.
659 (reg_table): Do not use OP_LWP_I, use Iq.
660 (OP_LWPCB_E): Remove use of names16.
661 (OP_LWP_E): Same.
662 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
663 should not set the Vex.length bit.
664 * i386-tbl.h: Regenerated.
665
63d0fa4e
AM		 6662010-02-25 Edmar Wienskoski <edmar@freescale.com>
667
668 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
669
c060226a
NC		 6702010-02-24 Nick Clifton <nickc@redhat.com>
671
672 PR binutils/6773
673 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
674 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
675 (thumb32_opcodes): Likewise.
676
ab7875de
NC		 6772010-02-15 Nick Clifton <nickc@redhat.com>
678
679 * po/vi.po: Updated Vietnamese translation.
680
fee1d3e8
DE		 6812010-02-12 Doug Evans <dje@sebabeach.org>
682
683 * lm32-opinst.c: Regenerate.
684
37ec9240
DE		 6852010-02-11 Doug Evans <dje@sebabeach.org>
686
9468ae89
DE		 687 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
688 (print_address): Delete CGEN_PRINT_ADDRESS.
689 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
690 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
691 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
692 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
693
37ec9240
DE		 694 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
695 * frv-desc.c, * frv-desc.h, * frv-opc.c,
696 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
697 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
698 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
699 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
700 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
701 * mep-desc.c, * mep-desc.h, * mep-opc.c,
702 * mt-desc.c, * mt-desc.h, * mt-opc.c,
703 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
704 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
705 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
706
c75ef631
L		 7072010-02-11 H.J. Lu <hongjiu.lu@intel.com>
708
709 * i386-dis.c: Update copyright.
710 * i386-gen.c: Likewise.
711 * i386-opc.h: Likewise.
712 * i386-opc.tbl: Likewise.
713
a683cc34
SP		 7142010-02-10 Quentin Neill <quentin.neill@amd.com>
715 Sebastian Pop <sebastian.pop@amd.com>
716
717 * i386-dis.c (OP_EX_VexImmW): Reintroduced
718 function to handle 5th imm8 operand.
719 (PREFIX_VEX_3A48): Added.
720 (PREFIX_VEX_3A49): Added.
721 (VEX_W_3A48_P_2): Added.
722 (VEX_W_3A49_P_2): Added.
723 (prefix table): Added entries for PREFIX_VEX_3A48
724 and PREFIX_VEX_3A49.
725 (vex table): Added entries for VEX_W_3A48_P_2 and
726 and VEX_W_3A49_P_2.
727 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
728 for Vec_Imm4 operands.
729 * i386-opc.h (enum): Added Vec_Imm4.
730 (i386_operand_type): Added vec_imm4.
731 * i386-opc.tbl: Add entries for vpermilp[ds].
732 * i386-init.h: Regenerated.
733 * i386-tbl.h: Regenerated.
734
cdc51b07
RS		 7352010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
736
737 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
738 and "pwr7". Move "a2" into alphabetical order.
739
ce3d2015
AM		 7402010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
741
742 * ppc-dis.c (ppc_opts): Add titan entry.
743 * ppc-opc.c (TITAN, MULHW): Define.
744 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
745
68339fdf
SP		 7462010-02-03 Quentin Neill <quentin.neill@amd.com>
747
748 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
749 to CPU_BDVER1_FLAGS
750 * i386-init.h: Regenerated.
751
f3d55a94
AG		 7522010-02-03 Anthony Green <green@moxielogic.com>
753
754 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
755 0x0f, and make 0x00 an illegal instruction.
756
b0e28b39
DJ		 7572010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
758
759 * opcodes/arm-dis.c (struct arm_private_data): New.
760 (print_insn_coprocessor, print_insn_arm): Update to use struct
761 arm_private_data.
762 (is_mapping_symbol, get_map_sym_type): New functions.
763 (get_sym_code_type): Check the symbol's section. Do not check
764 mapping symbols.
765 (print_insn): Default to disassembling ARM mode code. Check
766 for mapping symbols separately from other symbols. Use
767 struct arm_private_data.
768
1c480963
L		 7692010-01-28 H.J. Lu <hongjiu.lu@intel.com>
770
771 * i386-dis.c (EXVexWdqScalar): New.
772 (vex_scalar_w_dq_mode): Likewise.
773 (prefix_table): Update entries for PREFIX_VEX_3899,
774 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
775 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
776 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
777 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
778 (intel_operand_size): Handle vex_scalar_w_dq_mode.
779 (OP_EX): Likewise.
780
539f890d
L		 7812010-01-27 H.J. Lu <hongjiu.lu@intel.com>
782
783 * i386-dis.c (XMScalar): New.
784 (EXdScalar): Likewise.
785 (EXqScalar): Likewise.
786 (EXqScalarS): Likewise.
787 (VexScalar): Likewise.
788 (EXdVexScalarS): Likewise.
789 (EXqVexScalarS): Likewise.
790 (XMVexScalar): Likewise.
791 (scalar_mode): Likewise.
792 (d_scalar_mode): Likewise.
793 (d_scalar_swap_mode): Likewise.
794 (q_scalar_mode): Likewise.
795 (q_scalar_swap_mode): Likewise.
796 (vex_scalar_mode): Likewise.
797 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
798 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
799 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
800 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
801 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
802 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
803 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
804 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
805 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
806 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
807 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
808 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
809 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
810 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
811 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
812 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
813 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
814 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
815 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
816 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
817 q_scalar_mode, q_scalar_swap_mode.
818 (OP_XMM): Handle scalar_mode.
819 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
820 and q_scalar_swap_mode.
821 (OP_VEX): Handle vex_scalar_mode.
822
208b4d78
L		 8232010-01-24 H.J. Lu <hongjiu.lu@intel.com>
824
825 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
826
448b213a
L		 8272010-01-24 H.J. Lu <hongjiu.lu@intel.com>
828
829 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
830
47cf8fa0
L		 8312010-01-24 H.J. Lu <hongjiu.lu@intel.com>
832
833 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
834
592d1631
L		 8352010-01-24 H.J. Lu <hongjiu.lu@intel.com>
836
837 * i386-dis.c (Bad_Opcode): New.
838 (bad_opcode): Likewise.
839 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
840 (dis386_twobyte): Likewise.
841 (reg_table): Likewise.
842 (prefix_table): Likewise.
843 (x86_64_table): Likewise.
844 (vex_len_table): Likewise.
845 (vex_w_table): Likewise.
846 (mod_table): Likewise.
847 (rm_table): Likewise.
848 (float_reg): Likewise.
849 (reg_table): Remove trailing "(bad)" entries.
850 (prefix_table): Likewise.
851 (x86_64_table): Likewise.
852 (vex_len_table): Likewise.
853 (vex_w_table): Likewise.
854 (mod_table): Likewise.
855 (rm_table): Likewise.
856 (get_valid_dis386): Handle bytemode 0.
857
712366da
L		 8582010-01-23 H.J. Lu <hongjiu.lu@intel.com>
859
860 * i386-opc.h (VEXScalar): New.
861
862 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
863 instructions.
864 * i386-tbl.h: Regenerated.
865
706e8205 8662010-01-21 H.J. Lu <hongjiu.lu@intel.com>
73bb6729
L		 867
868 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
869
870 * i386-opc.tbl: Add xsave64 and xrstor64.
871 * i386-tbl.h: Regenerated.
872
99ea83aa
NC		 8732010-01-20 Nick Clifton <nickc@redhat.com>
874
875 PR 11170
876 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
877 based post-indexed addressing.
878
a6461c02
SP		 8792010-01-15 Sebastian Pop <sebastian.pop@amd.com>
880
881 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
882 * i386-tbl.h: Regenerated.
883
a2a7d12c
L		 8842010-01-14 H.J. Lu <hongjiu.lu@intel.com>
885
886 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
887 comments.
888
b9733481
L		 8892010-01-14 H.J. Lu <hongjiu.lu@intel.com>
890
891 * i386-dis.c (names_mm): New.
892 (intel_names_mm): Likewise.
893 (att_names_mm): Likewise.
894 (names_xmm): Likewise.
895 (intel_names_xmm): Likewise.
896 (att_names_xmm): Likewise.
897 (names_ymm): Likewise.
898 (intel_names_ymm): Likewise.
899 (att_names_ymm): Likewise.
900 (print_insn): Set names_mm, names_xmm and names_ymm.
901 (OP_MMX): Use names_mm, names_xmm and names_ymm.
902 (OP_XMM): Likewise.
903 (OP_EM): Likewise.
904 (OP_EMC): Likewise.
905 (OP_MXC): Likewise.
906 (OP_EX): Likewise.
907 (XMM_Fixup): Likewise.
908 (OP_VEX): Likewise.
909 (OP_EX_VexReg): Likewise.
910 (OP_Vex_2src): Likewise.
911 (OP_Vex_2src_1): Likewise.
912 (OP_Vex_2src_2): Likewise.
913 (OP_REG_VexI4): Likewise.
914
5e6718e4
L		 9152010-01-13 H.J. Lu <hongjiu.lu@intel.com>
916
917 * i386-dis.c (print_insn): Update comments.
918
d869730d
L		 9192010-01-12 H.J. Lu <hongjiu.lu@intel.com>
920
921 * i386-dis.c (rex_original): Removed.
922 (ckprefix): Remove rex_original.
923 (print_insn): Update comments.
924
3725885a
RW		 9252010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
926
927 * Makefile.in: Regenerate.
928 * configure: Regenerate.
929
b7cd1872
DE		 9302010-01-07 Doug Evans <dje@sebabeach.org>
931
932 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
933 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
934 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
935 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
936 * xstormy16-ibld.c: Regenerate.
937
69dd9865
SP		 9382010-01-06 Quentin Neill <quentin.neill@amd.com>
939
940 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
941 * i386-init.h: Regenerated.
942
e3e535bc
NC		 9432010-01-06 Daniel Gutson <dgutson@codesourcery.com>
944
945 * arm-dis.c (print_insn): Fixed search for next symbol and data
946 dumping condition, and the initial mapping symbol state.
947
fe8afbc4
DE		 9482010-01-05 Doug Evans <dje@sebabeach.org>
949
950 * cgen-ibld.in: #include "cgen/basic-modes.h".
951 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
952 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
953 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
954 * xstormy16-ibld.c: Regenerate.
955
2edcd244
NC		 9562010-01-04 Nick Clifton <nickc@redhat.com>
957
958 PR 11123
959 * arm-dis.c (print_insn_coprocessor): Initialise value.
960
0dc93057
AM		 9612010-01-04 Edmar Wienskoski <edmar@freescale.com>
962
963 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
964
05994f45
DE		 9652010-01-02 Doug Evans <dje@sebabeach.org>
966
967 * cgen-asm.in: Update copyright year.
968 * cgen-dis.in: Update copyright year.
969 * cgen-ibld.in: Update copyright year.
970 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
971 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
972 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
973 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
974 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
975 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
976 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
977 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
978 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
979 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
980 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
981 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
982 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
983 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
984 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
985 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
986 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
987 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
988 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
989 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
990 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2426c15f 991
43ecc30f 992For older changes see ChangeLog-2009
252b5132
RH		 993\f
994Local Variables:
2f6d2f85
NC		 995mode: change-log
996left-margin: 8
997fill-column: 74
252b5132
RH		 998version-control: never
999End:
GDB Binutils - Deliverables
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