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2005-01-19 Fred Fish <fnf@specifixinc.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
986e18a5
FF		 12005-01-19 Fred Fish <fnf@specifixinc.com>
2
3 * mips-dis.c (no_aliases): New disassembly option flag.
4 (set_default_mips_dis_options): Init no_aliases to zero.
5 (parse_mips_dis_option): Handle no-aliases option.
6 (print_insn_mips): Ignore table entries that are aliases
7 if no_aliases is set.
8 (print_insn_mips16): Ditto.
9 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
10 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
11 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
12 * mips16-opc.c (mips16_opcodes): Ditto.
13
e38bc3b5
NC		 142005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
15
16 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
17 (inheritance diagram): Add missing edge.
18 (arch_sh1_up): Rename arch_sh_up to match external name to make life
19 easier for the testsuite.
20 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
21 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
22 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
23 arch_sh2a_or_sh4_up child.
24 (sh_table): Do renaming as above.
25 Correct comment for ldc.l for gas testsuite to read.
26 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
27 Correct comments for movy.w and movy.l for gas testsuite to read.
28 Correct comments for fmov.d and fmov.s for gas testsuite to read.
29
9df48ba9
L		 302005-01-12 H.J. Lu <hongjiu.lu@intel.com>
31
32 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
33
2033b4b9
L		 342005-01-12 H.J. Lu <hongjiu.lu@intel.com>
35
36 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
37
0bcb06d2
AS		 382005-01-10 Andreas Schwab <schwab@suse.de>
39
40 * disassemble.c (disassemble_init_for_target) <case
41 bfd_arch_ia64>: Set skip_zeroes to 16.
42 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
43
47add74d
TL		 442004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
45
46 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
47
246f4c05
SS		 482004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
49
50 * avr-dis.c: Prettyprint. Added printing of symbol names in all
51 memory references. Convert avr_operand() to C90 formatting.
52
0e1200e5
TL		 532004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
54
55 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
56
89a649f7
TL		 572004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
58
59 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
60 (no_op_insn): Initialize array with instructions that have no
61 operands.
62 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
63
6255809c
RE		 642004-11-29 Richard Earnshaw <rearnsha@arm.com>
65
66 * arm-dis.c: Correct top-level comment.
67
2fbad815
RE		 682004-11-27 Richard Earnshaw <rearnsha@arm.com>
69
70 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
71 architecuture defining the insn.
72 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 73 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
74 field.
2fbad815
RE		 75 Also include opcode/arm.h.
76 * Makefile.am (arm-dis.lo): Update dependency list.
77 * Makefile.in: Regenerate.
78
d81acc42
NC		 792004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
80
81 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
82 reflect the change to the short immediate syntax.
83
ca4f2377
AM		 842004-11-19 Alan Modra <amodra@bigpond.net.au>
85
5da8bf1b
AM		 86 * or32-opc.c (debug): Warning fix.
87 * po/POTFILES.in: Regenerate.
88
ca4f2377
AM		 89 * maxq-dis.c: Formatting.
90 (print_insn): Warning fix.
91
b7693d02
DJ		 922004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
93
94 * arm-dis.c (WORD_ADDRESS): Define.
95 (print_insn): Use it. Correct big-endian end-of-section handling.
96
300dac7e
NC		 972004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
98 Vineet Sharma <vineets@noida.hcltech.com>
99
100 * maxq-dis.c: New file.
101 * disassemble.c (ARCH_maxq): Define.
102 (disassembler): Add 'print_insn_maxq_little' for handling maxq
103 instructions..
104 * configure.in: Add case for bfd_maxq_arch.
105 * configure: Regenerate.
106 * Makefile.am: Add support for maxq-dis.c
107 * Makefile.in: Regenerate.
108 * aclocal.m4: Regenerate.
109
42048ee7
TL		 1102004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
111
112 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
113 mode.
114 * crx-dis.c: Likewise.
115
bd21e58e
HPN		 1162004-11-04 Hans-Peter Nilsson <hp@axis.com>
117
118 Generally, handle CRISv32.
119 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
120 (struct cris_disasm_data): New type.
121 (format_reg, format_hex, cris_constraint, print_flags)
122 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
123 callers changed.
124 (format_sup_reg, print_insn_crisv32_with_register_prefix)
125 (print_insn_crisv32_without_register_prefix)
126 (print_insn_crisv10_v32_with_register_prefix)
127 (print_insn_crisv10_v32_without_register_prefix)
128 (cris_parse_disassembler_options): New functions.
129 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
130 parameter. All callers changed.
131 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
132 failure.
133 (cris_constraint) <case 'Y', 'U'>: New cases.
134 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
135 for constraint 'n'.
136 (print_with_operands) <case 'Y'>: New case.
137 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
138 <case 'N', 'Y', 'Q'>: New cases.
139 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
140 (print_insn_cris_with_register_prefix)
141 (print_insn_cris_without_register_prefix): Call
142 cris_parse_disassembler_options.
143 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
144 for CRISv32 and the size of immediate operands. New v32-only
145 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
146 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
147 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
148 Change brp to be v3..v10.
149 (cris_support_regs): New vector.
150 (cris_opcodes): Update head comment. New format characters '[',
151 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
152 Add new opcodes for v32 and adjust existing opcodes to accommodate
153 differences to earlier variants.
154 (cris_cond15s): New vector.
155
9306ca4a
JB		 1562004-11-04 Jan Beulich <jbeulich@novell.com>
157
158 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
159 (indirEb): Remove.
160 (Mp): Use f_mode rather than none at all.
161 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
162 replaces what previously was x_mode; x_mode now means 128-bit SSE
163 operands.
164 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
165 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
166 pinsrw's second operand is Edqw.
167 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
168 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
169 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
170 mode when an operand size override is present or always suffixing.
171 More instructions will need to be added to this group.
172 (putop): Handle new macro chars 'C' (short/long suffix selector),
173 'I' (Intel mode override for following macro char), and 'J' (for
174 adding the 'l' prefix to far branches in AT&T mode). When an
175 alternative was specified in the template, honor macro character when
176 specified for Intel mode.
177 (OP_E): Handle new *_mode values. Correct pointer specifications for
178 memory operands. Consolidate output of index register.
179 (OP_G): Handle new *_mode values.
180 (OP_I): Handle const_1_mode.
181 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
182 respective opcode prefix bits have been consumed.
183 (OP_EM, OP_EX): Provide some default handling for generating pointer
184 specifications.
185
f39c96a9
TL		 1862004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
187
188 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
189 COP_INST macro.
190
812337be
TL		 1912004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
192
193 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
194 (getregliststring): Support HI/LO and user registers.
195 * crx-opc.c (crx_instruction): Update data structure according to the
196 rearrangement done in CRX opcode header file.
197 (crx_regtab): Likewise.
198 (crx_optab): Likewise.
199 (crx_instruction): Reorder load/stor instructions, remove unsupported
200 formats.
201 support new Co-Processor instruction 'cpi'.
202
4030fa5a
NC		 2032004-10-27 Nick Clifton <nickc@redhat.com>
204
205 * opcodes/iq2000-asm.c: Regenerate.
206 * opcodes/iq2000-desc.c: Regenerate.
207 * opcodes/iq2000-desc.h: Regenerate.
208 * opcodes/iq2000-dis.c: Regenerate.
209 * opcodes/iq2000-ibld.c: Regenerate.
210 * opcodes/iq2000-opc.c: Regenerate.
211 * opcodes/iq2000-opc.h: Regenerate.
212
fc3d45e8
TL		 2132004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
214
215 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
216 us4, us5 (respectively).
217 Remove unsupported 'popa' instruction.
218 Reverse operands order in store co-processor instructions.
219
3c55da70
AM		 2202004-10-15 Alan Modra <amodra@bigpond.net.au>
221
222 * Makefile.am: Run "make dep-am"
223 * Makefile.in: Regenerate.
224
7fa3d080
BW		 2252004-10-12 Bob Wilson <bob.wilson@acm.org>
226
227 * xtensa-dis.c: Use ISO C90 formatting.
228
e612bb4d
AM		 2292004-10-09 Alan Modra <amodra@bigpond.net.au>
230
231 * ppc-opc.c: Revert 2004-09-09 change.
232
43cd72b9
BW		 2332004-10-07 Bob Wilson <bob.wilson@acm.org>
234
235 * xtensa-dis.c (state_names): Delete.
236 (fetch_data): Use xtensa_isa_maxlength.
237 (print_xtensa_operand): Replace operand parameter with opcode/operand
238 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
239 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
240 instruction bundles. Use xmalloc instead of malloc.
241
bbac1f2a
NC		 2422004-10-07 David Gibson <david@gibson.dropbear.id.au>
243
244 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
245 initializers.
246
48c9f030
NC		 2472004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
248
249 * crx-opc.c (crx_instruction): Support Co-processor insns.
250 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
251 (getregliststring): Change function to use the above enum.
252 (print_arg): Handle CO-Processor insns.
253 (crx_cinvs): Add 'b' option to invalidate the branch-target
254 cache.
255
12c64a4e
AH		 2562004-10-06 Aldy Hernandez <aldyh@redhat.com>
257
258 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
259 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
260 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
261 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
262 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
263
14127cc4
NC		 2642004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
265
266 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
267 rather than add it.
268
0dd132b6
NC		 2692004-09-30 Paul Brook <paul@codesourcery.com>
270
271 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
272 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
273
3f85e526
L		 2742004-09-17 H.J. Lu <hongjiu.lu@intel.com>
275
276 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
277 (CONFIG_STATUS_DEPENDENCIES): New.
278 (Makefile): Removed.
279 (config.status): Likewise.
280 * Makefile.in: Regenerated.
281
8ae85421
AM		 2822004-09-17 Alan Modra <amodra@bigpond.net.au>
283
284 * Makefile.am: Run "make dep-am".
285 * Makefile.in: Regenerate.
286 * aclocal.m4: Regenerate.
287 * configure: Regenerate.
288 * po/POTFILES.in: Regenerate.
289 * po/opcodes.pot: Regenerate.
290
24443139
AS		 2912004-09-11 Andreas Schwab <schwab@suse.de>
292
293 * configure: Rebuild.
294
2a309db0
AM		 2952004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
296
297 * ppc-opc.c (L): Make this field not optional.
298
42851540
NC		 2992004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
300
301 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
302 Fix parameter to 'm[t|f]csr' insns.
303
979273e3
NN		 3042004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
305
306 * configure.in: Autoupdate to autoconf 2.59.
307 * aclocal.m4: Rebuild with aclocal 1.4p6.
308 * configure: Rebuild with autoconf 2.59.
309 * Makefile.in: Rebuild with automake 1.4p6 (picking up
310 bfd changes for autoconf 2.59 on the way).
311 * config.in: Rebuild with autoheader 2.59.
312
ac28a1cb
RS		 3132004-08-27 Richard Sandiford <rsandifo@redhat.com>
314
315 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
316
30d1c836
ML		 3172004-07-30 Michal Ludvig <mludvig@suse.cz>
318
319 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
320 (GRPPADLCK2): New define.
321 (twobyte_has_modrm): True for 0xA6.
322 (grps): GRPPADLCK2 for opcode 0xA6.
323
0b0ac059
AO		 3242004-07-29 Alexandre Oliva <aoliva@redhat.com>
325
326 Introduce SH2a support.
327 * sh-opc.h (arch_sh2a_base): Renumber.
328 (arch_sh2a_nofpu_base): Remove.
329 (arch_sh_base_mask): Adjust.
330 (arch_opann_mask): New.
331 (arch_sh2a, arch_sh2a_nofpu): Adjust.
332 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
333 (sh_table): Adjust whitespace.
334 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
335 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
336 instruction list throughout.
337 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
338 of arch_sh2a in instruction list throughout.
339 (arch_sh2e_up): Accomodate above changes.
340 (arch_sh2_up): Ditto.
341 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
342 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
343 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
344 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
345 * sh-opc.h (arch_sh2a_nofpu): New.
346 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
347 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
348 instruction.
349 2004-01-20 DJ Delorie <dj@redhat.com>
350 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
351 2003-12-29 DJ Delorie <dj@redhat.com>
352 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
353 sh_opcode_info, sh_table): Add sh2a support.
354 (arch_op32): New, to tag 32-bit opcodes.
355 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
356 2003-12-02 Michael Snyder <msnyder@redhat.com>
357 * sh-opc.h (arch_sh2a): Add.
358 * sh-dis.c (arch_sh2a): Handle.
359 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
360
670ec21d
NC		 3612004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
362
363 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
364
ed049af3
NC		 3652004-07-22 Nick Clifton <nickc@redhat.com>
366
367 PR/280
368 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
369 insns - this is done by objdump itself.
370 * h8500-dis.c (print_insn_h8500): Likewise.
371
20f0a1fc
NC		 3722004-07-21 Jan Beulich <jbeulich@novell.com>
373
374 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
375 regardless of address size prefix in effect.
376 (ptr_reg): Size or address registers does not depend on rex64, but
377 on the presence of an address size override.
378 (OP_MMX): Use rex.x only for xmm registers.
379 (OP_EM): Use rex.z only for xmm registers.
380
6f14957b
MR		 3812004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
382
383 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
384 move/branch operations to the bottom so that VR5400 multimedia
385 instructions take precedence in disassembly.
386
1586d91e
MR		 3872004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
388
389 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
390 ISA-specific "break" encoding.
391
982de27a
NC		 3922004-07-13 Elvis Chiang <elvisfb@gmail.com>
393
394 * arm-opc.h: Fix typo in comment.
395
4300ab10
AS		 3962004-07-11 Andreas Schwab <schwab@suse.de>
397
398 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
399
8577e690
AS		 4002004-07-09 Andreas Schwab <schwab@suse.de>
401
402 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
403
1fe1f39c
NC		 4042004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
405
406 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
407 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
408 (crx-dis.lo): New target.
409 (crx-opc.lo): Likewise.
410 * Makefile.in: Regenerate.
411 * configure.in: Handle bfd_crx_arch.
412 * configure: Regenerate.
413 * crx-dis.c: New file.
414 * crx-opc.c: New file.
415 * disassemble.c (ARCH_crx): Define.
416 (disassembler): Handle ARCH_crx.
417
7a33b495
JW		 4182004-06-29 James E Wilson <wilson@specifixinc.com>
419
420 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
421 * ia64-asmtab.c: Regnerate.
422
98e69875
AM		 4232004-06-28 Alan Modra <amodra@bigpond.net.au>
424
425 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
426 (extract_fxm): Don't test dialect.
427 (XFXFXM_MASK): Include the power4 bit.
428 (XFXM): Add p4 param.
429 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
430
a53b85e2
AO		 4312004-06-27 Alexandre Oliva <aoliva@redhat.com>
432
433 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
434 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
435
d0618d1c
AM		 4362004-06-26 Alan Modra <amodra@bigpond.net.au>
437
438 * ppc-opc.c (BH, XLBH_MASK): Define.
439 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
440
1d9f512f
AM		 4412004-06-24 Alan Modra <amodra@bigpond.net.au>
442
443 * i386-dis.c (x_mode): Comment.
444 (two_source_ops): File scope.
445 (float_mem): Correct fisttpll and fistpll.
446 (float_mem_mode): New table.
447 (dofloat): Use it.
448 (OP_E): Correct intel mode PTR output.
449 (ptr_reg): Use open_char and close_char.
450 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
451 operands. Set two_source_ops.
452
52886d70
AM		 4532004-06-15 Alan Modra <amodra@bigpond.net.au>
454
455 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
456 instead of _raw_size.
457
bad9ceea
JJ		 4582004-06-08 Jakub Jelinek <jakub@redhat.com>
459
460 * ia64-gen.c (in_iclass): Handle more postinc st
461 and ld variants.
462 * ia64-asmtab.c: Rebuilt.
463
0451f5df
MS		 4642004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
465
466 * s390-opc.txt: Correct architecture mask for some opcodes.
467 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
468 in the esa mode as well.
469
f6f9408f
JR		 4702004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
471
472 * sh-dis.c (target_arch): Make unsigned.
473 (print_insn_sh): Replace (most of) switch with a call to
474 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
475 * sh-opc.h: Redefine architecture flags values.
476 Add sh3-nommu architecture.
477 Reorganise <arch>_up macros so they make more visual sense.
478 (SH_MERGE_ARCH_SET): Define new macro.
479 (SH_VALID_BASE_ARCH_SET): Likewise.
480 (SH_VALID_MMU_ARCH_SET): Likewise.
481 (SH_VALID_CO_ARCH_SET): Likewise.
482 (SH_VALID_ARCH_SET): Likewise.
483 (SH_MERGE_ARCH_SET_VALID): Likewise.
484 (SH_ARCH_SET_HAS_FPU): Likewise.
485 (SH_ARCH_SET_HAS_DSP): Likewise.
486 (SH_ARCH_UNKNOWN_ARCH): Likewise.
487 (sh_get_arch_from_bfd_mach): Add prototype.
488 (sh_get_arch_up_from_bfd_mach): Likewise.
489 (sh_get_bfd_mach_from_arch_set): Likewise.
490 (sh_merge_bfd_arc): Likewise.
491
be8c092b
NC		 4922004-05-24 Peter Barada <peter@the-baradas.com>
493
494 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
495 into new match_insn_m68k function. Loop over canidate
496 matches and select first that completely matches.
497 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
498 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
499 to verify addressing for MAC/EMAC.
500 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
501 reigster halves since 'fpu' and 'spl' look misleading.
502 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
503 * m68k-opc.c: Rearragne mac/emac cases to use longest for
504 first, tighten up match masks.
505 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
506 'size' from special case code in print_insn_m68k to
507 determine decode size of insns.
508
a30e9cc4
AM		 5092004-05-19 Alan Modra <amodra@bigpond.net.au>
510
511 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
512 well as when -mpower4.
513
9598fbe5
NC		 5142004-05-13 Nick Clifton <nickc@redhat.com>
515
516 * po/fr.po: Updated French translation.
517
6b6e92f4
NC		 5182004-05-05 Peter Barada <peter@the-baradas.com>
519
520 * m68k-dis.c(print_insn_m68k): Add new chips, use core
521 variants in arch_mask. Only set m68881/68851 for 68k chips.
522 * m68k-op.c: Switch from ColdFire chips to core variants.
523
a404d431
AM		 5242004-05-05 Alan Modra <amodra@bigpond.net.au>
525
a30e9cc4 526 PR 147.
a404d431
AM		 527 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
528
f3806e43
BE		 5292004-04-29 Ben Elliston <bje@au.ibm.com>
530
520ceea4
BE		 531 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
532 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 533
1f1799d5
KK		 5342004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
535
536 * sh-dis.c (print_insn_sh): Print the value in constant pool
537 as a symbol if it looks like a symbol.
538
fd99574b
NC		 5392004-04-22 Peter Barada <peter@the-baradas.com>
540
541 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
542 appropriate ColdFire architectures.
543 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
544 mask addressing.
545 Add EMAC instructions, fix MAC instructions. Remove
546 macmw/macml/msacmw/msacml instructions since mask addressing now
547 supported.
548
b4781d44
JJ		 5492004-04-20 Jakub Jelinek <jakub@redhat.com>
550
551 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
552 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
553 suffix. Use fmov*x macros, create all 3 fpsize variants in one
554 macro. Adjust all users.
555
91809fda
NC		 5562004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
557
558 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
559 separately.
560
f4453dfa
NC		 5612004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
562
563 * m32r-asm.c: Regenerate.
564
9b0de91a
SS		 5652004-03-29 Stan Shebs <shebs@apple.com>
566
567 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
568 used.
569
e20c0b3d
AM		 5702004-03-19 Alan Modra <amodra@bigpond.net.au>
571
572 * aclocal.m4: Regenerate.
573 * config.in: Regenerate.
574 * configure: Regenerate.
575 * po/POTFILES.in: Regenerate.
576 * po/opcodes.pot: Regenerate.
577
fdd12ef3
AM		 5782004-03-16 Alan Modra <amodra@bigpond.net.au>
579
580 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
581 PPC_OPERANDS_GPR_0.
582 * ppc-opc.c (RA0): Define.
583 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
584 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 585 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 586
2dc111b3 5872004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 588
589 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 590
7bfeee7b
AM		 5912004-03-15 Alan Modra <amodra@bigpond.net.au>
592
593 * sparc-dis.c (print_insn_sparc): Update getword prototype.
594
7ffdda93
ML		 5952004-03-12 Michal Ludvig <mludvig@suse.cz>
596
597 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 598 (grps): Delete GRPPLOCK entry.
7ffdda93 599
cc0ec051
AM		 6002004-03-12 Alan Modra <amodra@bigpond.net.au>
601
602 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
603 (M, Mp): Use OP_M.
604 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
605 (GRPPADLCK): Define.
606 (dis386): Use NOP_Fixup on "nop".
607 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
608 (twobyte_has_modrm): Set for 0xa7.
609 (padlock_table): Delete. Move to..
610 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
611 and clflush.
612 (print_insn): Revert PADLOCK_SPECIAL code.
613 (OP_E): Delete sfence, lfence, mfence checks.
614
4fd61dcb
JJ		 6152004-03-12 Jakub Jelinek <jakub@redhat.com>
616
617 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
618 (INVLPG_Fixup): New function.
619 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
620
0f10071e
ML		 6212004-03-12 Michal Ludvig <mludvig@suse.cz>
622
623 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
624 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
625 (padlock_table): New struct with PadLock instructions.
626 (print_insn): Handle PADLOCK_SPECIAL.
627
c02908d2
AM		 6282004-03-12 Alan Modra <amodra@bigpond.net.au>
629
630 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
631 (OP_E): Twiddle clflush to sfence here.
632
d5bb7600
NC		 6332004-03-08 Nick Clifton <nickc@redhat.com>
634
635 * po/de.po: Updated German translation.
636
ae51a426
JR		 6372003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
638
639 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
640 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
641 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
642 accordingly.
643
676a64f4
RS		 6442004-03-01 Richard Sandiford <rsandifo@redhat.com>
645
646 * frv-asm.c: Regenerate.
647 * frv-desc.c: Regenerate.
648 * frv-desc.h: Regenerate.
649 * frv-dis.c: Regenerate.
650 * frv-ibld.c: Regenerate.
651 * frv-opc.c: Regenerate.
652 * frv-opc.h: Regenerate.
653
c7a48b9a
RS		 6542004-03-01 Richard Sandiford <rsandifo@redhat.com>
655
656 * frv-desc.c, frv-opc.c: Regenerate.
657
8ae0baa2
RS		 6582004-03-01 Richard Sandiford <rsandifo@redhat.com>
659
660 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
661
ce11586c
JR		 6622004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
663
664 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
665 Also correct mistake in the comment.
666
6a5709a5
JR		 6672004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
668
669 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
670 ensure that double registers have even numbers.
671 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
672 that reserved instruction 0xfffd does not decode the same
673 as 0xfdfd (ftrv).
674 * sh-opc.h: Add REG_N_D nibble type and use it whereever
675 REG_N refers to a double register.
676 Add REG_N_B01 nibble type and use it instead of REG_NM
677 in ftrv.
678 Adjust the bit patterns in a few comments.
679
e5d2b64f 6802004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 681
682 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 683
1f04b05f
AH		 6842004-02-20 Aldy Hernandez <aldyh@redhat.com>
685
686 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
687
2f3b8700
AH		 6882004-02-20 Aldy Hernandez <aldyh@redhat.com>
689
690 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
691
f0b26da6 6922004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 693
694 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
695 mtivor32, mtivor33, mtivor34.
f0b26da6 696
23d59c56 6972004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 698
699 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 700
34920d91
NC		 7012004-02-10 Petko Manolov <petkan@nucleusys.com>
702
703 * arm-opc.h Maverick accumulator register opcode fixes.
704
44d86481
BE		 7052004-02-13 Ben Elliston <bje@wasabisystems.com>
706
707 * m32r-dis.c: Regenerate.
708
17707c23
MS		 7092004-01-27 Michael Snyder <msnyder@redhat.com>
710
711 * sh-opc.h (sh_table): "fsrra", not "fssra".
712
fe3a9bc4
NC		 7132004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
714
715 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
716 contraints.
717
ff24f124
JJ		 7182004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
719
720 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
721
a02a862a
AM		 7222004-01-19 Alan Modra <amodra@bigpond.net.au>
723
724 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
725 1. Don't print scale factor on AT&T mode when index missing.
726
d164ea7f
AO		 7272004-01-16 Alexandre Oliva <aoliva@redhat.com>
728
729 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
730 when loaded into XR registers.
731
cb10e79a
RS		 7322004-01-14 Richard Sandiford <rsandifo@redhat.com>
733
734 * frv-desc.h: Regenerate.
735 * frv-desc.c: Regenerate.
736 * frv-opc.c: Regenerate.
737
f532f3fa
MS		 7382004-01-13 Michael Snyder <msnyder@redhat.com>
739
740 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
741
e45d0630
PB		 7422004-01-09 Paul Brook <paul@codesourcery.com>
743
744 * arm-opc.h (arm_opcodes): Move generic mcrr after known
745 specific opcodes.
746
3ba7a1aa
DJ		 7472004-01-07 Daniel Jacobowitz <drow@mvista.com>
748
749 * Makefile.am (libopcodes_la_DEPENDENCIES)
750 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
751 comment about the problem.
752 * Makefile.in: Regenerate.
753
ba2d3f07
AO		 7542004-01-06 Alexandre Oliva <aoliva@redhat.com>
755
756 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
757 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
758 cut&paste errors in shifting/truncating numerical operands.
759 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
760 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
761 (parse_uslo16): Likewise.
762 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
763 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
764 (parse_s12): Likewise.
765 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
766 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
767 (parse_uslo16): Likewise.
768 (parse_uhi16): Parse gothi and gotfuncdeschi.
769 (parse_d12): Parse got12 and gotfuncdesc12.
770 (parse_s12): Likewise.
771
3ab48931
NC		 7722004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
773
774 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
775 instruction which looks similar to an 'rla' instruction.
a0bd404e 776
c9e214e5 777For older changes see ChangeLog-0203
252b5132
RH		 778\f
779Local Variables:
2f6d2f85
NC		 780mode: change-log
781left-margin: 8
782fill-column: 74
252b5132
RH		 783version-control: never
784End:
GDB Binutils - Deliverables
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