projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gas/testsuite/
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
989993d8
JB		 12011-09-28 Jan Beulich <jbeulich@suse.com>
2
3 * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
4 RBX): New.
5 (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
6 (powerpc_opcodes): Use RAX for second and RBXC for third operand of
7 lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
8 lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
9 mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
10 on DFP quad instructions.
11
92a7795b
DM		 122011-09-27 David S. Miller <davem@davemloft.net>
13
14 * sparc-opc.c (sparc_opcodes): Fix random instruction to write
15 to a float instead of an integer register.
16
e91d1076
DM		 172011-09-26 David S. Miller <davem@davemloft.net>
18
19 * sparc-opc.c (sparc_opcodes): Add integer multiply-add
20 instructions.
21
9e8c70f9
DM		 222011-09-21 David S. Miller <davem@davemloft.net>
23
24 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
25 bits. Fix "fchksm16" mnemonic.
26
9bf29d72
DM		 272011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
28
29 The changes below bring 'mov' and 'ticc' instructions into line
30 with the V8 SPARC Architecture Manual.
31 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
32 * sparc-opc.c (sparc_opcodes): Add alias entries for
33 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
34 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
35 * sparc-opc.c (sparc_opcodes): Move/Change entries for
36 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
37 and 'mov imm,%tbr'.
38 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
39 mov aliases.
40
8dbb9eb3
DM		 41 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
42 This has been reported as being accepted by the Sun assmebler.
43
cdf49201
DM		 442011-09-08 David S. Miller <davem@davemloft.net>
45
46 * sparc-opc.c (pdistn): Destination is integer not float register.
47
96e67898
AS		 482011-09-07 Andreas Schwab <schwab@linux-m68k.org>
49
b2ea1829 50 PR gas/13145
96e67898
AS		 51 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
52
7cf80422
NC		 532011-08-26 Nick Clifton <nickc@redhat.com>
54
55 * po/es.po: Updated Spanish translation.
56
dc15e575
NC		 572011-08-22 Nick Clifton <nickc@redhat.com>
58
59 * Makefile.am (CPUDIR): Redfine to point to top level cpu
60 directory.
61 (stamp-frv): Use CPUDIR.
62 (stamp-iq2000): Likewise.
63 (stamp-lm32): Likewise.
64 (stamp-m32c): Likewise.
65 (stamp-mt): Likewise.
66 (stamp-xc16x): Likewise.
67 * Makefile.in: Regenerate.
68
dec0624d
MR		 692011-08-09 Chao-ying Fu <fu@mips.com>
70 Maciej W. Rozycki <macro@codesourcery.com>
71
72 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
73 and "mips64r2".
74 (print_insn_args, print_insn_micromips): Handle MCU.
75 * micromips-opc.c (MC): New macro.
76 (micromips_opcodes): Add "aclr", "aset" and "iret".
77 * mips-opc.c (MC): New macro.
78 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
79
2b0c8b40
MR		 802011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
81
82 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
83 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
84 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
85 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
86 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
87 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
88 (WR_s): Update macro.
89 (micromips_opcodes): Update register use flags of: "addiu",
90 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
91 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
92 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
93 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
94 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
95 "swm" and "xor" instructions.
96
ea783ef3
DM		 972011-08-05 David S. Miller <davem@davemloft.net>
98
99 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
100 (X_RS3): New macro.
101 (print_insn_sparc): Handle '4', '5', and '(' format codes.
102 Accept %asr numbers below 28.
103 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
104 instructions.
105
3929df09
QN		 1062011-08-02 Quentin Neill <quentin.neill@amd.com>
107
108 * i386-dis.c (xop_table): Remove spurious bextr insn.
109
d7921315
L		 1102011-08-01 H.J. Lu <hongjiu.lu@intel.com>
111
112 PR ld/13048
113 * i386-dis.c (print_insn): Optimize info->mach check.
114
00f51a41
L		 1152011-08-01 H.J. Lu <hongjiu.lu@intel.com>
116
117 PR gas/13046
118 * i386-opc.tbl: Add Disp32S to 64bit call.
119 * i386-tbl.h: Regenerated.
120
df58fc94
RS		 1212011-07-24 Chao-ying Fu <fu@mips.com>
122 Maciej W. Rozycki <macro@codesourcery.com>
123
124 * micromips-opc.c: New file.
125 * mips-dis.c (micromips_to_32_reg_b_map): New array.
126 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
127 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
128 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
129 (micromips_to_32_reg_q_map): Likewise.
130 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
131 (micromips_ase): New variable.
132 (is_micromips): New function.
133 (set_default_mips_dis_options): Handle microMIPS ASE.
134 (print_insn_micromips): New function.
135 (is_compressed_mode_p): Likewise.
136 (_print_insn_mips): Handle microMIPS instructions.
137 * Makefile.am (CFILES): Add micromips-opc.c.
138 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
139 * Makefile.in: Regenerate.
140 * configure: Regenerate.
141
142 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
143 (micromips_to_32_reg_i_map): Likewise.
144 (micromips_to_32_reg_m_map): Likewise.
145 (micromips_to_32_reg_n_map): New macro.
146
bcd530a7
RS		 1472011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
148
149 * mips-opc.c (NODS): New macro.
150 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
151 (DSP_VOLA): Likewise.
152 (mips_builtin_opcodes): Add NODS annotation to "deret" and
153 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
154 place of TRAP for "wait", "waiti" and "yield".
155 * mips16-opc.c (NODS): New macro.
156 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
157 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
158 "restore" and "save".
159
7a9068fe
L		 1602011-07-22 H.J. Lu <hongjiu.lu@intel.com>
161
162 * configure.in: Handle bfd_k1om_arch.
163 * configure: Regenerated.
164
165 * disassemble.c (disassembler): Handle bfd_k1om_arch.
166
167 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
168 bfd_mach_k1om_intel_syntax.
169
170 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
171 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
172 (cpu_flags): Add CpuK1OM.
173
174 * i386-opc.h (CpuK1OM): New.
175 (i386_cpu_flags): Add cpuk1om.
176
177 * i386-init.h: Regenerated.
178 * i386-tbl.h: Likewise.
179
1b93226d
NC		 1802011-07-12 Nick Clifton <nickc@redhat.com>
181
182 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
183 accidental change.
184
5d73b1f1
NC		 1852011-07-01 Nick Clifton <nickc@redhat.com>
186
187 PR binutils/12329
188 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
189 insns using post-increment addressing.
190
182ae480
L		 1912011-06-30 H.J. Lu <hongjiu.lu@intel.com>
192
193 * i386-dis.c (vex_len_table): Update rorxS.
194
4cb0953d
L		 1952011-06-30 H.J. Lu <hongjiu.lu@intel.com>
196
197 AVX Programming Reference (June, 2011)
198 * i386-dis.c (vex_len_table): Correct rorxS.
199
200 * i386-opc.tbl: Correct rorx.
201 * i386-tbl.h: Regenerated.
202
906efcbc
L		 2032011-06-29 H.J. Lu <hongjiu.lu@intel.com>
204
205 * tilegx-opc.c (find_opcode): Replace "index" with "i".
206 * tilepro-opc.c (find_opcode): Likewise.
207
ceb94aa5
RS		 2082011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
209
210 * mips16-opc.c (jalrc, jrc): Move earlier in file.
211
f7002f42
L		 2122011-06-21 H.J. Lu <hongjiu.lu@intel.com>
213
214 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
215 PREFIX_VEX_0F388E.
216
56300268
AS		 2172011-06-17 Andreas Schwab <schwab@redhat.com>
218
219 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
220 (MOSTLYCLEANFILES): ... here.
221 * Makefile.in: Regenerate.
222
bcf2cf9f
AM		 2232011-06-14 Alan Modra <amodra@gmail.com>
224
225 * Makefile.in: Regenerate.
226
aa137e4d
NC		 2272011-06-13 Walter Lee <walt@tilera.com>
228
229 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
230 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
231 * Makefile.in: Regenerate.
232 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
233 * configure: Regenerate.
234 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
235 * po/POTFILES.in: Regenerate.
236 * tilegx-dis.c: New file.
237 * tilegx-opc.c: New file.
238 * tilepro-dis.c: New file.
239 * tilepro-opc.c: New file.
240
6c30d220
L		 2412011-06-10 H.J. Lu <hongjiu.lu@intel.com>
242
243 AVX Programming Reference (June, 2011)
244 * i386-dis.c (XMGatherQ): New.
245 * i386-dis.c (EXxmm_mb): New.
246 (EXxmm_mb): Likewise.
247 (EXxmm_mw): Likewise.
248 (EXxmm_md): Likewise.
249 (EXxmm_mq): Likewise.
250 (EXxmmdw): Likewise.
251 (EXxmmqd): Likewise.
252 (VexGatherQ): Likewise.
253 (MVexVSIBDWpX): Likewise.
254 (MVexVSIBQWpX): Likewise.
255 (xmm_mb_mode): Likewise.
256 (xmm_mw_mode): Likewise.
257 (xmm_md_mode): Likewise.
258 (xmm_mq_mode): Likewise.
259 (xmmdw_mode): Likewise.
260 (xmmqd_mode): Likewise.
261 (ymmxmm_mode): Likewise.
262 (vex_vsib_d_w_dq_mode): Likewise.
263 (vex_vsib_q_w_dq_mode): Likewise.
264 (MOD_VEX_0F385A_PREFIX_2): Likewise.
265 (MOD_VEX_0F388C_PREFIX_2): Likewise.
266 (MOD_VEX_0F388E_PREFIX_2): Likewise.
267 (PREFIX_0F3882): Likewise.
268 (PREFIX_VEX_0F3816): Likewise.
269 (PREFIX_VEX_0F3836): Likewise.
270 (PREFIX_VEX_0F3845): Likewise.
271 (PREFIX_VEX_0F3846): Likewise.
272 (PREFIX_VEX_0F3847): Likewise.
273 (PREFIX_VEX_0F3858): Likewise.
274 (PREFIX_VEX_0F3859): Likewise.
275 (PREFIX_VEX_0F385A): Likewise.
276 (PREFIX_VEX_0F3878): Likewise.
277 (PREFIX_VEX_0F3879): Likewise.
278 (PREFIX_VEX_0F388C): Likewise.
279 (PREFIX_VEX_0F388E): Likewise.
280 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
281 (PREFIX_VEX_0F38F5): Likewise.
282 (PREFIX_VEX_0F38F6): Likewise.
283 (PREFIX_VEX_0F3A00): Likewise.
284 (PREFIX_VEX_0F3A01): Likewise.
285 (PREFIX_VEX_0F3A02): Likewise.
286 (PREFIX_VEX_0F3A38): Likewise.
287 (PREFIX_VEX_0F3A39): Likewise.
288 (PREFIX_VEX_0F3A46): Likewise.
289 (PREFIX_VEX_0F3AF0): Likewise.
290 (VEX_LEN_0F3816_P_2): Likewise.
291 (VEX_LEN_0F3819_P_2): Likewise.
292 (VEX_LEN_0F3836_P_2): Likewise.
293 (VEX_LEN_0F385A_P_2_M_0): Likewise.
294 (VEX_LEN_0F38F5_P_0): Likewise.
295 (VEX_LEN_0F38F5_P_1): Likewise.
296 (VEX_LEN_0F38F5_P_3): Likewise.
297 (VEX_LEN_0F38F6_P_3): Likewise.
298 (VEX_LEN_0F38F7_P_1): Likewise.
299 (VEX_LEN_0F38F7_P_2): Likewise.
300 (VEX_LEN_0F38F7_P_3): Likewise.
301 (VEX_LEN_0F3A00_P_2): Likewise.
302 (VEX_LEN_0F3A01_P_2): Likewise.
303 (VEX_LEN_0F3A38_P_2): Likewise.
304 (VEX_LEN_0F3A39_P_2): Likewise.
305 (VEX_LEN_0F3A46_P_2): Likewise.
306 (VEX_LEN_0F3AF0_P_3): Likewise.
307 (VEX_W_0F3816_P_2): Likewise.
308 (VEX_W_0F3818_P_2): Likewise.
309 (VEX_W_0F3819_P_2): Likewise.
310 (VEX_W_0F3836_P_2): Likewise.
311 (VEX_W_0F3846_P_2): Likewise.
312 (VEX_W_0F3858_P_2): Likewise.
313 (VEX_W_0F3859_P_2): Likewise.
314 (VEX_W_0F385A_P_2_M_0): Likewise.
315 (VEX_W_0F3878_P_2): Likewise.
316 (VEX_W_0F3879_P_2): Likewise.
317 (VEX_W_0F3A00_P_2): Likewise.
318 (VEX_W_0F3A01_P_2): Likewise.
319 (VEX_W_0F3A02_P_2): Likewise.
320 (VEX_W_0F3A38_P_2): Likewise.
321 (VEX_W_0F3A39_P_2): Likewise.
322 (VEX_W_0F3A46_P_2): Likewise.
323 (MOD_VEX_0F3818_PREFIX_2): Removed.
324 (MOD_VEX_0F3819_PREFIX_2): Likewise.
325 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
326 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
327 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
328 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
329 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
330 (VEX_LEN_0F3A0E_P_2): Likewise.
331 (VEX_LEN_0F3A0F_P_2): Likewise.
332 (VEX_LEN_0F3A42_P_2): Likewise.
333 (VEX_LEN_0F3A4C_P_2): Likewise.
334 (VEX_W_0F3818_P_2_M_0): Likewise.
335 (VEX_W_0F3819_P_2_M_0): Likewise.
336 (prefix_table): Updated.
337 (three_byte_table): Likewise.
338 (vex_table): Likewise.
339 (vex_len_table): Likewise.
340 (vex_w_table): Likewise.
341 (mod_table): Likewise.
342 (putop): Handle "LW".
343 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
344 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
345 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
346 (OP_EX): Likewise.
347 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
348 vex_vsib_q_w_dq_mode.
349 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
350 (OP_VEX): Likewise.
351
352 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
353 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
354 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
355 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
356 (opcode_modifiers): Add VecSIB.
357
358 * i386-opc.h (CpuAVX2): New.
359 (CpuBMI2): Likewise.
360 (CpuLZCNT): Likewise.
361 (CpuINVPCID): Likewise.
362 (VecSIB128): Likewise.
363 (VecSIB256): Likewise.
364 (VecSIB): Likewise.
365 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
366 (i386_opcode_modifier): Add vecsib.
367
368 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
369 * i386-init.h: Regenerated.
370 * i386-tbl.h: Likewise.
371
d535accd
QN		 3722011-06-03 Quentin Neill <quentin.neill@amd.com>
373
374 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
375 * i386-init.h: Regenerated.
376
f8b960bc
NC		 3772011-06-03 Nick Clifton <nickc@redhat.com>
378
379 PR binutils/12752
380 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
381 computing address offsets.
382 (print_arm_address): Likewise.
383 (print_insn_arm): Likewise.
384 (print_insn_thumb16): Likewise.
385 (print_insn_thumb32): Likewise.
386
26d97720
NS		 3872011-06-02 Jie Zhang <jie@codesourcery.com>
388 Nathan Sidwell <nathan@codesourcery.com>
389 Maciej Rozycki <macro@codesourcery.com>
390
391 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
392 as address offset.
393 (print_arm_address): Likewise. Elide positive #0 appropriately.
394 (print_insn_arm): Likewise.
395
f8b960bc
NC		 3962011-06-02 Nick Clifton <nickc@redhat.com>
397
398 PR gas/12752
399 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
400 passed to print_address_func.
401
cc643b88
NC		 4022011-06-02 Nick Clifton <nickc@redhat.com>
403
404 * arm-dis.c: Fix spelling mistakes.
405 * op/opcodes.pot: Regenerate.
406
c8fa16ed
AK		 4072011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
408
409 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
410 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
411 * s390-opc.txt: Fix cxr instruction type.
412
5e4b319c
AK		 4132011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
414
415 * s390-opc.c: Add new instruction types marking register pair
416 operands.
417 * s390-opc.txt: Match instructions having register pair operands
418 to the new instruction types.
419
fda544a2
NC		 4202011-05-19 Nick Clifton <nickc@redhat.com>
421
422 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
423 operands.
424
4cab4add
QN		 4252011-05-10 Quentin Neill <quentin.neill@amd.com>
426
427 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
428 * i386-init.h: Regenerated.
429
b4e7b885
NC		 4302011-04-27 Nick Clifton <nickc@redhat.com>
431
432 * po/da.po: Updated Danish translation.
433
2f7f7710
AM		 4342011-04-26 Anton Blanchard <anton@samba.org>
435
436 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
437
9887672f
DD		 4382011-04-21 DJ Delorie <dj@redhat.com>
439
440 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
441 * rx-decode.c: Regenerate.
442
3251b375
L		 4432011-04-20 H.J. Lu <hongjiu.lu@intel.com>
444
445 * i386-init.h: Regenerated.
446
b13a3ca6
QN		 4472011-04-19 Quentin Neill <quentin.neill@amd.com>
448
449 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
450 from bdver1 flags.
451
7d063384
NC		 4522011-04-13 Nick Clifton <nickc@redhat.com>
453
454 * v850-dis.c (disassemble): Always print a closing square brace if
455 an opening square brace was printed.
456
32a94698
NC		 4572011-04-12 Nick Clifton <nickc@redhat.com>
458
459 PR binutils/12534
460 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
461 patterns.
462 (print_insn_thumb32): Handle %L.
463
d2cd1205
JB		 4642011-04-11 Julian Brown <julian@codesourcery.com>
465
466 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
467 (print_insn_thumb32): Add APSR bitmask support.
468
1fbaefec
PB		 4692011-04-07 Paul Carroll<pcarroll@codesourcery.com>
470
471 * arm-dis.c (print_insn): init vars moved into private_data structure.
472
67171547
MF		 4732011-03-24 Mike Frysinger <vapier@gentoo.org>
474
475 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
476
8cc66334
EW		 4772011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
478
479 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
480 post-increment to support LPM Z+ instruction. Add support for 'E'
481 constraint for DES instruction.
482 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
483
34e77a92
RS		 4842011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
485
486 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
487
35fc36a8
RS		 4882011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
489
490 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
491 Use branch types instead.
492 (print_insn): Likewise.
493
0067d8fc
MR		 4942011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
495
496 * mips-opc.c (mips_builtin_opcodes): Correct register use
497 annotation of "alnv.ps".
498
3eebd5eb
MR		 4992011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
500
501 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
502
500cccad
MF		 5032011-02-22 Mike Frysinger <vapier@gentoo.org>
504
505 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
506
f5caf9f4
MF		 5072011-02-22 Mike Frysinger <vapier@gentoo.org>
508
509 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
510
e5bc4265
MF		 5112011-02-19 Mike Frysinger <vapier@gentoo.org>
512
513 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
514 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
515 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
516 exception, end_of_registers, msize, memory, bfd_mach.
517 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
518 LB0REG, LC1REG, LT1REG, LB1REG): Delete
519 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
520 (get_allreg): Change to new defines. Fallback to abort().
521
602427c4
MF		 5222011-02-14 Mike Frysinger <vapier@gentoo.org>
523
524 * bfin-dis.c: Add whitespace/parenthesis where needed.
525
298c1ec2
MF		 5262011-02-14 Mike Frysinger <vapier@gentoo.org>
527
528 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
529 than 7.
530
822ce8ee
RW		 5312011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
532
533 * configure: Regenerate.
534
13c02f06
MF		 5352011-02-13 Mike Frysinger <vapier@gentoo.org>
536
537 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
538
4db66394
MF		 5392011-02-13 Mike Frysinger <vapier@gentoo.org>
540
541 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
542 dregs only when P is set, and dregs_lo otherwise.
543
36f44611
MF		 5442011-02-13 Mike Frysinger <vapier@gentoo.org>
545
546 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
547
9805c0a5
MF		 5482011-02-12 Mike Frysinger <vapier@gentoo.org>
549
550 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
551
43a6aa65
MF		 5522011-02-12 Mike Frysinger <vapier@gentoo.org>
553
554 * bfin-dis.c (machine_registers): Delete REG_GP.
555 (reg_names): Delete "GP".
556 (decode_allregs): Change REG_GP to REG_LASTREG.
557
26bb3ddd
MF		 5582011-02-12 Mike Frysinger <vapier@gentoo.org>
559
89c0d58c
MR		 560 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
561 M_IH, M_IU): Delete.
26bb3ddd 562
69b8ea4a
MF		 5632011-02-11 Mike Frysinger <vapier@gentoo.org>
564
565 * bfin-dis.c (reg_names): Add const.
566 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
567 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
568 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
569 decode_counters, decode_allregs): Likewise.
570
42d5f9c6
MS		 5712011-02-09 Michael Snyder <msnyder@vmware.com>
572
56300268 573 * i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6
MS		 574 truncated addresses.
575 (print_insn): Fix indentation off-by-one.
576
4be0c941
NC		 5772011-02-01 Nick Clifton <nickc@redhat.com>
578
579 * po/da.po: Updated Danish translation.
580
6b069ee7
AM		 5812011-01-21 Dave Murphy <davem@devkitpro.org>
582
583 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
584
e3949f17
L		 5852011-01-18 H.J. Lu <hongjiu.lu@intel.com>
586
587 * i386-dis.c (sIbT): New.
588 (b_T_mode): Likewise.
589 (dis386): Replace sIb with sIbT on "pushT".
590 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
591 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
592
752573b2
JK		 5932011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
594
595 * i386-init.h: Regenerated.
596 * i386-tbl.h: Regenerated
597
2a2a0f38
QN		 5982011-01-17 Quentin Neill <quentin.neill@amd.com>
599
600 * i386-dis.c (REG_XOP_TBM_01): New.
601 (REG_XOP_TBM_02): New.
602 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
603 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
604 entries, and add bextr instruction.
605
606 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
607 (cpu_flags): Add CpuTBM.
608
609 * i386-opc.h (CpuTBM) New.
610 (i386_cpu_flags): Add bit cputbm.
611
612 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
613 blcs, blsfill, blsic, t1mskc, and tzmsk.
614
90d6ff62
DD		 6152011-01-12 DJ Delorie <dj@redhat.com>
616
617 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
618
c95354ed
MX		 6192011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
620
621 * mips-dis.c (print_insn_args): Adjust the value to print the real
622 offset for "+c" argument.
623
f7465604
NC		 6242011-01-10 Nick Clifton <nickc@redhat.com>
625
626 * po/da.po: Updated Danish translation.
627
639e30d2
NS		 6282011-01-05 Nathan Sidwell <nathan@codesourcery.com>
629
630 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
631
f12dc422
L		 6322011-01-04 H.J. Lu <hongjiu.lu@intel.com>
633
634 * i386-dis.c (REG_VEX_38F3): New.
635 (PREFIX_0FBC): Likewise.
636 (PREFIX_VEX_38F2): Likewise.
637 (PREFIX_VEX_38F3_REG_1): Likewise.
638 (PREFIX_VEX_38F3_REG_2): Likewise.
639 (PREFIX_VEX_38F3_REG_3): Likewise.
640 (PREFIX_VEX_38F7): Likewise.
641 (VEX_LEN_38F2_P_0): Likewise.
642 (VEX_LEN_38F3_R_1_P_0): Likewise.
643 (VEX_LEN_38F3_R_2_P_0): Likewise.
644 (VEX_LEN_38F3_R_3_P_0): Likewise.
645 (VEX_LEN_38F7_P_0): Likewise.
646 (dis386_twobyte): Use PREFIX_0FBC.
647 (reg_table): Add REG_VEX_38F3.
648 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
649 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
650 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
651 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
652 PREFIX_VEX_38F7.
653 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
654 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
655 VEX_LEN_38F7_P_0.
656
657 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
658 (cpu_flags): Add CpuBMI.
659
660 * i386-opc.h (CpuBMI): New.
661 (i386_cpu_flags): Add cpubmi.
662
663 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
664 * i386-init.h: Regenerated.
665 * i386-tbl.h: Likewise.
666
cb21baef
L		 6672011-01-04 H.J. Lu <hongjiu.lu@intel.com>
668
669 * i386-dis.c (VexGdq): New.
670 (OP_VEX): Handle dq_mode.
671
0db46eb4
L		 6722011-01-01 H.J. Lu <hongjiu.lu@intel.com>
673
674 * i386-gen.c (process_copyright): Update copyright to 2011.
675
9e9e0820 676For older changes see ChangeLog-2010
252b5132
RH		 677\f
678Local Variables:
2f6d2f85
NC		 679mode: change-log
680left-margin: 8
681fill-column: 74
252b5132
RH		 682version-control: never
683End:
GDB Binutils - Deliverables
This page took 0.66044 seconds and 4 git commands to generate.