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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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9a2c7088
MR		 12010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
2
3 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
4 type and delay slot determination.
5 (print_insn_mips16): Extend branch instruction type and delay
6 slot determination to cover all instructions.
7 * mips16-opc.c (BR): Remove macro.
8 (UBR, CBR): New macros.
9 (mips16_opcodes): Update branch annotation for "b", "beqz",
10 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
11 and "jrc".
12
d7d9a9f8
L		 132010-07-05 H.J. Lu <hongjiu.lu@intel.com>
14
15 AVX Programming Reference (June, 2010)
16 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
17 * i386-opc.tbl: Likewise.
18 * i386-tbl.h: Regenerated.
19
77321f53
L		 202010-07-05 H.J. Lu <hongjiu.lu@intel.com>
21
22 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
23
7102e95e
AS		 242010-07-03 Andreas Schwab <schwab@linux-m68k.org>
25
26 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
27 ppc_cpu_t before inverting.
3a5530ea
AS		 28 (ppc_parse_cpu): Likewise.
29 (print_insn_powerpc): Likewise.
7102e95e 30
bdc70b4a
AM		 312010-07-03 Alan Modra <amodra@gmail.com>
32
33 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
34 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
35 (PPC64, MFDEC2): Update.
36 (NON32, NO371): Define.
37 (powerpc_opcode): Update to not use old opcode flags, and avoid
38 -m601 duplicates.
39
21375995
DD		 402010-07-03 DJ Delorie <dj@delorie.com>
41
42 * m32c-ibld.c: Regenerate.
43
81a0b7e2
AM		 442010-07-03 Alan Modra <amodra@gmail.com>
45
46 * ppc-opc.c (PWR2COM): Define.
47 (PPCPWR2): Add PPC_OPCODE_COMMON.
48 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
49 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
50 "rac" from -mcom.
51
c7b8aa3a
L		 522010-07-01 H.J. Lu <hongjiu.lu@intel.com>
53
54 AVX Programming Reference (June, 2010)
55 * i386-dis.c (PREFIX_0FAE_REG_0): New.
56 (PREFIX_0FAE_REG_1): Likewise.
57 (PREFIX_0FAE_REG_2): Likewise.
58 (PREFIX_0FAE_REG_3): Likewise.
59 (PREFIX_VEX_3813): Likewise.
60 (PREFIX_VEX_3A1D): Likewise.
61 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
62 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
63 PREFIX_VEX_3A1D.
64 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
65 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
66 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
67
68 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
69 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
70 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
71
72 * i386-opc.h (CpuXsaveopt): New.
77321f53 73 (CpuFSGSBase): Likewise.
c7b8aa3a
L		 74 (CpuRdRnd): Likewise.
75 (CpuF16C): Likewise.
76 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
77 cpuf16c.
78
79 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
80 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
a00eb5e8
L		 81 * i386-init.h: Regenerated.
82 * i386-tbl.h: Likewise.
c7b8aa3a 83
09a8ad8d
AM		 842010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
85
86 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
87 and mtocrf on EFS.
88
360cfc9c
AM		 892010-06-29 Alan Modra <amodra@gmail.com>
90
91 * maxq-dis.c: Delete file.
92 * Makefile.am: Remove references to maxq.
93 * configure.in: Likewise.
94 * disassemble.c: Likewise.
95 * Makefile.in: Regenerate.
96 * configure: Regenerate.
97 * po/POTFILES.in: Regenerate.
98
dc898d5e
AM		 992010-06-29 Alan Modra <amodra@gmail.com>
100
101 * mep-dis.c: Regenerate.
102
8e560766
MGD		 1032010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
104
105 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
106
c7e2358a
AM		 1072010-06-27 Alan Modra <amodra@gmail.com>
108
109 * arc-dis.c (arc_sprintf): Delete set but unused variables.
110 (decodeInstr): Likewise.
111 * dlx-dis.c (print_insn_dlx): Likewise.
112 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
113 * maxq-dis.c (check_move, print_insn): Likewise.
114 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
115 * msp430-dis.c (msp430_branchinstr): Likewise.
116 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
117 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
118 * sparc-dis.c (print_insn_sparc): Likewise.
119 * fr30-asm.c: Regenerate.
120 * frv-asm.c: Regenerate.
121 * ip2k-asm.c: Regenerate.
122 * iq2000-asm.c: Regenerate.
123 * lm32-asm.c: Regenerate.
124 * m32c-asm.c: Regenerate.
125 * m32r-asm.c: Regenerate.
126 * mep-asm.c: Regenerate.
127 * mt-asm.c: Regenerate.
128 * openrisc-asm.c: Regenerate.
129 * xc16x-asm.c: Regenerate.
130 * xstormy16-asm.c: Regenerate.
131
6ffe3d99
NC		 1322010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
133
134 PR gas/11673
135 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
136
09ec0d17
NC		 1372010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
138
139 PR binutils/11676
140 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
141
e01d869a
AM		 1422010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
143
144 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
145 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
146 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
147 touch floating point regs and are enabled by COM, PPC or PPCCOM.
148 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
149 Treat lwsync as msync on e500.
150
1f4e4950
MGD		 1512010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
152
153 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
154
9d82ec38
MGD		 1552010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
156
e01d869a 157 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
9d82ec38
MGD		 158 constants is the same on 32-bit and 64-bit hosts.
159
c3a6ea62 1602010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
d8b24b95
NC		 161
162 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
163 .short directives so that they can be reassembled.
164
9db8dccb
CM		 1652010-05-26 Catherine Moore <clm@codesourcery.com>
166 David Ung <davidu@mips.com>
167
168 * mips-opc.c: Change membership to I1 for instructions ssnop and
169 ehb.
170
dfc8cf43
L		 1712010-05-26 H.J. Lu <hongjiu.lu@intel.com>
172
173 * i386-dis.c (sib): New.
174 (get_sib): Likewise.
175 (print_insn): Call get_sib.
176 OP_E_memory): Use sib.
177
f79e2745
CM		 1782010-05-26 Catherine Moore <clm@codesoourcery.com>
179
180 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
181 * mips-opc.c (I16): Remove.
182 (mips_builtin_op): Reclassify jalx.
183
51b5d4a8
AM		 1842010-05-19 Alan Modra <amodra@gmail.com>
185
186 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
187 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
188
85d4ac0b
AM		 1892010-05-13 Alan Modra <amodra@gmail.com>
190
191 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
192
4547cb56
NC		 1932010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
194
195 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
196 format.
197 (print_insn_thumb16): Add support for new %W format.
198
6540b386
TG		 1992010-05-07 Tristan Gingold <gingold@adacore.com>
200
201 * Makefile.in: Regenerate with automake 1.11.1.
202 * aclocal.m4: Ditto.
203
3e01a7fd
NC		 2042010-05-05 Nick Clifton <nickc@redhat.com>
205
206 * po/es.po: Updated Spanish translation.
207
9c9c98a5
NC		 2082010-04-22 Nick Clifton <nickc@redhat.com>
209
210 * po/opcodes.pot: Updated by the Translation project.
211 * po/vi.po: Updated Vietnamese translation.
212
f07af43e
L		 2132010-04-16 H.J. Lu <hongjiu.lu@intel.com>
214
215 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
216 bits in opcode.
217
3d540e93
NC		 2182010-04-09 Nick Clifton <nickc@redhat.com>
219
220 * i386-dis.c (print_insn): Remove unused variable op.
221 (OP_sI): Remove unused variable mask.
222
397841b5
AM		 2232010-04-07 Alan Modra <amodra@gmail.com>
224
225 * configure: Regenerate.
226
cee62821
PB		 2272010-04-06 Peter Bergner <bergner@vnet.ibm.com>
228
229 * ppc-opc.c (RBOPT): New define.
230 ("dccci"): Enable for PPCA2. Make operands optional.
231 ("iccci"): Likewise. Do not deprecate for PPC476.
232
accf4463
NC		 2332010-04-02 Masaki Muranaka <monaka@monami-software.com>
234
235 * cr16-opc.c (cr16_instruction): Fix typo in comment.
236
40b36596
JM		 2372010-03-25 Joseph Myers <joseph@codesourcery.com>
238
239 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
240 * Makefile.in: Regenerate.
241 * configure.in (bfd_tic6x_arch): New.
242 * configure: Regenerate.
243 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
244 (disassembler): Handle TI C6X.
245 * tic6x-dis.c: New.
246
1985c81c
MF		 2472010-03-24 Mike Frysinger <vapier@gentoo.org>
248
249 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
250
f66187fd
JM		 2512010-03-23 Joseph Myers <joseph@codesourcery.com>
252
253 * dis-buf.c (buffer_read_memory): Give error for reading just
254 before the start of memory.
255
ce7d077e
SP		 2562010-03-22 Sebastian Pop <sebastian.pop@amd.com>
257 Quentin Neill <quentin.neill@amd.com>
258
259 * i386-dis.c (OP_LWP_I): Removed.
260 (reg_table): Do not use OP_LWP_I, use Iq.
261 (OP_LWPCB_E): Remove use of names16.
262 (OP_LWP_E): Same.
263 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
264 should not set the Vex.length bit.
265 * i386-tbl.h: Regenerated.
266
63d0fa4e
AM		 2672010-02-25 Edmar Wienskoski <edmar@freescale.com>
268
269 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
270
c060226a
NC		 2712010-02-24 Nick Clifton <nickc@redhat.com>
272
273 PR binutils/6773
274 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
275 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
276 (thumb32_opcodes): Likewise.
277
ab7875de
NC		 2782010-02-15 Nick Clifton <nickc@redhat.com>
279
280 * po/vi.po: Updated Vietnamese translation.
281
fee1d3e8
DE		 2822010-02-12 Doug Evans <dje@sebabeach.org>
283
284 * lm32-opinst.c: Regenerate.
285
37ec9240
DE		 2862010-02-11 Doug Evans <dje@sebabeach.org>
287
9468ae89
DE		 288 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
289 (print_address): Delete CGEN_PRINT_ADDRESS.
290 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
291 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
292 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
293 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
294
37ec9240
DE		 295 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
296 * frv-desc.c, * frv-desc.h, * frv-opc.c,
297 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
298 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
299 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
300 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
301 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
302 * mep-desc.c, * mep-desc.h, * mep-opc.c,
303 * mt-desc.c, * mt-desc.h, * mt-opc.c,
304 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
305 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
306 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
307
c75ef631
L		 3082010-02-11 H.J. Lu <hongjiu.lu@intel.com>
309
310 * i386-dis.c: Update copyright.
311 * i386-gen.c: Likewise.
312 * i386-opc.h: Likewise.
313 * i386-opc.tbl: Likewise.
314
a683cc34
SP		 3152010-02-10 Quentin Neill <quentin.neill@amd.com>
316 Sebastian Pop <sebastian.pop@amd.com>
317
318 * i386-dis.c (OP_EX_VexImmW): Reintroduced
319 function to handle 5th imm8 operand.
320 (PREFIX_VEX_3A48): Added.
321 (PREFIX_VEX_3A49): Added.
322 (VEX_W_3A48_P_2): Added.
323 (VEX_W_3A49_P_2): Added.
324 (prefix table): Added entries for PREFIX_VEX_3A48
325 and PREFIX_VEX_3A49.
326 (vex table): Added entries for VEX_W_3A48_P_2 and
327 and VEX_W_3A49_P_2.
328 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
329 for Vec_Imm4 operands.
330 * i386-opc.h (enum): Added Vec_Imm4.
331 (i386_operand_type): Added vec_imm4.
332 * i386-opc.tbl: Add entries for vpermilp[ds].
333 * i386-init.h: Regenerated.
334 * i386-tbl.h: Regenerated.
335
cdc51b07
RS		 3362010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
337
338 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
339 and "pwr7". Move "a2" into alphabetical order.
340
ce3d2015
AM		 3412010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
342
343 * ppc-dis.c (ppc_opts): Add titan entry.
344 * ppc-opc.c (TITAN, MULHW): Define.
345 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
346
68339fdf
SP		 3472010-02-03 Quentin Neill <quentin.neill@amd.com>
348
349 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
350 to CPU_BDVER1_FLAGS
351 * i386-init.h: Regenerated.
352
f3d55a94
AG		 3532010-02-03 Anthony Green <green@moxielogic.com>
354
355 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
356 0x0f, and make 0x00 an illegal instruction.
357
b0e28b39
DJ		 3582010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
359
360 * opcodes/arm-dis.c (struct arm_private_data): New.
361 (print_insn_coprocessor, print_insn_arm): Update to use struct
362 arm_private_data.
363 (is_mapping_symbol, get_map_sym_type): New functions.
364 (get_sym_code_type): Check the symbol's section. Do not check
365 mapping symbols.
366 (print_insn): Default to disassembling ARM mode code. Check
367 for mapping symbols separately from other symbols. Use
368 struct arm_private_data.
369
1c480963
L		 3702010-01-28 H.J. Lu <hongjiu.lu@intel.com>
371
372 * i386-dis.c (EXVexWdqScalar): New.
373 (vex_scalar_w_dq_mode): Likewise.
374 (prefix_table): Update entries for PREFIX_VEX_3899,
375 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
376 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
377 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
378 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
379 (intel_operand_size): Handle vex_scalar_w_dq_mode.
380 (OP_EX): Likewise.
381
539f890d
L		 3822010-01-27 H.J. Lu <hongjiu.lu@intel.com>
383
384 * i386-dis.c (XMScalar): New.
385 (EXdScalar): Likewise.
386 (EXqScalar): Likewise.
387 (EXqScalarS): Likewise.
388 (VexScalar): Likewise.
389 (EXdVexScalarS): Likewise.
390 (EXqVexScalarS): Likewise.
391 (XMVexScalar): Likewise.
392 (scalar_mode): Likewise.
393 (d_scalar_mode): Likewise.
394 (d_scalar_swap_mode): Likewise.
395 (q_scalar_mode): Likewise.
396 (q_scalar_swap_mode): Likewise.
397 (vex_scalar_mode): Likewise.
398 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
399 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
400 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
401 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
402 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
403 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
404 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
405 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
406 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
407 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
408 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
409 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
410 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
411 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
412 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
413 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
414 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
415 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
416 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
417 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
418 q_scalar_mode, q_scalar_swap_mode.
419 (OP_XMM): Handle scalar_mode.
420 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
421 and q_scalar_swap_mode.
422 (OP_VEX): Handle vex_scalar_mode.
423
208b4d78
L		 4242010-01-24 H.J. Lu <hongjiu.lu@intel.com>
425
426 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
427
448b213a
L		 4282010-01-24 H.J. Lu <hongjiu.lu@intel.com>
429
430 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
431
47cf8fa0
L		 4322010-01-24 H.J. Lu <hongjiu.lu@intel.com>
433
434 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
435
592d1631
L		 4362010-01-24 H.J. Lu <hongjiu.lu@intel.com>
437
438 * i386-dis.c (Bad_Opcode): New.
439 (bad_opcode): Likewise.
440 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
441 (dis386_twobyte): Likewise.
442 (reg_table): Likewise.
443 (prefix_table): Likewise.
444 (x86_64_table): Likewise.
445 (vex_len_table): Likewise.
446 (vex_w_table): Likewise.
447 (mod_table): Likewise.
448 (rm_table): Likewise.
449 (float_reg): Likewise.
450 (reg_table): Remove trailing "(bad)" entries.
451 (prefix_table): Likewise.
452 (x86_64_table): Likewise.
453 (vex_len_table): Likewise.
454 (vex_w_table): Likewise.
455 (mod_table): Likewise.
456 (rm_table): Likewise.
457 (get_valid_dis386): Handle bytemode 0.
458
712366da
L		 4592010-01-23 H.J. Lu <hongjiu.lu@intel.com>
460
461 * i386-opc.h (VEXScalar): New.
462
463 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
464 instructions.
465 * i386-tbl.h: Regenerated.
466
706e8205 4672010-01-21 H.J. Lu <hongjiu.lu@intel.com>
73bb6729
L		 468
469 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
470
471 * i386-opc.tbl: Add xsave64 and xrstor64.
472 * i386-tbl.h: Regenerated.
473
99ea83aa
NC		 4742010-01-20 Nick Clifton <nickc@redhat.com>
475
476 PR 11170
477 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
478 based post-indexed addressing.
479
a6461c02
SP		 4802010-01-15 Sebastian Pop <sebastian.pop@amd.com>
481
482 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
483 * i386-tbl.h: Regenerated.
484
a2a7d12c
L		 4852010-01-14 H.J. Lu <hongjiu.lu@intel.com>
486
487 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
488 comments.
489
b9733481
L		 4902010-01-14 H.J. Lu <hongjiu.lu@intel.com>
491
492 * i386-dis.c (names_mm): New.
493 (intel_names_mm): Likewise.
494 (att_names_mm): Likewise.
495 (names_xmm): Likewise.
496 (intel_names_xmm): Likewise.
497 (att_names_xmm): Likewise.
498 (names_ymm): Likewise.
499 (intel_names_ymm): Likewise.
500 (att_names_ymm): Likewise.
501 (print_insn): Set names_mm, names_xmm and names_ymm.
502 (OP_MMX): Use names_mm, names_xmm and names_ymm.
503 (OP_XMM): Likewise.
504 (OP_EM): Likewise.
505 (OP_EMC): Likewise.
506 (OP_MXC): Likewise.
507 (OP_EX): Likewise.
508 (XMM_Fixup): Likewise.
509 (OP_VEX): Likewise.
510 (OP_EX_VexReg): Likewise.
511 (OP_Vex_2src): Likewise.
512 (OP_Vex_2src_1): Likewise.
513 (OP_Vex_2src_2): Likewise.
514 (OP_REG_VexI4): Likewise.
515
5e6718e4
L		 5162010-01-13 H.J. Lu <hongjiu.lu@intel.com>
517
518 * i386-dis.c (print_insn): Update comments.
519
d869730d
L		 5202010-01-12 H.J. Lu <hongjiu.lu@intel.com>
521
522 * i386-dis.c (rex_original): Removed.
523 (ckprefix): Remove rex_original.
524 (print_insn): Update comments.
525
3725885a
RW		 5262010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
527
528 * Makefile.in: Regenerate.
529 * configure: Regenerate.
530
b7cd1872
DE		 5312010-01-07 Doug Evans <dje@sebabeach.org>
532
533 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
534 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
535 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
536 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
537 * xstormy16-ibld.c: Regenerate.
538
69dd9865
SP		 5392010-01-06 Quentin Neill <quentin.neill@amd.com>
540
541 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
542 * i386-init.h: Regenerated.
543
e3e535bc
NC		 5442010-01-06 Daniel Gutson <dgutson@codesourcery.com>
545
546 * arm-dis.c (print_insn): Fixed search for next symbol and data
547 dumping condition, and the initial mapping symbol state.
548
fe8afbc4
DE		 5492010-01-05 Doug Evans <dje@sebabeach.org>
550
551 * cgen-ibld.in: #include "cgen/basic-modes.h".
552 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
553 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
554 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
555 * xstormy16-ibld.c: Regenerate.
556
2edcd244
NC		 5572010-01-04 Nick Clifton <nickc@redhat.com>
558
559 PR 11123
560 * arm-dis.c (print_insn_coprocessor): Initialise value.
561
0dc93057
AM		 5622010-01-04 Edmar Wienskoski <edmar@freescale.com>
563
564 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
565
05994f45
DE		 5662010-01-02 Doug Evans <dje@sebabeach.org>
567
568 * cgen-asm.in: Update copyright year.
569 * cgen-dis.in: Update copyright year.
570 * cgen-ibld.in: Update copyright year.
571 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
572 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
573 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
574 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
575 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
576 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
577 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
578 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
579 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
580 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
581 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
582 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
583 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
584 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
585 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
586 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
587 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
588 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
589 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
590 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
591 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2426c15f 592
43ecc30f 593For older changes see ChangeLog-2009
252b5132
RH		 594\f
595Local Variables:
2f6d2f85
NC		 596mode: change-log
597left-margin: 8
598fill-column: 74
252b5132
RH		 599version-control: never
600End:
GDB Binutils - Deliverables
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