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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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1cd986c5
NC		 12010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
2 Ina Pandit <ina.pandit@kpitcummins.com>
3
4 * v850-dis.c (v850_sreg_names): Updated structure for system
5 registers.
6 (float_cc_names): new structure for condition codes.
7 (print_value): Update the function that prints value.
8 (get_operand_value): New function to get the operand value.
9 (disassemble): Updated to handle the disassembly of instructions.
10 (print_insn_v850): Updated function to print instruction for different
11 families.
12 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
13 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
14 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
15 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
16 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
17 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
18 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
19 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
20 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
21 (v850_operands): Update with the relocation name. Also update
22 the instructions with specific set of processors.
23
52e7f43d
RE		 242010-07-08 Tejas Belagod <tejas.belagod@arm.com>
25
26 * arm-dis.c (print_insn_arm): Add cases for printing more
27 symbolic operands.
28 (print_insn_thumb32): Likewise.
29
c680e7f6
MR		 302010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
31
32 * mips-dis.c (print_insn_mips): Correct branch instruction type
33 determination.
34
9a2c7088
MR		 352010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
36
37 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
38 type and delay slot determination.
39 (print_insn_mips16): Extend branch instruction type and delay
40 slot determination to cover all instructions.
41 * mips16-opc.c (BR): Remove macro.
42 (UBR, CBR): New macros.
43 (mips16_opcodes): Update branch annotation for "b", "beqz",
44 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
45 and "jrc".
46
d7d9a9f8
L		 472010-07-05 H.J. Lu <hongjiu.lu@intel.com>
48
49 AVX Programming Reference (June, 2010)
50 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
51 * i386-opc.tbl: Likewise.
52 * i386-tbl.h: Regenerated.
53
77321f53
L		 542010-07-05 H.J. Lu <hongjiu.lu@intel.com>
55
56 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
57
7102e95e
AS		 582010-07-03 Andreas Schwab <schwab@linux-m68k.org>
59
60 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
61 ppc_cpu_t before inverting.
3a5530ea
AS		 62 (ppc_parse_cpu): Likewise.
63 (print_insn_powerpc): Likewise.
7102e95e 64
bdc70b4a
AM		 652010-07-03 Alan Modra <amodra@gmail.com>
66
67 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
68 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
69 (PPC64, MFDEC2): Update.
70 (NON32, NO371): Define.
71 (powerpc_opcode): Update to not use old opcode flags, and avoid
72 -m601 duplicates.
73
21375995
DD		 742010-07-03 DJ Delorie <dj@delorie.com>
75
76 * m32c-ibld.c: Regenerate.
77
81a0b7e2
AM		 782010-07-03 Alan Modra <amodra@gmail.com>
79
80 * ppc-opc.c (PWR2COM): Define.
81 (PPCPWR2): Add PPC_OPCODE_COMMON.
82 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
83 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
84 "rac" from -mcom.
85
c7b8aa3a
L		 862010-07-01 H.J. Lu <hongjiu.lu@intel.com>
87
88 AVX Programming Reference (June, 2010)
89 * i386-dis.c (PREFIX_0FAE_REG_0): New.
90 (PREFIX_0FAE_REG_1): Likewise.
91 (PREFIX_0FAE_REG_2): Likewise.
92 (PREFIX_0FAE_REG_3): Likewise.
93 (PREFIX_VEX_3813): Likewise.
94 (PREFIX_VEX_3A1D): Likewise.
95 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
96 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
97 PREFIX_VEX_3A1D.
98 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
99 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
100 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
101
102 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
103 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
104 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
105
106 * i386-opc.h (CpuXsaveopt): New.
77321f53 107 (CpuFSGSBase): Likewise.
c7b8aa3a
L		 108 (CpuRdRnd): Likewise.
109 (CpuF16C): Likewise.
110 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
111 cpuf16c.
112
113 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
114 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
a00eb5e8
L		 115 * i386-init.h: Regenerated.
116 * i386-tbl.h: Likewise.
c7b8aa3a 117
09a8ad8d
AM		 1182010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
119
120 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
121 and mtocrf on EFS.
122
360cfc9c
AM		 1232010-06-29 Alan Modra <amodra@gmail.com>
124
125 * maxq-dis.c: Delete file.
126 * Makefile.am: Remove references to maxq.
127 * configure.in: Likewise.
128 * disassemble.c: Likewise.
129 * Makefile.in: Regenerate.
130 * configure: Regenerate.
131 * po/POTFILES.in: Regenerate.
132
dc898d5e
AM		 1332010-06-29 Alan Modra <amodra@gmail.com>
134
135 * mep-dis.c: Regenerate.
136
8e560766
MGD		 1372010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
138
139 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
140
c7e2358a
AM		 1412010-06-27 Alan Modra <amodra@gmail.com>
142
143 * arc-dis.c (arc_sprintf): Delete set but unused variables.
144 (decodeInstr): Likewise.
145 * dlx-dis.c (print_insn_dlx): Likewise.
146 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
147 * maxq-dis.c (check_move, print_insn): Likewise.
148 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
149 * msp430-dis.c (msp430_branchinstr): Likewise.
150 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
151 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
152 * sparc-dis.c (print_insn_sparc): Likewise.
153 * fr30-asm.c: Regenerate.
154 * frv-asm.c: Regenerate.
155 * ip2k-asm.c: Regenerate.
156 * iq2000-asm.c: Regenerate.
157 * lm32-asm.c: Regenerate.
158 * m32c-asm.c: Regenerate.
159 * m32r-asm.c: Regenerate.
160 * mep-asm.c: Regenerate.
161 * mt-asm.c: Regenerate.
162 * openrisc-asm.c: Regenerate.
163 * xc16x-asm.c: Regenerate.
164 * xstormy16-asm.c: Regenerate.
165
6ffe3d99
NC		 1662010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
167
168 PR gas/11673
169 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
170
09ec0d17
NC		 1712010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
172
173 PR binutils/11676
174 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
175
e01d869a
AM		 1762010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
177
178 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
179 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
180 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
181 touch floating point regs and are enabled by COM, PPC or PPCCOM.
182 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
183 Treat lwsync as msync on e500.
184
1f4e4950
MGD		 1852010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
186
187 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
188
9d82ec38
MGD		 1892010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
190
e01d869a 191 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
9d82ec38
MGD		 192 constants is the same on 32-bit and 64-bit hosts.
193
c3a6ea62 1942010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
d8b24b95
NC		 195
196 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
197 .short directives so that they can be reassembled.
198
9db8dccb
CM		 1992010-05-26 Catherine Moore <clm@codesourcery.com>
200 David Ung <davidu@mips.com>
201
202 * mips-opc.c: Change membership to I1 for instructions ssnop and
203 ehb.
204
dfc8cf43
L		 2052010-05-26 H.J. Lu <hongjiu.lu@intel.com>
206
207 * i386-dis.c (sib): New.
208 (get_sib): Likewise.
209 (print_insn): Call get_sib.
210 OP_E_memory): Use sib.
211
f79e2745
CM		 2122010-05-26 Catherine Moore <clm@codesoourcery.com>
213
214 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
215 * mips-opc.c (I16): Remove.
216 (mips_builtin_op): Reclassify jalx.
217
51b5d4a8
AM		 2182010-05-19 Alan Modra <amodra@gmail.com>
219
220 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
221 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
222
85d4ac0b
AM		 2232010-05-13 Alan Modra <amodra@gmail.com>
224
225 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
226
4547cb56
NC		 2272010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
228
229 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
230 format.
231 (print_insn_thumb16): Add support for new %W format.
232
6540b386
TG		 2332010-05-07 Tristan Gingold <gingold@adacore.com>
234
235 * Makefile.in: Regenerate with automake 1.11.1.
236 * aclocal.m4: Ditto.
237
3e01a7fd
NC		 2382010-05-05 Nick Clifton <nickc@redhat.com>
239
240 * po/es.po: Updated Spanish translation.
241
9c9c98a5
NC		 2422010-04-22 Nick Clifton <nickc@redhat.com>
243
244 * po/opcodes.pot: Updated by the Translation project.
245 * po/vi.po: Updated Vietnamese translation.
246
f07af43e
L		 2472010-04-16 H.J. Lu <hongjiu.lu@intel.com>
248
249 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
250 bits in opcode.
251
3d540e93
NC		 2522010-04-09 Nick Clifton <nickc@redhat.com>
253
254 * i386-dis.c (print_insn): Remove unused variable op.
255 (OP_sI): Remove unused variable mask.
256
397841b5
AM		 2572010-04-07 Alan Modra <amodra@gmail.com>
258
259 * configure: Regenerate.
260
cee62821
PB		 2612010-04-06 Peter Bergner <bergner@vnet.ibm.com>
262
263 * ppc-opc.c (RBOPT): New define.
264 ("dccci"): Enable for PPCA2. Make operands optional.
265 ("iccci"): Likewise. Do not deprecate for PPC476.
266
accf4463
NC		 2672010-04-02 Masaki Muranaka <monaka@monami-software.com>
268
269 * cr16-opc.c (cr16_instruction): Fix typo in comment.
270
40b36596
JM		 2712010-03-25 Joseph Myers <joseph@codesourcery.com>
272
273 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
274 * Makefile.in: Regenerate.
275 * configure.in (bfd_tic6x_arch): New.
276 * configure: Regenerate.
277 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
278 (disassembler): Handle TI C6X.
279 * tic6x-dis.c: New.
280
1985c81c
MF		 2812010-03-24 Mike Frysinger <vapier@gentoo.org>
282
283 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
284
f66187fd
JM		 2852010-03-23 Joseph Myers <joseph@codesourcery.com>
286
287 * dis-buf.c (buffer_read_memory): Give error for reading just
288 before the start of memory.
289
ce7d077e
SP		 2902010-03-22 Sebastian Pop <sebastian.pop@amd.com>
291 Quentin Neill <quentin.neill@amd.com>
292
293 * i386-dis.c (OP_LWP_I): Removed.
294 (reg_table): Do not use OP_LWP_I, use Iq.
295 (OP_LWPCB_E): Remove use of names16.
296 (OP_LWP_E): Same.
297 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
298 should not set the Vex.length bit.
299 * i386-tbl.h: Regenerated.
300
63d0fa4e
AM		 3012010-02-25 Edmar Wienskoski <edmar@freescale.com>
302
303 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
304
c060226a
NC		 3052010-02-24 Nick Clifton <nickc@redhat.com>
306
307 PR binutils/6773
308 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
309 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
310 (thumb32_opcodes): Likewise.
311
ab7875de
NC		 3122010-02-15 Nick Clifton <nickc@redhat.com>
313
314 * po/vi.po: Updated Vietnamese translation.
315
fee1d3e8
DE		 3162010-02-12 Doug Evans <dje@sebabeach.org>
317
318 * lm32-opinst.c: Regenerate.
319
37ec9240
DE		 3202010-02-11 Doug Evans <dje@sebabeach.org>
321
9468ae89
DE		 322 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
323 (print_address): Delete CGEN_PRINT_ADDRESS.
324 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
325 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
326 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
327 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
328
37ec9240
DE		 329 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
330 * frv-desc.c, * frv-desc.h, * frv-opc.c,
331 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
332 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
333 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
334 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
335 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
336 * mep-desc.c, * mep-desc.h, * mep-opc.c,
337 * mt-desc.c, * mt-desc.h, * mt-opc.c,
338 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
339 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
340 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
341
c75ef631
L		 3422010-02-11 H.J. Lu <hongjiu.lu@intel.com>
343
344 * i386-dis.c: Update copyright.
345 * i386-gen.c: Likewise.
346 * i386-opc.h: Likewise.
347 * i386-opc.tbl: Likewise.
348
a683cc34
SP		 3492010-02-10 Quentin Neill <quentin.neill@amd.com>
350 Sebastian Pop <sebastian.pop@amd.com>
351
352 * i386-dis.c (OP_EX_VexImmW): Reintroduced
353 function to handle 5th imm8 operand.
354 (PREFIX_VEX_3A48): Added.
355 (PREFIX_VEX_3A49): Added.
356 (VEX_W_3A48_P_2): Added.
357 (VEX_W_3A49_P_2): Added.
358 (prefix table): Added entries for PREFIX_VEX_3A48
359 and PREFIX_VEX_3A49.
360 (vex table): Added entries for VEX_W_3A48_P_2 and
361 and VEX_W_3A49_P_2.
362 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
363 for Vec_Imm4 operands.
364 * i386-opc.h (enum): Added Vec_Imm4.
365 (i386_operand_type): Added vec_imm4.
366 * i386-opc.tbl: Add entries for vpermilp[ds].
367 * i386-init.h: Regenerated.
368 * i386-tbl.h: Regenerated.
369
cdc51b07
RS		 3702010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
371
372 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
373 and "pwr7". Move "a2" into alphabetical order.
374
ce3d2015
AM		 3752010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
376
377 * ppc-dis.c (ppc_opts): Add titan entry.
378 * ppc-opc.c (TITAN, MULHW): Define.
379 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
380
68339fdf
SP		 3812010-02-03 Quentin Neill <quentin.neill@amd.com>
382
383 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
384 to CPU_BDVER1_FLAGS
385 * i386-init.h: Regenerated.
386
f3d55a94
AG		 3872010-02-03 Anthony Green <green@moxielogic.com>
388
389 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
390 0x0f, and make 0x00 an illegal instruction.
391
b0e28b39
DJ		 3922010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
393
394 * opcodes/arm-dis.c (struct arm_private_data): New.
395 (print_insn_coprocessor, print_insn_arm): Update to use struct
396 arm_private_data.
397 (is_mapping_symbol, get_map_sym_type): New functions.
398 (get_sym_code_type): Check the symbol's section. Do not check
399 mapping symbols.
400 (print_insn): Default to disassembling ARM mode code. Check
401 for mapping symbols separately from other symbols. Use
402 struct arm_private_data.
403
1c480963
L		 4042010-01-28 H.J. Lu <hongjiu.lu@intel.com>
405
406 * i386-dis.c (EXVexWdqScalar): New.
407 (vex_scalar_w_dq_mode): Likewise.
408 (prefix_table): Update entries for PREFIX_VEX_3899,
409 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
410 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
411 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
412 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
413 (intel_operand_size): Handle vex_scalar_w_dq_mode.
414 (OP_EX): Likewise.
415
539f890d
L		 4162010-01-27 H.J. Lu <hongjiu.lu@intel.com>
417
418 * i386-dis.c (XMScalar): New.
419 (EXdScalar): Likewise.
420 (EXqScalar): Likewise.
421 (EXqScalarS): Likewise.
422 (VexScalar): Likewise.
423 (EXdVexScalarS): Likewise.
424 (EXqVexScalarS): Likewise.
425 (XMVexScalar): Likewise.
426 (scalar_mode): Likewise.
427 (d_scalar_mode): Likewise.
428 (d_scalar_swap_mode): Likewise.
429 (q_scalar_mode): Likewise.
430 (q_scalar_swap_mode): Likewise.
431 (vex_scalar_mode): Likewise.
432 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
433 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
434 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
435 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
436 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
437 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
438 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
439 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
440 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
441 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
442 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
443 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
444 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
445 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
446 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
447 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
448 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
449 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
450 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
451 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
452 q_scalar_mode, q_scalar_swap_mode.
453 (OP_XMM): Handle scalar_mode.
454 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
455 and q_scalar_swap_mode.
456 (OP_VEX): Handle vex_scalar_mode.
457
208b4d78
L		 4582010-01-24 H.J. Lu <hongjiu.lu@intel.com>
459
460 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
461
448b213a
L		 4622010-01-24 H.J. Lu <hongjiu.lu@intel.com>
463
464 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
465
47cf8fa0
L		 4662010-01-24 H.J. Lu <hongjiu.lu@intel.com>
467
468 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
469
592d1631
L		 4702010-01-24 H.J. Lu <hongjiu.lu@intel.com>
471
472 * i386-dis.c (Bad_Opcode): New.
473 (bad_opcode): Likewise.
474 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
475 (dis386_twobyte): Likewise.
476 (reg_table): Likewise.
477 (prefix_table): Likewise.
478 (x86_64_table): Likewise.
479 (vex_len_table): Likewise.
480 (vex_w_table): Likewise.
481 (mod_table): Likewise.
482 (rm_table): Likewise.
483 (float_reg): Likewise.
484 (reg_table): Remove trailing "(bad)" entries.
485 (prefix_table): Likewise.
486 (x86_64_table): Likewise.
487 (vex_len_table): Likewise.
488 (vex_w_table): Likewise.
489 (mod_table): Likewise.
490 (rm_table): Likewise.
491 (get_valid_dis386): Handle bytemode 0.
492
712366da
L		 4932010-01-23 H.J. Lu <hongjiu.lu@intel.com>
494
495 * i386-opc.h (VEXScalar): New.
496
497 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
498 instructions.
499 * i386-tbl.h: Regenerated.
500
706e8205 5012010-01-21 H.J. Lu <hongjiu.lu@intel.com>
73bb6729
L		 502
503 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
504
505 * i386-opc.tbl: Add xsave64 and xrstor64.
506 * i386-tbl.h: Regenerated.
507
99ea83aa
NC		 5082010-01-20 Nick Clifton <nickc@redhat.com>
509
510 PR 11170
511 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
512 based post-indexed addressing.
513
a6461c02
SP		 5142010-01-15 Sebastian Pop <sebastian.pop@amd.com>
515
516 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
517 * i386-tbl.h: Regenerated.
518
a2a7d12c
L		 5192010-01-14 H.J. Lu <hongjiu.lu@intel.com>
520
521 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
522 comments.
523
b9733481
L		 5242010-01-14 H.J. Lu <hongjiu.lu@intel.com>
525
526 * i386-dis.c (names_mm): New.
527 (intel_names_mm): Likewise.
528 (att_names_mm): Likewise.
529 (names_xmm): Likewise.
530 (intel_names_xmm): Likewise.
531 (att_names_xmm): Likewise.
532 (names_ymm): Likewise.
533 (intel_names_ymm): Likewise.
534 (att_names_ymm): Likewise.
535 (print_insn): Set names_mm, names_xmm and names_ymm.
536 (OP_MMX): Use names_mm, names_xmm and names_ymm.
537 (OP_XMM): Likewise.
538 (OP_EM): Likewise.
539 (OP_EMC): Likewise.
540 (OP_MXC): Likewise.
541 (OP_EX): Likewise.
542 (XMM_Fixup): Likewise.
543 (OP_VEX): Likewise.
544 (OP_EX_VexReg): Likewise.
545 (OP_Vex_2src): Likewise.
546 (OP_Vex_2src_1): Likewise.
547 (OP_Vex_2src_2): Likewise.
548 (OP_REG_VexI4): Likewise.
549
5e6718e4
L		 5502010-01-13 H.J. Lu <hongjiu.lu@intel.com>
551
552 * i386-dis.c (print_insn): Update comments.
553
d869730d
L		 5542010-01-12 H.J. Lu <hongjiu.lu@intel.com>
555
556 * i386-dis.c (rex_original): Removed.
557 (ckprefix): Remove rex_original.
558 (print_insn): Update comments.
559
3725885a
RW		 5602010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
561
562 * Makefile.in: Regenerate.
563 * configure: Regenerate.
564
b7cd1872
DE		 5652010-01-07 Doug Evans <dje@sebabeach.org>
566
567 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
568 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
569 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
570 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
571 * xstormy16-ibld.c: Regenerate.
572
69dd9865
SP		 5732010-01-06 Quentin Neill <quentin.neill@amd.com>
574
575 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
576 * i386-init.h: Regenerated.
577
e3e535bc
NC		 5782010-01-06 Daniel Gutson <dgutson@codesourcery.com>
579
580 * arm-dis.c (print_insn): Fixed search for next symbol and data
581 dumping condition, and the initial mapping symbol state.
582
fe8afbc4
DE		 5832010-01-05 Doug Evans <dje@sebabeach.org>
584
585 * cgen-ibld.in: #include "cgen/basic-modes.h".
586 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
587 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
588 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
589 * xstormy16-ibld.c: Regenerate.
590
2edcd244
NC		 5912010-01-04 Nick Clifton <nickc@redhat.com>
592
593 PR 11123
594 * arm-dis.c (print_insn_coprocessor): Initialise value.
595
0dc93057
AM		 5962010-01-04 Edmar Wienskoski <edmar@freescale.com>
597
598 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
599
05994f45
DE		 6002010-01-02 Doug Evans <dje@sebabeach.org>
601
602 * cgen-asm.in: Update copyright year.
603 * cgen-dis.in: Update copyright year.
604 * cgen-ibld.in: Update copyright year.
605 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
606 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
607 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
608 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
609 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
610 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
611 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
612 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
613 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
614 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
615 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
616 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
617 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
618 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
619 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
620 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
621 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
622 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
623 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
624 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
625 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2426c15f 626
43ecc30f 627For older changes see ChangeLog-2009
252b5132
RH		 628\f
629Local Variables:
2f6d2f85
NC		 630mode: change-log
631left-margin: 8
632fill-column: 74
252b5132
RH		 633version-control: never
634End:
GDB Binutils - Deliverables
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