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Revert "Do not issue error messages when parsing a PSTATE register".
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
8f8c3854
CM		 12013-11-19 Catherine Moore <clm@codesourcery.com>
2
3 * micromips-opc.c (LM): Define.
4 (micromips_opcodes): Add LM to load instructions.
5 * mips-opc.c (prefe): Add LM attribute.
6
a203d9b7
YZ		 72013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
8
9 Revert
10
11 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
12
13 * aarch64-opc.c (CPENT): New define.
14 (F_READONLY, F_WRITEONLY): Likewise.
15 (aarch64_sys_regs): Add trace unit registers.
16 (aarch64_sys_reg_readonly_p): New function.
17 (aarch64_sys_reg_writeonly_p): Ditto.
18
75468c93
YZ		 192013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
20
21 * aarch64-opc.c (CPENT): New define.
22 (F_READONLY, F_WRITEONLY): Likewise.
23 (aarch64_sys_regs): Add trace unit registers.
24 (aarch64_sys_reg_readonly_p): New function.
25 (aarch64_sys_reg_writeonly_p): Ditto.
26
caeba11c
MR		 272013-11-15 Maciej W. Rozycki <macro@codesourcery.com>
28
29 * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
30 "mtcr".
31
b83a9376
CM		 322013-11-11 Catherine Moore <clm@codesourcery.com>
33
34 * mips-dis.c (print_insn_mips): Use
35 INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
36 (print_insn_micromips): Likewise.
37 * mips-opc.c (LDD): Remove.
38 (CLD): Include INSN_LOAD_MEMORY.
39 (LM): New.
40 (mips_builtin_opcodes): Use LM instead of LDD.
41 Add LM to load instructions.
42
d56da83e
L		 432013-11-08 H.J. Lu <hongjiu.lu@intel.com>
44
45 PR gas/16140
46 * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
47 * i386-init.h: Regenerated.
48
49eec193
YZ		 492013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
50
51 * aarch64-opc.c (F_DEPRECATED): New macro.
52 (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
53 F_DEPRECATED.
54 (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
55 AARCH64_OPND_SYSREG.
56
68a64283
YZ		 572013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
58
59 * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
60 (convert_from_csel): Likewise.
61 * aarch64-opc.c (operand_general_constraint_met_p): Handle
62 AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
63 (aarch64_print_operand): Handle AARCH64_OPND_COND1.
64 * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
65 COND for cinc, cset, cinv, csetm and cneg.
66 (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
67 * aarch64-asm-2.c: Re-generated.
68 * aarch64-dis-2.c: Ditto.
69 * aarch64-opc-2.c: Ditto.
70
4e50d5f8
YZ		 712013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
72
73 * aarch64-opc.c (set_syntax_error): New function.
74 (operand_general_constraint_met_p): Replace set_other_error
75 with set_syntax_error.
76
7d4a7d10
AA		 772013-10-30 Andreas Arnez <arnez@linux.vnet.ibm.com>
78
79 * s390-dis.c (init_disasm): Default to full 'zarch' opcode
80 availability even for 31-bit programs.
81
85181173
RR		 822013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
83
84 * arm-dis.c (neon_opcodes): Adjust print string for vshll.
85
4edbb8e3
CF		 862013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
87
88 * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
89 +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
90 +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
91 (MSA): New define.
92 (MSA64): New define.
93 (micromips_opcodes): Add MSA instructions.
94 * mips-dis.c (msa_control_names): New array.
95 (mips_abi_choice): Add ASE_MSA to mips32r2.
96 Remove ASE_MDMX from mips64r2.
97 Add ASE_MSA and ASE_MSA64 to mips64r2.
98 (parse_mips_dis_option): Handle -Mmsa.
99 (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
100 (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
101 (print_mips_disassembler_options): Print -Mmsa.
102 * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
103 +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
104 (MSA): New define.
105 (MSA64): New define.
106 (mips_builtin_op): Add MSA instructions.
107
ae335a4e
SL		 1082013-10-13 Sandra Loosemore <sandra@codesourcery.com>
109
110 * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
111 as the primary name of r30.
112
6c75cc62
L		 1132013-10-12 Jan Beulich <jbeulich@suse.com>
114
115 * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
116 default case.
117 (OP_E_register): Move v_bnd_mode alongside m_mode.
118 * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
119 Drop Reg16 and Disp16. Add NoRex64.
120 (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
121 * i386-tbl.h: Re-generate.
122
0e1c2434
SK		 1232013-10-10 Sean Keys <skeys@ipdatasys.com>
124
125 * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
126 table.
127 * xgate-dis.c (print_insn): Refactor to work with table change.
128
7903e530
RM		 1292013-10-10 Roland McGrath <mcgrathr@google.com>
130
9ce09ba2
RM		 131 * i386-dis.c (oappend_maybe_intel): New function.
132 (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
133 (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
134 (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
135
2b4e983c
RM		 136 * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
137 possible compiler warnings when the union's initializer is
138 actually meant for the 'preg' enum typed member.
139 * crx-opc.c (REG): Likewise.
140
7903e530
RM		 141 * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
142 Remove duplicate const qualifier.
143
79e0e31d
JB		 1442013-10-08 Jan Beulich <jbeulich@suse.com>
145
146 * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
147 (clflush): Use Anysize instead of Byte|Unspecified.
148 (prefetch*): Likewise.
149 * i386-tbl.h: Re-generate.
150
45099dfa
CF		 1512013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
152
153 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
154
916fae91
L		 1552013-09-30 H.J. Lu <hongjiu.lu@intel.com>
156
157 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
158 * i386-init.h: Regenerated.
159
c7b0bd56
SE		 1602013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
161
162 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
163 * i386-init.h: Regenerated.
164
cc9afea3
AM		 1652013-09-20 Alan Modra <amodra@gmail.com>
166
167 * configure: Regenerate.
168
e3f9e852
RS		 1692013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
170
171 * s390-opc.txt (clih): Make the immediate unsigned.
172
74db7efb
NC		 1732013-09-04 Roland McGrath <mcgrathr@google.com>
174
175 PR gas/15914
176 * arm-dis.c (arm_opcodes): Add udf.
177 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
178 (thumb32_opcodes): Add udf.w.
179 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
180
c8094e01
AK		 1812013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
182
183 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
184 For the load fp integer instructions only the suppression flag was
185 new with z196 version.
186
7e105031
NC		 1872013-08-28 Nick Clifton <nickc@redhat.com>
188
189 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
190 immediate is not suitable for the 32-bit ABI.
191
fb6f3895
MR		 1922013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
193
194 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
195 replacing NODS.
196
9aff4b7a
NC		 1972013-08-23 Yuri Chornoivan <yurchor@ukr.net>
198
199 PR binutils/15834
200 * aarch64-asm.c: Fix typos.
201 * aarch64-dis.c: Likewise.
202 * msp430-dis.c: Likewise.
203
5e0dc5ba
RS		 2042013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
205
206 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
207 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
208 Use +H rather than +C for the real "dext".
209 * mips-opc.c (mips_builtin_opcodes): Likewise.
210
0f35dbc4
RS		 2112013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
212
213 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
214 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
215 and OPTIONAL_MAPPED_REG.
216 * mips-opc.c (decode_mips_operand): Likewise.
217 * mips16-opc.c (decode_mips16_operand): Likewise.
218 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
219
79ceb7cb
L		 2202013-08-19 H.J. Lu <hongjiu.lu@intel.com>
221
222 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
223 (PREFIX_EVEX_0F3A3F): Likewise.
224 * i386-dis-evex.h (evex_table): Updated.
225
ee5734f0
RS		 2262013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
227
228 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
229 VCLIPW.
230
d6787ef9
EB		 2312013-08-05 Eric Botcazou <ebotcazou@adacore.com>
232 Konrad Eisele <konrad@gaisler.com>
233
234 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
235 bfd_mach_sparc.
236 * sparc-opc.c (MASK_LEON): Define.
237 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
238 (letandleon): New macro.
239 (v9andleon): Likewise.
240 (sparc_opc): Add leon.
241 (umac): Enable for letandleon.
242 (smac): Likewise.
243 (casa): Enable for v9andleon.
244 (cas): Likewise.
245 (casl): Likewise.
246
14daeee3
RS		 2472013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
248 Richard Sandiford <rdsandiford@googlemail.com>
249
250 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
251 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
252 (print_vu0_channel): New function.
253 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
254 (print_insn_args): Handle '#'.
255 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
256 * mips-opc.c (mips_vu0_channel_mask): New constant.
257 (decode_mips_operand): Handle new VU0 operand types.
258 (VU0, VU0CH): New macros.
259 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
260 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
261 Use "+6" rather than "G" for QMFC2 and QMTC2.
262
3ccad066
RS		 2632013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
264
265 * mips-formats.h (PCREL): Reorder parameters and update the definition
266 to match new mips_pcrel_operand layout.
267 (JUMP, JALX, BRANCH): Update accordingly.
268 * mips16-opc.c (decode_mips16_operand): Likewise.
269
df34fbcc
RS		 2702013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
271
272 * micromips-opc.c (WR_s): Delete.
273
fc76e730
RS		 2742013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
275
276 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
277 New macros.
278 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
279 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
280 (mips_builtin_opcodes): Use the new position-based read-write flags
281 instead of field-based ones. Use UDI for "udi..." instructions.
282 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
283 New macros.
284 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
285 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
286 (WR_SP, RD_16): New macros.
287 (RD_SP): Redefine as an INSN2_* flag.
288 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
289 (mips16_opcodes): Use the new position-based read-write flags
290 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
291 pinfo2 field.
292 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
293 New macros.
294 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
295 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
296 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
297 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
298 (micromips_opcodes): Use the new position-based read-write flags
299 instead of field-based ones.
300 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
301 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
302 of field-based flags.
303
26545944
RS		 3042013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
305
306 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
307 (WR_SP): Replace with...
308 (MOD_SP): ...this.
309 (mips16_opcodes): Update accordingly.
310 * mips-dis.c (print_insn_mips16): Likewise.
311
a8d92fc6
RS		 3122013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
313
314 * mips16-opc.c (mips16_opcodes): Reformat.
315
6a819047
RS		 3162013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
317
318 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
319 for operands that are hard-coded to $0.
320 * micromips-opc.c (micromips_opcodes): Likewise.
321
344c74a6
RS		 3222013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
323
324 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
325 for the single-operand forms of JALR and JALR.HB.
326 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
327 and JALRS.HB.
328
41989114
RS		 3292013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
330
331 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
332 instructions. Fix them to use WR_MACC instead of WR_CC and
333 add missing RD_MACCs.
334
6d075bce
RS		 3352013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
336
337 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
338
4f6ffcd3
PB		 3392013-07-29 Peter Bergner <bergner@vnet.ibm.com>
340
341 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
342
43234a1e
L		 3432013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
344 Alexander Ivchenko <alexander.ivchenko@intel.com>
345 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
346 Sergey Lega <sergey.s.lega@intel.com>
347 Anna Tikhonova <anna.tikhonova@intel.com>
348 Ilya Tocar <ilya.tocar@intel.com>
349 Andrey Turetskiy <andrey.turetskiy@intel.com>
350 Ilya Verbin <ilya.verbin@intel.com>
351 Kirill Yukhin <kirill.yukhin@intel.com>
352 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
353
354 * i386-dis-evex.h: New.
355 * i386-dis.c (OP_Rounding): New.
356 (VPCMP_Fixup): New.
357 (OP_Mask): New.
358 (Rdq): New.
359 (XMxmmq): New.
360 (EXdScalarS): New.
361 (EXymm): New.
362 (EXEvexHalfBcstXmmq): New.
363 (EXxmm_mdq): New.
364 (EXEvexXGscat): New.
365 (EXEvexXNoBcst): New.
366 (VPCMP): New.
367 (EXxEVexR): New.
368 (EXxEVexS): New.
369 (XMask): New.
370 (MaskG): New.
371 (MaskE): New.
372 (MaskR): New.
373 (MaskVex): New.
374 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
375 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
376 evex_rounding_mode, evex_sae_mode, mask_mode.
377 (USE_EVEX_TABLE): New.
378 (EVEX_TABLE): New.
379 (EVEX enum): New.
380 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
381 REG_EVEX_0F38C7.
382 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
383 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
384 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
385 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
386 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
387 MOD_EVEX_0F38C7_REG_6.
388 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
389 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
390 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
391 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
392 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
393 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
394 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
395 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
396 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
397 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
398 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
399 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
400 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
401 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
402 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
403 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
404 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
405 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
406 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
407 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
408 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
409 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
410 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
411 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
412 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
413 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
414 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
415 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
416 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
417 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
418 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
419 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
420 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
421 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
422 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
423 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
424 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
425 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
426 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
427 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
428 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
429 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
430 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
431 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
432 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
433 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
434 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
435 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
436 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
437 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
438 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
439 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
440 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
441 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
442 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
443 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
444 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
445 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
446 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
447 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
448 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
449 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
450 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
451 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
452 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
453 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
454 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
455 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
456 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
457 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
458 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
459 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
460 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
461 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
462 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
463 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
464 PREFIX_EVEX_0F3A55.
465 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
466 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
467 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
468 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
469 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
470 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
471 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
472 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
473 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
474 VEX_W_0F3A32_P_2_LEN_0.
475 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
476 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
477 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
478 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
479 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
480 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
481 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
482 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
483 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
484 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
485 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
486 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
487 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
488 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
489 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
490 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
491 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
492 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
493 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
494 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
495 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
496 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
497 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
498 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
499 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
500 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
501 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
502 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
503 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
504 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
505 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
506 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
507 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
508 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
509 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
510 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
511 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
512 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
513 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
514 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
515 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
516 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
517 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
518 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
519 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
520 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
521 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
522 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
523 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
524 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
525 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
526 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
527 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
528 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
529 (struct vex): Add fields evex, r, v, mask_register_specifier,
530 zeroing, ll, b.
531 (intel_names_xmm): Add upper 16 registers.
532 (att_names_xmm): Ditto.
533 (intel_names_ymm): Ditto.
534 (att_names_ymm): Ditto.
535 (names_zmm): New.
536 (intel_names_zmm): Ditto.
537 (att_names_zmm): Ditto.
538 (names_mask): Ditto.
539 (intel_names_mask): Ditto.
540 (att_names_mask): Ditto.
541 (names_rounding): Ditto.
542 (names_broadcast): Ditto.
543 (x86_64_table): Add escape to evex-table.
544 (reg_table): Include reg_table evex-entries from
545 i386-dis-evex.h. Fix prefetchwt1 instruction.
546 (prefix_table): Add entries for new instructions.
547 (vex_table): Ditto.
548 (vex_len_table): Ditto.
549 (vex_w_table): Ditto.
550 (mod_table): Ditto.
551 (get_valid_dis386): Properly handle new instructions.
552 (print_insn): Handle zmm and mask registers, print mask operand.
553 (intel_operand_size): Support EVEX, new modes and sizes.
554 (OP_E_register): Handle new modes.
555 (OP_E_memory): Ditto.
556 (OP_G): Ditto.
557 (OP_XMM): Ditto.
558 (OP_EX): Ditto.
559 (OP_VEX): Ditto.
560 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
561 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
562 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
563 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
564 CpuAVX512PF and CpuVREX.
565 (operand_type_init): Add OPERAND_TYPE_REGZMM,
566 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
567 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
568 StaticRounding, SAE, Disp8MemShift, NoDefMask.
569 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
570 * i386-init.h: Regenerate.
571 * i386-opc.h (CpuAVX512F): New.
572 (CpuAVX512CD): New.
573 (CpuAVX512ER): New.
574 (CpuAVX512PF): New.
575 (CpuVREX): New.
576 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
577 cpuavx512pf and cpuvrex fields.
578 (VecSIB): Add VecSIB512.
579 (EVex): New.
580 (Masking): New.
581 (VecESize): New.
582 (Broadcast): New.
583 (StaticRounding): New.
584 (SAE): New.
585 (Disp8MemShift): New.
586 (NoDefMask): New.
587 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
588 staticrounding, sae, disp8memshift and nodefmask.
589 (RegZMM): New.
590 (Zmmword): Ditto.
591 (Vec_Disp8): Ditto.
592 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
593 fields.
594 (RegVRex): New.
595 * i386-opc.tbl: Add AVX512 instructions.
596 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
597 registers, mask registers.
598 * i386-tbl.h: Regenerate.
599
1d2db237
RS		 6002013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
601
602 PR gas/15220
603 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
604 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
605
a0046408
L		 6062013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
607
608 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
609 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
610 PREFIX_0F3ACC.
611 (prefix_table): Updated.
612 (three_byte_table): Likewise.
613 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
614 (cpu_flags): Add CpuSHA.
615 (i386_cpu_flags): Add cpusha.
616 * i386-init.h: Regenerate.
617 * i386-opc.h (CpuSHA): New.
618 (CpuUnused): Restored.
619 (i386_cpu_flags): Add cpusha.
620 * i386-opc.tbl: Add SHA instructions.
621 * i386-tbl.h: Regenerate.
622
7e8b059b
L		 6232013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
624 Kirill Yukhin <kirill.yukhin@intel.com>
625 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
626
627 * i386-dis.c (BND_Fixup): New.
628 (Ebnd): New.
629 (Ev_bnd): New.
630 (Gbnd): New.
631 (BND): New.
632 (v_bnd_mode): New.
633 (bnd_mode): New.
c623f86c
L		 634 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
635 MOD_0F1B_PREFIX_1.
636 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 637 (dis tables): Replace XX with BND for near branch and call
638 instructions.
639 (prefix_table): Add new entries.
640 (mod_table): Likewise.
641 (names_bnd): New.
642 (intel_names_bnd): New.
643 (att_names_bnd): New.
644 (BND_PREFIX): New.
645 (prefix_name): Handle BND_PREFIX.
646 (print_insn): Initialize names_bnd.
647 (intel_operand_size): Handle new modes.
648 (OP_E_register): Likewise.
649 (OP_E_memory): Likewise.
650 (OP_G): Likewise.
651 * i386-gen.c (cpu_flag_init): Add CpuMPX.
652 (cpu_flags): Add CpuMPX.
653 (operand_type_init): Add RegBND.
654 (opcode_modifiers): Add BNDPrefixOk.
655 (operand_types): Add RegBND.
656 * i386-init.h: Regenerate.
657 * i386-opc.h (CpuMPX): New.
658 (CpuUnused): Comment out.
659 (i386_cpu_flags): Add cpumpx.
660 (BNDPrefixOk): New.
661 (i386_opcode_modifier): Add bndprefixok.
662 (RegBND): New.
663 (i386_operand_type): Add regbnd.
664 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
665 Add MPX instructions and bnd prefix.
666 * i386-reg.tbl: Add bnd0-bnd3 registers.
667 * i386-tbl.h: Regenerate.
668
b56e23fb
RS		 6692013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
670
671 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
672 ATTRIBUTE_UNUSED.
673
e7ae278d
RS		 6742013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
675
676 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
677 special rules.
678 * Makefile.in: Regenerate.
679 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
680 all fields. Reformat.
681
c3c07478
RS		 6822013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
683
684 * mips16-opc.c: Include mips-formats.h.
685 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
686 static arrays.
687 (decode_mips16_operand): New function.
688 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
689 (print_insn_arg): Handle OP_ENTRY_EXIT list.
690 Abort for OP_SAVE_RESTORE_LIST.
691 (print_mips16_insn_arg): Change interface. Use mips_operand
692 structures. Delete GET_OP_S. Move GET_OP definition to...
693 (print_insn_mips16): ...here. Call init_print_arg_state.
694 Update the call to print_mips16_insn_arg.
695
ab902481
RS		 6962013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
697
698 * mips-formats.h: New file.
699 * mips-opc.c: Include mips-formats.h.
700 (reg_0_map): New static array.
701 (decode_mips_operand): New function.
702 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
703 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
704 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
705 (int_c_map): New static arrays.
706 (decode_micromips_operand): New function.
707 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
708 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
709 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
710 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
711 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
712 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
713 (micromips_imm_b_map, micromips_imm_c_map): Delete.
714 (print_reg): New function.
715 (mips_print_arg_state): New structure.
716 (init_print_arg_state, print_insn_arg): New functions.
717 (print_insn_args): Change interface and use mips_operand structures.
718 Delete GET_OP_S. Move GET_OP definition to...
719 (print_insn_mips): ...here. Update the call to print_insn_args.
720 (print_insn_micromips): Use print_insn_args.
721
cc537e56
RS		 7222013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
723
724 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
725 in macros.
726
7a5f87ce
RS		 7272013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
728
729 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
730 ADDA.S, MULA.S and SUBA.S.
731
41741fa4
L		 7322013-07-08 H.J. Lu <hongjiu.lu@intel.com>
733
734 PR gas/13572
735 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
736 * i386-tbl.h: Regenerated.
737
f2ae14a1
RS		 7382013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
739
740 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
741 and SD A(B) macros up.
742 * micromips-opc.c (micromips_opcodes): Likewise.
743
04c9d415
RS		 7442013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
745
746 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
747 instructions.
748
5c324c16
RS		 7492013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
750
751 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
752 MDMX-like instructions.
753 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
754 printing "Q" operands for INSN_5400 instructions.
755
23e69e47
RS		 7562013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
757
758 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
759 "+S" for "cins".
760 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
761 Combine cases.
762
27c5c572
RS		 7632013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
764
765 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
766 "jalx".
767 * mips16-opc.c (mips16_opcodes): Likewise.
768 * micromips-opc.c (micromips_opcodes): Likewise.
769 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
770 (print_insn_mips16): Handle "+i".
771 (print_insn_micromips): Likewise. Conditionally preserve the
772 ISA bit for "a" but not for "+i".
773
e76ff5ab
RS		 7742013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
775
776 * micromips-opc.c (WR_mhi): Rename to..
777 (WR_mh): ...this.
778 (micromips_opcodes): Update "movep" entry accordingly. Replace
779 "mh,mi" with "mh".
780 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
781 (micromips_to_32_reg_h_map1): ...this.
782 (micromips_to_32_reg_i_map): Rename to...
783 (micromips_to_32_reg_h_map2): ...this.
784 (print_micromips_insn): Remove "mi" case. Print both registers
785 in the pair for "mh".
786
fa7616a4
RS		 7872013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
788
789 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
790 * micromips-opc.c (micromips_opcodes): Likewise.
791 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
792 and "+T" handling. Check for a "0" suffix when deciding whether to
793 use coprocessor 0 names. In that case, also check for ",H" selectors.
794
fb798c50
AK		 7952013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
796
797 * s390-opc.c (J12_12, J24_24): New macros.
798 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
799 (MASK_MII_UPI): Rename to MASK_MII_UPP.
800 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
801
58ae08f2
AM		 8022013-07-04 Alan Modra <amodra@gmail.com>
803
804 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
805
b5e04c2b
NC		 8062013-06-26 Nick Clifton <nickc@redhat.com>
807
808 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
809 field when checking for type 2 nop.
810 * rx-decode.c: Regenerate.
811
833794fc
MR		 8122013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
813
814 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
815 and "movep" macros.
816
1bbce132
MR		 8172013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
818
819 * mips-dis.c (is_mips16_plt_tail): New function.
820 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
821 word.
822 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
823
34c911a4
NC		 8242013-06-21 DJ Delorie <dj@redhat.com>
825
826 * msp430-decode.opc: New.
827 * msp430-decode.c: New/generated.
828 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
829 (MAINTAINER_CLEANFILES): Likewise.
830 Add rule to build msp430-decode.c frommsp430decode.opc
831 using the opc2c program.
832 * Makefile.in: Regenerate.
833 * configure.in: Add msp430-decode.lo to msp430 architecture files.
834 * configure: Regenerate.
835
b9eead84
YZ		 8362013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
837
838 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
839 (SYMTAB_AVAILABLE): Removed.
840 (#include "elf/aarch64.h): Ditto.
841
7f3c4072
CM		 8422013-06-17 Catherine Moore <clm@codesourcery.com>
843 Maciej W. Rozycki <macro@codesourcery.com>
844 Chao-Ying Fu <fu@mips.com>
845
846 * micromips-opc.c (EVA): Define.
847 (TLBINV): Define.
848 (micromips_opcodes): Add EVA opcodes.
849 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
850 (print_insn_args): Handle EVA offsets.
851 (print_insn_micromips): Likewise.
852 * mips-opc.c (EVA): Define.
853 (TLBINV): Define.
854 (mips_builtin_opcodes): Add EVA opcodes.
855
de40ceb6
AM		 8562013-06-17 Alan Modra <amodra@gmail.com>
857
858 * Makefile.am (mips-opc.lo): Add rules to create automatic
859 dependency files. Pass archdefs.
860 (micromips-opc.lo, mips16-opc.lo): Likewise.
861 * Makefile.in: Regenerate.
862
3531d549
DD		 8632013-06-14 DJ Delorie <dj@redhat.com>
864
865 * rx-decode.opc (rx_decode_opcode): Bit operations on
866 registers are 32-bit operations, not 8-bit operations.
867 * rx-decode.c: Regenerate.
868
ba92f7fb
CF		 8692013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
870
871 * micromips-opc.c (IVIRT): New define.
872 (IVIRT64): New define.
873 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
874 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
875
876 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
877 dmtgc0 to print cp0 names.
878
9daf7bab
SL		 8792013-06-09 Sandra Loosemore <sandra@codesourcery.com>
880
881 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
882 argument.
883
d301a56b
RS		 8842013-06-08 Catherine Moore <clm@codesourcery.com>
885 Richard Sandiford <rdsandiford@googlemail.com>
886
887 * micromips-opc.c (D32, D33, MC): Update definitions.
888 (micromips_opcodes): Initialize ase field.
889 * mips-dis.c (mips_arch_choice): Add ase field.
890 (mips_arch_choices): Initialize ase field.
891 (set_default_mips_dis_options): Declare and setup mips_ase.
892 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
893 MT32, MC): Update definitions.
894 (mips_builtin_opcodes): Initialize ase field.
895
a3dcb6c5
RS		 8962013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
897
898 * s390-opc.txt (flogr): Require a register pair destination.
899
6cf1d90c
AK		 9002013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
901
902 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
903 instruction format.
904
c77c0862
RS		 9052013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
906
907 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
908
c0637f3a
PB		 9092013-05-20 Peter Bergner <bergner@vnet.ibm.com>
910
911 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
912 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
913 XLS_MASK, PPCVSX2): New defines.
914 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
915 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
916 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
917 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
918 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
919 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
920 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
921 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
922 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
923 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
924 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
925 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
926 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
927 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
928 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
929 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
930 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
931 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
932 <lxvx, stxvx>: New extended mnemonics.
933
4934fdaf
AM		 9342013-05-17 Alan Modra <amodra@gmail.com>
935
936 * ia64-raw.tbl: Replace non-ASCII char.
937 * ia64-waw.tbl: Likewise.
938 * ia64-asmtab.c: Regenerate.
939
6091d651
SE		 9402013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
941
942 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
943 * i386-init.h: Regenerated.
944
d2865ed3
YZ		 9452013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
946
947 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
948 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
949 check from [0, 255] to [-128, 255].
950
b015e599
AP		 9512013-05-09 Andrew Pinski <apinski@cavium.com>
952
953 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
954 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
955 (parse_mips_dis_option): Handle the virt option.
956 (print_insn_args): Handle "+J".
957 (print_mips_disassembler_options): Print out message about virt64.
958 * mips-opc.c (IVIRT): New define.
959 (IVIRT64): New define.
960 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
961 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
962 Move rfe to the bottom as it conflicts with tlbgp.
963
9f0682fe
AM		 9642013-05-09 Alan Modra <amodra@gmail.com>
965
966 * ppc-opc.c (extract_vlesi): Properly sign extend.
967 (extract_vlensi): Likewise. Comment reason for setting invalid.
968
13761a11
NC		 9692013-05-02 Nick Clifton <nickc@redhat.com>
970
971 * msp430-dis.c: Add support for MSP430X instructions.
972
e3031850
SL		 9732013-04-24 Sandra Loosemore <sandra@codesourcery.com>
974
975 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
976 to "eccinj".
977
17310e56
NC		 9782013-04-17 Wei-chen Wang <cole945@gmail.com>
979
980 PR binutils/15369
981 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
982 of CGEN_CPU_ENDIAN.
983 (hash_insns_list): Likewise.
984
731df338
JK		 9852013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
986
987 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
988 warning workaround.
989
5f77db52
JB		 9902013-04-08 Jan Beulich <jbeulich@suse.com>
991
992 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
993 * i386-tbl.h: Re-generate.
994
0afd1215
DM		 9952013-04-06 David S. Miller <davem@davemloft.net>
996
997 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
998 of an opcode, prefer the one with F_PREFERRED set.
999 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
1000 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
1001 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
1002 mark existing mnenomics as aliases. Add "cc" suffix to edge
1003 instructions generating condition codes, mark existing mnenomics
1004 as aliases. Add "fp" prefix to VIS compare instructions, mark
1005 existing mnenomics as aliases.
1006
41702d50
NC		 10072013-04-03 Nick Clifton <nickc@redhat.com>
1008
1009 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
1010 destination address by subtracting the operand from the current
1011 address.
1012 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
1013 a positive value in the insn.
1014 (extract_u16_loop): Do not negate the returned value.
1015 (D16_LOOP): Add V850_INVERSE_PCREL flag.
1016
1017 (ceilf.sw): Remove duplicate entry.
1018 (cvtf.hs): New entry.
1019 (cvtf.sh): Likewise.
1020 (fmaf.s): Likewise.
1021 (fmsf.s): Likewise.
1022 (fnmaf.s): Likewise.
1023 (fnmsf.s): Likewise.
1024 (maddf.s): Restrict to E3V5 architectures.
1025 (msubf.s): Likewise.
1026 (nmaddf.s): Likewise.
1027 (nmsubf.s): Likewise.
1028
55cf16e1
L		 10292013-03-27 H.J. Lu <hongjiu.lu@intel.com>
1030
1031 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
1032 check address mode.
1033 (print_insn): Pass sizeflag to get_sib.
1034
51dcdd4d
NC		 10352013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
1036
1037 PR binutils/15068
1038 * tic6x-dis.c: Add support for displaying 16-bit insns.
1039
795b8e6b
NC		 10402013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
1041
1042 PR gas/15095
1043 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1044 individual msb and lsb halves in src1 & src2 fields. Discard the
1045 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1046 follow what Ti SDK does in that case as any value in the src1
1047 field yields the same output with SDK disassembler.
1048
314d60dd
ME		 10492013-03-12 Michael Eager <eager@eagercon.com>
1050
795b8e6b 1051 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 1052
dad60f8e
SL		 10532013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1054
1055 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1056
f5cb796a
SL		 10572013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1058
1059 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1060
21fde85c
SL		 10612013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1062
1063 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1064
dd5181d5
KT		 10652013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1066
1067 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1068 (thumb32_opcodes): Likewise.
1069 (print_insn_thumb32): Handle 'S' control char.
1070
87a8d6cb
NC		 10712013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
1072
1073 * lm32-desc.c: Regenerate.
1074
99dce992
L		 10752013-03-01 H.J. Lu <hongjiu.lu@intel.com>
1076
1077 * i386-reg.tbl (riz): Add RegRex64.
1078 * i386-tbl.h: Regenerated.
1079
e60bb1dd
YZ		 10802013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1081
1082 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1083 (aarch64_feature_crc): New static.
1084 (CRC): New macro.
1085 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1086 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1087 * aarch64-asm-2.c: Re-generate.
1088 * aarch64-dis-2.c: Ditto.
1089 * aarch64-opc-2.c: Ditto.
1090
c7570fcd
AM		 10912013-02-27 Alan Modra <amodra@gmail.com>
1092
1093 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1094 * rl78-decode.c: Regenerate.
1095
151fa98f
NC		 10962013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1097
1098 * rl78-decode.opc: Fix encoding of DIVWU insn.
1099 * rl78-decode.c: Regenerate.
1100
5c111e37
L		 11012013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1102
1103 PR gas/15159
1104 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1105
1106 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1107 (cpu_flags): Add CpuSMAP.
1108
1109 * i386-opc.h (CpuSMAP): New.
1110 (i386_cpu_flags): Add cpusmap.
1111
1112 * i386-opc.tbl: Add clac and stac.
1113
1114 * i386-init.h: Regenerated.
1115 * i386-tbl.h: Likewise.
1116
9d1df426
NC		 11172013-02-15 Markos Chandras <markos.chandras@imgtec.com>
1118
1119 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1120 which also makes the disassembler output be in little
1121 endian like it should be.
1122
a1ccaec9
YZ		 11232013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1124
1125 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1126 fields to NULL.
1127 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1128
ef068ef4 11292013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 1130
1131 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1132 section disassembled.
1133
6fe6ded9
RE		 11342013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1135
1136 * arm-dis.c: Update strht pattern.
1137
0aa27725
RS		 11382013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1139
1140 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1141 single-float. Disable ll, lld, sc and scd for EE. Disable the
1142 trunc.w.s macro for EE.
1143
36591ba1
SL		 11442013-02-06 Sandra Loosemore <sandra@codesourcery.com>
1145 Andrew Jenner <andrew@codesourcery.com>
1146
1147 Based on patches from Altera Corporation.
1148
1149 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1150 nios2-opc.c.
1151 * Makefile.in: Regenerated.
1152 * configure.in: Add case for bfd_nios2_arch.
1153 * configure: Regenerated.
1154 * disassemble.c (ARCH_nios2): Define.
1155 (disassembler): Add case for bfd_arch_nios2.
1156 * nios2-dis.c: New file.
1157 * nios2-opc.c: New file.
1158
545093a4
AM		 11592013-02-04 Alan Modra <amodra@gmail.com>
1160
1161 * po/POTFILES.in: Regenerate.
1162 * rl78-decode.c: Regenerate.
1163 * rx-decode.c: Regenerate.
1164
e30181a5
YZ		 11652013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1166
1167 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1168 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1169 * aarch64-asm.c (convert_xtl_to_shll): New function.
1170 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1171 calling convert_xtl_to_shll.
1172 * aarch64-dis.c (convert_shll_to_xtl): New function.
1173 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1174 calling convert_shll_to_xtl.
1175 * aarch64-gen.c: Update copyright year.
1176 * aarch64-asm-2.c: Re-generate.
1177 * aarch64-dis-2.c: Re-generate.
1178 * aarch64-opc-2.c: Re-generate.
1179
78c8d46c
NC		 11802013-01-24 Nick Clifton <nickc@redhat.com>
1181
1182 * v850-dis.c: Add support for e3v5 architecture.
1183 * v850-opc.c: Likewise.
1184
f5555712
YZ		 11852013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1186
1187 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1188 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1189 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 1190 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 1191 alignment check; change to call set_sft_amount_out_of_range_error
1192 instead of set_imm_out_of_range_error.
1193 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1194 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1195 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1196 SIMD_IMM_SFT.
1197
2f81ff92
L		 11982013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1199
1200 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1201
1202 * i386-init.h: Regenerated.
1203 * i386-tbl.h: Likewise.
1204
dd42f060
NC		 12052013-01-15 Nick Clifton <nickc@redhat.com>
1206
1207 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1208 values.
1209 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1210
a4533ed8
NC		 12112013-01-14 Will Newton <will.newton@imgtec.com>
1212
1213 * metag-dis.c (REG_WIDTH): Increase to 64.
1214
5817ffd1
PB		 12152013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1216
1217 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1218 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1219 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1220 (SH6): Update.
1221 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1222 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1223 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1224 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1225
a3c62988
NC		 12262013-01-10 Will Newton <will.newton@imgtec.com>
1227
1228 * Makefile.am: Add Meta.
1229 * configure.in: Add Meta.
1230 * disassemble.c: Add Meta support.
1231 * metag-dis.c: New file.
1232 * Makefile.in: Regenerate.
1233 * configure: Regenerate.
1234
73335eae
NC		 12352013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1236
1237 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1238 (match_opcode): Rename to cr16_match_opcode.
1239
e407c74b
NC		 12402013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1241
1242 * mips-dis.c: Add names for CP0 registers of r5900.
1243 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1244 instructions sq and lq.
1245 Add support for MIPS r5900 CPU.
1246 Add support for 128 bit MMI (Multimedia Instructions).
1247 Add support for EE instructions (Emotion Engine).
1248 Disable unsupported floating point instructions (64 bit and
1249 undefined compare operations).
1250 Enable instructions of MIPS ISA IV which are supported by r5900.
1251 Disable 64 bit co processor instructions.
1252 Disable 64 bit multiplication and division instructions.
1253 Disable instructions for co-processor 2 and 3, because these are
1254 not supported (preparation for later VU0 support (Vector Unit)).
1255 Disable cvt.w.s because this behaves like trunc.w.s and the
1256 correct execution can't be ensured on r5900.
1257 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1258 will confuse less developers and compilers.
1259
a32c3ff8
NC		 12602013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1261
fb098a1e
YZ		 1262 * aarch64-opc.c (aarch64_print_operand): Change to print
1263 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1264 in comment.
1265 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1266 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1267 OP_MOV_IMM_WIDE.
1268
12692013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1270
1271 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1272 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1273
62658407
L		 12742013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1275
1276 * i386-gen.c (process_copyright): Update copyright year to 2013.
1277
bab4becb 12782013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1279
bab4becb
NC		 1280 * cr16-dis.c (match_opcode,make_instruction): Remove static
1281 declaration.
1282 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1283 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1284
bab4becb 1285For older changes see ChangeLog-2012
252b5132 1286\f
bab4becb 1287Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1288
1289Copying and distribution of this file, with or without modification,
1290are permitted in any medium without royalty provided the copyright
1291notice and this notice are preserved.
1292
252b5132 1293Local Variables:
2f6d2f85
NC		 1294mode: change-log
1295left-margin: 8
1296fill-column: 74
252b5132
RH		 1297version-control: never
1298End:
GDB Binutils - Deliverables
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