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PR binutils/15834
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9aff4b7a
NC		 12013-08-23 Yuri Chornoivan <yurchor@ukr.net>
2
3 PR binutils/15834
4 * aarch64-asm.c: Fix typos.
5 * aarch64-dis.c: Likewise.
6 * msp430-dis.c: Likewise.
7
5e0dc5ba
RS		 82013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
9
10 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
11 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
12 Use +H rather than +C for the real "dext".
13 * mips-opc.c (mips_builtin_opcodes): Likewise.
14
0f35dbc4
RS		 152013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
16
17 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
18 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
19 and OPTIONAL_MAPPED_REG.
20 * mips-opc.c (decode_mips_operand): Likewise.
21 * mips16-opc.c (decode_mips16_operand): Likewise.
22 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
23
79ceb7cb
L		 242013-08-19 H.J. Lu <hongjiu.lu@intel.com>
25
26 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
27 (PREFIX_EVEX_0F3A3F): Likewise.
28 * i386-dis-evex.h (evex_table): Updated.
29
ee5734f0
RS		 302013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
31
32 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
33 VCLIPW.
34
d6787ef9
EB		 352013-08-05 Eric Botcazou <ebotcazou@adacore.com>
36 Konrad Eisele <konrad@gaisler.com>
37
38 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
39 bfd_mach_sparc.
40 * sparc-opc.c (MASK_LEON): Define.
41 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
42 (letandleon): New macro.
43 (v9andleon): Likewise.
44 (sparc_opc): Add leon.
45 (umac): Enable for letandleon.
46 (smac): Likewise.
47 (casa): Enable for v9andleon.
48 (cas): Likewise.
49 (casl): Likewise.
50
14daeee3
RS		 512013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
52 Richard Sandiford <rdsandiford@googlemail.com>
53
54 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
55 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
56 (print_vu0_channel): New function.
57 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
58 (print_insn_args): Handle '#'.
59 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
60 * mips-opc.c (mips_vu0_channel_mask): New constant.
61 (decode_mips_operand): Handle new VU0 operand types.
62 (VU0, VU0CH): New macros.
63 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
64 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
65 Use "+6" rather than "G" for QMFC2 and QMTC2.
66
3ccad066
RS		 672013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
68
69 * mips-formats.h (PCREL): Reorder parameters and update the definition
70 to match new mips_pcrel_operand layout.
71 (JUMP, JALX, BRANCH): Update accordingly.
72 * mips16-opc.c (decode_mips16_operand): Likewise.
73
df34fbcc
RS		 742013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
75
76 * micromips-opc.c (WR_s): Delete.
77
fc76e730
RS		 782013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
79
80 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
81 New macros.
82 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
83 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
84 (mips_builtin_opcodes): Use the new position-based read-write flags
85 instead of field-based ones. Use UDI for "udi..." instructions.
86 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
87 New macros.
88 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
89 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
90 (WR_SP, RD_16): New macros.
91 (RD_SP): Redefine as an INSN2_* flag.
92 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
93 (mips16_opcodes): Use the new position-based read-write flags
94 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
95 pinfo2 field.
96 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
97 New macros.
98 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
99 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
100 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
101 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
102 (micromips_opcodes): Use the new position-based read-write flags
103 instead of field-based ones.
104 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
105 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
106 of field-based flags.
107
26545944
RS		 1082013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
109
110 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
111 (WR_SP): Replace with...
112 (MOD_SP): ...this.
113 (mips16_opcodes): Update accordingly.
114 * mips-dis.c (print_insn_mips16): Likewise.
115
a8d92fc6
RS		 1162013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
117
118 * mips16-opc.c (mips16_opcodes): Reformat.
119
6a819047
RS		 1202013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
121
122 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
123 for operands that are hard-coded to $0.
124 * micromips-opc.c (micromips_opcodes): Likewise.
125
344c74a6
RS		 1262013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
127
128 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
129 for the single-operand forms of JALR and JALR.HB.
130 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
131 and JALRS.HB.
132
41989114
RS		 1332013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
134
135 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
136 instructions. Fix them to use WR_MACC instead of WR_CC and
137 add missing RD_MACCs.
138
6d075bce
RS		 1392013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
140
141 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
142
4f6ffcd3
PB		 1432013-07-29 Peter Bergner <bergner@vnet.ibm.com>
144
145 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
146
43234a1e
L		 1472013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
148 Alexander Ivchenko <alexander.ivchenko@intel.com>
149 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
150 Sergey Lega <sergey.s.lega@intel.com>
151 Anna Tikhonova <anna.tikhonova@intel.com>
152 Ilya Tocar <ilya.tocar@intel.com>
153 Andrey Turetskiy <andrey.turetskiy@intel.com>
154 Ilya Verbin <ilya.verbin@intel.com>
155 Kirill Yukhin <kirill.yukhin@intel.com>
156 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
157
158 * i386-dis-evex.h: New.
159 * i386-dis.c (OP_Rounding): New.
160 (VPCMP_Fixup): New.
161 (OP_Mask): New.
162 (Rdq): New.
163 (XMxmmq): New.
164 (EXdScalarS): New.
165 (EXymm): New.
166 (EXEvexHalfBcstXmmq): New.
167 (EXxmm_mdq): New.
168 (EXEvexXGscat): New.
169 (EXEvexXNoBcst): New.
170 (VPCMP): New.
171 (EXxEVexR): New.
172 (EXxEVexS): New.
173 (XMask): New.
174 (MaskG): New.
175 (MaskE): New.
176 (MaskR): New.
177 (MaskVex): New.
178 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
179 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
180 evex_rounding_mode, evex_sae_mode, mask_mode.
181 (USE_EVEX_TABLE): New.
182 (EVEX_TABLE): New.
183 (EVEX enum): New.
184 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
185 REG_EVEX_0F38C7.
186 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
187 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
188 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
189 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
190 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
191 MOD_EVEX_0F38C7_REG_6.
192 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
193 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
194 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
195 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
196 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
197 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
198 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
199 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
200 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
201 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
202 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
203 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
204 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
205 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
206 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
207 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
208 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
209 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
210 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
211 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
212 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
213 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
214 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
215 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
216 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
217 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
218 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
219 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
220 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
221 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
222 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
223 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
224 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
225 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
226 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
227 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
228 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
229 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
230 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
231 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
232 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
233 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
234 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
235 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
236 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
237 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
238 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
239 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
240 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
241 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
242 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
243 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
244 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
245 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
246 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
247 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
248 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
249 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
250 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
251 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
252 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
253 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
254 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
255 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
256 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
257 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
258 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
259 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
260 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
261 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
262 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
263 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
264 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
265 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
266 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
267 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
268 PREFIX_EVEX_0F3A55.
269 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
270 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
271 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
272 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
273 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
274 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
275 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
276 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
277 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
278 VEX_W_0F3A32_P_2_LEN_0.
279 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
280 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
281 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
282 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
283 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
284 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
285 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
286 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
287 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
288 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
289 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
290 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
291 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
292 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
293 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
294 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
295 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
296 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
297 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
298 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
299 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
300 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
301 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
302 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
303 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
304 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
305 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
306 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
307 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
308 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
309 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
310 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
311 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
312 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
313 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
314 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
315 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
316 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
317 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
318 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
319 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
320 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
321 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
322 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
323 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
324 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
325 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
326 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
327 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
328 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
329 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
330 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
331 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
332 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
333 (struct vex): Add fields evex, r, v, mask_register_specifier,
334 zeroing, ll, b.
335 (intel_names_xmm): Add upper 16 registers.
336 (att_names_xmm): Ditto.
337 (intel_names_ymm): Ditto.
338 (att_names_ymm): Ditto.
339 (names_zmm): New.
340 (intel_names_zmm): Ditto.
341 (att_names_zmm): Ditto.
342 (names_mask): Ditto.
343 (intel_names_mask): Ditto.
344 (att_names_mask): Ditto.
345 (names_rounding): Ditto.
346 (names_broadcast): Ditto.
347 (x86_64_table): Add escape to evex-table.
348 (reg_table): Include reg_table evex-entries from
349 i386-dis-evex.h. Fix prefetchwt1 instruction.
350 (prefix_table): Add entries for new instructions.
351 (vex_table): Ditto.
352 (vex_len_table): Ditto.
353 (vex_w_table): Ditto.
354 (mod_table): Ditto.
355 (get_valid_dis386): Properly handle new instructions.
356 (print_insn): Handle zmm and mask registers, print mask operand.
357 (intel_operand_size): Support EVEX, new modes and sizes.
358 (OP_E_register): Handle new modes.
359 (OP_E_memory): Ditto.
360 (OP_G): Ditto.
361 (OP_XMM): Ditto.
362 (OP_EX): Ditto.
363 (OP_VEX): Ditto.
364 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
365 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
366 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
367 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
368 CpuAVX512PF and CpuVREX.
369 (operand_type_init): Add OPERAND_TYPE_REGZMM,
370 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
371 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
372 StaticRounding, SAE, Disp8MemShift, NoDefMask.
373 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
374 * i386-init.h: Regenerate.
375 * i386-opc.h (CpuAVX512F): New.
376 (CpuAVX512CD): New.
377 (CpuAVX512ER): New.
378 (CpuAVX512PF): New.
379 (CpuVREX): New.
380 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
381 cpuavx512pf and cpuvrex fields.
382 (VecSIB): Add VecSIB512.
383 (EVex): New.
384 (Masking): New.
385 (VecESize): New.
386 (Broadcast): New.
387 (StaticRounding): New.
388 (SAE): New.
389 (Disp8MemShift): New.
390 (NoDefMask): New.
391 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
392 staticrounding, sae, disp8memshift and nodefmask.
393 (RegZMM): New.
394 (Zmmword): Ditto.
395 (Vec_Disp8): Ditto.
396 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
397 fields.
398 (RegVRex): New.
399 * i386-opc.tbl: Add AVX512 instructions.
400 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
401 registers, mask registers.
402 * i386-tbl.h: Regenerate.
403
1d2db237
RS		 4042013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
405
406 PR gas/15220
407 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
408 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
409
a0046408
L		 4102013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
411
412 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
413 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
414 PREFIX_0F3ACC.
415 (prefix_table): Updated.
416 (three_byte_table): Likewise.
417 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
418 (cpu_flags): Add CpuSHA.
419 (i386_cpu_flags): Add cpusha.
420 * i386-init.h: Regenerate.
421 * i386-opc.h (CpuSHA): New.
422 (CpuUnused): Restored.
423 (i386_cpu_flags): Add cpusha.
424 * i386-opc.tbl: Add SHA instructions.
425 * i386-tbl.h: Regenerate.
426
7e8b059b
L		 4272013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
428 Kirill Yukhin <kirill.yukhin@intel.com>
429 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
430
431 * i386-dis.c (BND_Fixup): New.
432 (Ebnd): New.
433 (Ev_bnd): New.
434 (Gbnd): New.
435 (BND): New.
436 (v_bnd_mode): New.
437 (bnd_mode): New.
c623f86c
L		 438 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
439 MOD_0F1B_PREFIX_1.
440 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 441 (dis tables): Replace XX with BND for near branch and call
442 instructions.
443 (prefix_table): Add new entries.
444 (mod_table): Likewise.
445 (names_bnd): New.
446 (intel_names_bnd): New.
447 (att_names_bnd): New.
448 (BND_PREFIX): New.
449 (prefix_name): Handle BND_PREFIX.
450 (print_insn): Initialize names_bnd.
451 (intel_operand_size): Handle new modes.
452 (OP_E_register): Likewise.
453 (OP_E_memory): Likewise.
454 (OP_G): Likewise.
455 * i386-gen.c (cpu_flag_init): Add CpuMPX.
456 (cpu_flags): Add CpuMPX.
457 (operand_type_init): Add RegBND.
458 (opcode_modifiers): Add BNDPrefixOk.
459 (operand_types): Add RegBND.
460 * i386-init.h: Regenerate.
461 * i386-opc.h (CpuMPX): New.
462 (CpuUnused): Comment out.
463 (i386_cpu_flags): Add cpumpx.
464 (BNDPrefixOk): New.
465 (i386_opcode_modifier): Add bndprefixok.
466 (RegBND): New.
467 (i386_operand_type): Add regbnd.
468 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
469 Add MPX instructions and bnd prefix.
470 * i386-reg.tbl: Add bnd0-bnd3 registers.
471 * i386-tbl.h: Regenerate.
472
b56e23fb
RS		 4732013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
474
475 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
476 ATTRIBUTE_UNUSED.
477
e7ae278d
RS		 4782013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
479
480 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
481 special rules.
482 * Makefile.in: Regenerate.
483 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
484 all fields. Reformat.
485
c3c07478
RS		 4862013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
487
488 * mips16-opc.c: Include mips-formats.h.
489 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
490 static arrays.
491 (decode_mips16_operand): New function.
492 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
493 (print_insn_arg): Handle OP_ENTRY_EXIT list.
494 Abort for OP_SAVE_RESTORE_LIST.
495 (print_mips16_insn_arg): Change interface. Use mips_operand
496 structures. Delete GET_OP_S. Move GET_OP definition to...
497 (print_insn_mips16): ...here. Call init_print_arg_state.
498 Update the call to print_mips16_insn_arg.
499
ab902481
RS		 5002013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
501
502 * mips-formats.h: New file.
503 * mips-opc.c: Include mips-formats.h.
504 (reg_0_map): New static array.
505 (decode_mips_operand): New function.
506 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
507 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
508 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
509 (int_c_map): New static arrays.
510 (decode_micromips_operand): New function.
511 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
512 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
513 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
514 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
515 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
516 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
517 (micromips_imm_b_map, micromips_imm_c_map): Delete.
518 (print_reg): New function.
519 (mips_print_arg_state): New structure.
520 (init_print_arg_state, print_insn_arg): New functions.
521 (print_insn_args): Change interface and use mips_operand structures.
522 Delete GET_OP_S. Move GET_OP definition to...
523 (print_insn_mips): ...here. Update the call to print_insn_args.
524 (print_insn_micromips): Use print_insn_args.
525
cc537e56
RS		 5262013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
527
528 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
529 in macros.
530
7a5f87ce
RS		 5312013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
532
533 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
534 ADDA.S, MULA.S and SUBA.S.
535
41741fa4
L		 5362013-07-08 H.J. Lu <hongjiu.lu@intel.com>
537
538 PR gas/13572
539 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
540 * i386-tbl.h: Regenerated.
541
f2ae14a1
RS		 5422013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
543
544 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
545 and SD A(B) macros up.
546 * micromips-opc.c (micromips_opcodes): Likewise.
547
04c9d415
RS		 5482013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
549
550 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
551 instructions.
552
5c324c16
RS		 5532013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
554
555 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
556 MDMX-like instructions.
557 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
558 printing "Q" operands for INSN_5400 instructions.
559
23e69e47
RS		 5602013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
561
562 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
563 "+S" for "cins".
564 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
565 Combine cases.
566
27c5c572
RS		 5672013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
568
569 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
570 "jalx".
571 * mips16-opc.c (mips16_opcodes): Likewise.
572 * micromips-opc.c (micromips_opcodes): Likewise.
573 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
574 (print_insn_mips16): Handle "+i".
575 (print_insn_micromips): Likewise. Conditionally preserve the
576 ISA bit for "a" but not for "+i".
577
e76ff5ab
RS		 5782013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
579
580 * micromips-opc.c (WR_mhi): Rename to..
581 (WR_mh): ...this.
582 (micromips_opcodes): Update "movep" entry accordingly. Replace
583 "mh,mi" with "mh".
584 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
585 (micromips_to_32_reg_h_map1): ...this.
586 (micromips_to_32_reg_i_map): Rename to...
587 (micromips_to_32_reg_h_map2): ...this.
588 (print_micromips_insn): Remove "mi" case. Print both registers
589 in the pair for "mh".
590
fa7616a4
RS		 5912013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
592
593 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
594 * micromips-opc.c (micromips_opcodes): Likewise.
595 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
596 and "+T" handling. Check for a "0" suffix when deciding whether to
597 use coprocessor 0 names. In that case, also check for ",H" selectors.
598
fb798c50
AK		 5992013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
600
601 * s390-opc.c (J12_12, J24_24): New macros.
602 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
603 (MASK_MII_UPI): Rename to MASK_MII_UPP.
604 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
605
58ae08f2
AM		 6062013-07-04 Alan Modra <amodra@gmail.com>
607
608 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
609
b5e04c2b
NC		 6102013-06-26 Nick Clifton <nickc@redhat.com>
611
612 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
613 field when checking for type 2 nop.
614 * rx-decode.c: Regenerate.
615
833794fc
MR		 6162013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
617
618 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
619 and "movep" macros.
620
1bbce132
MR		 6212013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
622
623 * mips-dis.c (is_mips16_plt_tail): New function.
624 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
625 word.
626 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
627
34c911a4
NC		 6282013-06-21 DJ Delorie <dj@redhat.com>
629
630 * msp430-decode.opc: New.
631 * msp430-decode.c: New/generated.
632 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
633 (MAINTAINER_CLEANFILES): Likewise.
634 Add rule to build msp430-decode.c frommsp430decode.opc
635 using the opc2c program.
636 * Makefile.in: Regenerate.
637 * configure.in: Add msp430-decode.lo to msp430 architecture files.
638 * configure: Regenerate.
639
b9eead84
YZ		 6402013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
641
642 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
643 (SYMTAB_AVAILABLE): Removed.
644 (#include "elf/aarch64.h): Ditto.
645
7f3c4072
CM		 6462013-06-17 Catherine Moore <clm@codesourcery.com>
647 Maciej W. Rozycki <macro@codesourcery.com>
648 Chao-Ying Fu <fu@mips.com>
649
650 * micromips-opc.c (EVA): Define.
651 (TLBINV): Define.
652 (micromips_opcodes): Add EVA opcodes.
653 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
654 (print_insn_args): Handle EVA offsets.
655 (print_insn_micromips): Likewise.
656 * mips-opc.c (EVA): Define.
657 (TLBINV): Define.
658 (mips_builtin_opcodes): Add EVA opcodes.
659
de40ceb6
AM		 6602013-06-17 Alan Modra <amodra@gmail.com>
661
662 * Makefile.am (mips-opc.lo): Add rules to create automatic
663 dependency files. Pass archdefs.
664 (micromips-opc.lo, mips16-opc.lo): Likewise.
665 * Makefile.in: Regenerate.
666
3531d549
DD		 6672013-06-14 DJ Delorie <dj@redhat.com>
668
669 * rx-decode.opc (rx_decode_opcode): Bit operations on
670 registers are 32-bit operations, not 8-bit operations.
671 * rx-decode.c: Regenerate.
672
ba92f7fb
CF		 6732013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
674
675 * micromips-opc.c (IVIRT): New define.
676 (IVIRT64): New define.
677 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
678 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
679
680 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
681 dmtgc0 to print cp0 names.
682
9daf7bab
SL		 6832013-06-09 Sandra Loosemore <sandra@codesourcery.com>
684
685 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
686 argument.
687
d301a56b
RS		 6882013-06-08 Catherine Moore <clm@codesourcery.com>
689 Richard Sandiford <rdsandiford@googlemail.com>
690
691 * micromips-opc.c (D32, D33, MC): Update definitions.
692 (micromips_opcodes): Initialize ase field.
693 * mips-dis.c (mips_arch_choice): Add ase field.
694 (mips_arch_choices): Initialize ase field.
695 (set_default_mips_dis_options): Declare and setup mips_ase.
696 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
697 MT32, MC): Update definitions.
698 (mips_builtin_opcodes): Initialize ase field.
699
a3dcb6c5
RS		 7002013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
701
702 * s390-opc.txt (flogr): Require a register pair destination.
703
6cf1d90c
AK		 7042013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
705
706 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
707 instruction format.
708
c77c0862
RS		 7092013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
710
711 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
712
c0637f3a
PB		 7132013-05-20 Peter Bergner <bergner@vnet.ibm.com>
714
715 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
716 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
717 XLS_MASK, PPCVSX2): New defines.
718 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
719 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
720 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
721 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
722 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
723 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
724 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
725 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
726 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
727 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
728 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
729 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
730 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
731 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
732 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
733 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
734 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
735 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
736 <lxvx, stxvx>: New extended mnemonics.
737
4934fdaf
AM		 7382013-05-17 Alan Modra <amodra@gmail.com>
739
740 * ia64-raw.tbl: Replace non-ASCII char.
741 * ia64-waw.tbl: Likewise.
742 * ia64-asmtab.c: Regenerate.
743
6091d651
SE		 7442013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
745
746 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
747 * i386-init.h: Regenerated.
748
d2865ed3
YZ		 7492013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
750
751 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
752 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
753 check from [0, 255] to [-128, 255].
754
b015e599
AP		 7552013-05-09 Andrew Pinski <apinski@cavium.com>
756
757 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
758 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
759 (parse_mips_dis_option): Handle the virt option.
760 (print_insn_args): Handle "+J".
761 (print_mips_disassembler_options): Print out message about virt64.
762 * mips-opc.c (IVIRT): New define.
763 (IVIRT64): New define.
764 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
765 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
766 Move rfe to the bottom as it conflicts with tlbgp.
767
9f0682fe
AM		 7682013-05-09 Alan Modra <amodra@gmail.com>
769
770 * ppc-opc.c (extract_vlesi): Properly sign extend.
771 (extract_vlensi): Likewise. Comment reason for setting invalid.
772
13761a11
NC		 7732013-05-02 Nick Clifton <nickc@redhat.com>
774
775 * msp430-dis.c: Add support for MSP430X instructions.
776
e3031850
SL		 7772013-04-24 Sandra Loosemore <sandra@codesourcery.com>
778
779 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
780 to "eccinj".
781
17310e56
NC		 7822013-04-17 Wei-chen Wang <cole945@gmail.com>
783
784 PR binutils/15369
785 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
786 of CGEN_CPU_ENDIAN.
787 (hash_insns_list): Likewise.
788
731df338
JK		 7892013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
790
791 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
792 warning workaround.
793
5f77db52
JB		 7942013-04-08 Jan Beulich <jbeulich@suse.com>
795
796 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
797 * i386-tbl.h: Re-generate.
798
0afd1215
DM		 7992013-04-06 David S. Miller <davem@davemloft.net>
800
801 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
802 of an opcode, prefer the one with F_PREFERRED set.
803 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
804 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
805 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
806 mark existing mnenomics as aliases. Add "cc" suffix to edge
807 instructions generating condition codes, mark existing mnenomics
808 as aliases. Add "fp" prefix to VIS compare instructions, mark
809 existing mnenomics as aliases.
810
41702d50
NC		 8112013-04-03 Nick Clifton <nickc@redhat.com>
812
813 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
814 destination address by subtracting the operand from the current
815 address.
816 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
817 a positive value in the insn.
818 (extract_u16_loop): Do not negate the returned value.
819 (D16_LOOP): Add V850_INVERSE_PCREL flag.
820
821 (ceilf.sw): Remove duplicate entry.
822 (cvtf.hs): New entry.
823 (cvtf.sh): Likewise.
824 (fmaf.s): Likewise.
825 (fmsf.s): Likewise.
826 (fnmaf.s): Likewise.
827 (fnmsf.s): Likewise.
828 (maddf.s): Restrict to E3V5 architectures.
829 (msubf.s): Likewise.
830 (nmaddf.s): Likewise.
831 (nmsubf.s): Likewise.
832
55cf16e1
L		 8332013-03-27 H.J. Lu <hongjiu.lu@intel.com>
834
835 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
836 check address mode.
837 (print_insn): Pass sizeflag to get_sib.
838
51dcdd4d
NC		 8392013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
840
841 PR binutils/15068
842 * tic6x-dis.c: Add support for displaying 16-bit insns.
843
795b8e6b
NC		 8442013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
845
846 PR gas/15095
847 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
848 individual msb and lsb halves in src1 & src2 fields. Discard the
849 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
850 follow what Ti SDK does in that case as any value in the src1
851 field yields the same output with SDK disassembler.
852
314d60dd
ME		 8532013-03-12 Michael Eager <eager@eagercon.com>
854
795b8e6b 855 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 856
dad60f8e
SL		 8572013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
858
859 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
860
f5cb796a
SL		 8612013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
862
863 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
864
21fde85c
SL		 8652013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
866
867 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
868
dd5181d5
KT		 8692013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
870
871 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
872 (thumb32_opcodes): Likewise.
873 (print_insn_thumb32): Handle 'S' control char.
874
87a8d6cb
NC		 8752013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
876
877 * lm32-desc.c: Regenerate.
878
99dce992
L		 8792013-03-01 H.J. Lu <hongjiu.lu@intel.com>
880
881 * i386-reg.tbl (riz): Add RegRex64.
882 * i386-tbl.h: Regenerated.
883
e60bb1dd
YZ		 8842013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
885
886 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
887 (aarch64_feature_crc): New static.
888 (CRC): New macro.
889 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
890 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
891 * aarch64-asm-2.c: Re-generate.
892 * aarch64-dis-2.c: Ditto.
893 * aarch64-opc-2.c: Ditto.
894
c7570fcd
AM		 8952013-02-27 Alan Modra <amodra@gmail.com>
896
897 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
898 * rl78-decode.c: Regenerate.
899
151fa98f
NC		 9002013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
901
902 * rl78-decode.opc: Fix encoding of DIVWU insn.
903 * rl78-decode.c: Regenerate.
904
5c111e37
L		 9052013-02-19 H.J. Lu <hongjiu.lu@intel.com>
906
907 PR gas/15159
908 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
909
910 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
911 (cpu_flags): Add CpuSMAP.
912
913 * i386-opc.h (CpuSMAP): New.
914 (i386_cpu_flags): Add cpusmap.
915
916 * i386-opc.tbl: Add clac and stac.
917
918 * i386-init.h: Regenerated.
919 * i386-tbl.h: Likewise.
920
9d1df426
NC		 9212013-02-15 Markos Chandras <markos.chandras@imgtec.com>
922
923 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
924 which also makes the disassembler output be in little
925 endian like it should be.
926
a1ccaec9
YZ		 9272013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
928
929 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
930 fields to NULL.
931 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
932
ef068ef4 9332013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 934
935 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
936 section disassembled.
937
6fe6ded9
RE		 9382013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
939
940 * arm-dis.c: Update strht pattern.
941
0aa27725
RS		 9422013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
943
944 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
945 single-float. Disable ll, lld, sc and scd for EE. Disable the
946 trunc.w.s macro for EE.
947
36591ba1
SL		 9482013-02-06 Sandra Loosemore <sandra@codesourcery.com>
949 Andrew Jenner <andrew@codesourcery.com>
950
951 Based on patches from Altera Corporation.
952
953 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
954 nios2-opc.c.
955 * Makefile.in: Regenerated.
956 * configure.in: Add case for bfd_nios2_arch.
957 * configure: Regenerated.
958 * disassemble.c (ARCH_nios2): Define.
959 (disassembler): Add case for bfd_arch_nios2.
960 * nios2-dis.c: New file.
961 * nios2-opc.c: New file.
962
545093a4
AM		 9632013-02-04 Alan Modra <amodra@gmail.com>
964
965 * po/POTFILES.in: Regenerate.
966 * rl78-decode.c: Regenerate.
967 * rx-decode.c: Regenerate.
968
e30181a5
YZ		 9692013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
970
971 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
972 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
973 * aarch64-asm.c (convert_xtl_to_shll): New function.
974 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
975 calling convert_xtl_to_shll.
976 * aarch64-dis.c (convert_shll_to_xtl): New function.
977 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
978 calling convert_shll_to_xtl.
979 * aarch64-gen.c: Update copyright year.
980 * aarch64-asm-2.c: Re-generate.
981 * aarch64-dis-2.c: Re-generate.
982 * aarch64-opc-2.c: Re-generate.
983
78c8d46c
NC		 9842013-01-24 Nick Clifton <nickc@redhat.com>
985
986 * v850-dis.c: Add support for e3v5 architecture.
987 * v850-opc.c: Likewise.
988
f5555712
YZ		 9892013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
990
991 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
992 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
993 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 994 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 995 alignment check; change to call set_sft_amount_out_of_range_error
996 instead of set_imm_out_of_range_error.
997 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
998 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
999 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1000 SIMD_IMM_SFT.
1001
2f81ff92
L		 10022013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1003
1004 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1005
1006 * i386-init.h: Regenerated.
1007 * i386-tbl.h: Likewise.
1008
dd42f060
NC		 10092013-01-15 Nick Clifton <nickc@redhat.com>
1010
1011 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1012 values.
1013 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1014
a4533ed8
NC		 10152013-01-14 Will Newton <will.newton@imgtec.com>
1016
1017 * metag-dis.c (REG_WIDTH): Increase to 64.
1018
5817ffd1
PB		 10192013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1020
1021 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1022 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1023 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1024 (SH6): Update.
1025 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1026 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1027 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1028 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1029
a3c62988
NC		 10302013-01-10 Will Newton <will.newton@imgtec.com>
1031
1032 * Makefile.am: Add Meta.
1033 * configure.in: Add Meta.
1034 * disassemble.c: Add Meta support.
1035 * metag-dis.c: New file.
1036 * Makefile.in: Regenerate.
1037 * configure: Regenerate.
1038
73335eae
NC		 10392013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1040
1041 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1042 (match_opcode): Rename to cr16_match_opcode.
1043
e407c74b
NC		 10442013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1045
1046 * mips-dis.c: Add names for CP0 registers of r5900.
1047 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1048 instructions sq and lq.
1049 Add support for MIPS r5900 CPU.
1050 Add support for 128 bit MMI (Multimedia Instructions).
1051 Add support for EE instructions (Emotion Engine).
1052 Disable unsupported floating point instructions (64 bit and
1053 undefined compare operations).
1054 Enable instructions of MIPS ISA IV which are supported by r5900.
1055 Disable 64 bit co processor instructions.
1056 Disable 64 bit multiplication and division instructions.
1057 Disable instructions for co-processor 2 and 3, because these are
1058 not supported (preparation for later VU0 support (Vector Unit)).
1059 Disable cvt.w.s because this behaves like trunc.w.s and the
1060 correct execution can't be ensured on r5900.
1061 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1062 will confuse less developers and compilers.
1063
a32c3ff8
NC		 10642013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1065
fb098a1e
YZ		 1066 * aarch64-opc.c (aarch64_print_operand): Change to print
1067 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1068 in comment.
1069 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1070 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1071 OP_MOV_IMM_WIDE.
1072
10732013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1074
1075 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1076 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1077
62658407
L		 10782013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1079
1080 * i386-gen.c (process_copyright): Update copyright year to 2013.
1081
bab4becb 10822013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1083
bab4becb
NC		 1084 * cr16-dis.c (match_opcode,make_instruction): Remove static
1085 declaration.
1086 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1087 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1088
bab4becb 1089For older changes see ChangeLog-2012
252b5132 1090\f
bab4becb 1091Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1092
1093Copying and distribution of this file, with or without modification,
1094are permitted in any medium without royalty provided the copyright
1095notice and this notice are preserved.
1096
252b5132 1097Local Variables:
2f6d2f85
NC		 1098mode: change-log
1099left-margin: 8
1100fill-column: 74
252b5132
RH		 1101version-control: never
1102End:
GDB Binutils - Deliverables
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