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PR21303, objdump doesn't show e200z4 insns
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9b753937
AM		 12017-03-27 Alan Modra <amodra@gmail.com>
2
3 PR 21303
4 * ppc-dis.c (struct ppc_mopt): Comment.
5 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
6
c0c31e91
RZ		 72017-03-27 Rinat Zelig <rinat@mellanox.com>
8
9 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
10 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
11 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
12 (insert_nps_misc_imm_offset): New function.
13 (extract_nps_misc imm_offset): New function.
14 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
15 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
16
2253c8f0
AK		 172017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
18
19 * s390-mkopc.c (main): Remove vx2 check.
20 * s390-opc.txt: Remove vx2 instruction flags.
21
645d3342
RZ		 222017-03-21 Rinat Zelig <rinat@mellanox.com>
23
24 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
25 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
26 (insert_nps_imm_offset): New function.
27 (extract_nps_imm_offset): New function.
28 (insert_nps_imm_entry): New function.
29 (extract_nps_imm_entry): New function.
30
4b94dd2d
AM		 312017-03-17 Alan Modra <amodra@gmail.com>
32
33 PR 21248
34 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
35 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
36 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
37
b416fe87
KC		 382017-03-14 Kito Cheng <kito.cheng@gmail.com>
39
40 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
41 <c.andi>: Likewise.
42 <c.addiw> Likewise.
43
03b039a5
KC		 442017-03-14 Kito Cheng <kito.cheng@gmail.com>
45
46 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
47
2c232b83
AW		 482017-03-13 Andrew Waterman <andrew@sifive.com>
49
50 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
51 <srl> Likewise.
52 <srai> Likewise.
53 <sra> Likewise.
54
86fa6981
L		 552017-03-09 H.J. Lu <hongjiu.lu@intel.com>
56
57 * i386-gen.c (opcode_modifiers): Replace S with Load.
58 * i386-opc.h (S): Removed.
59 (Load): New.
60 (i386_opcode_modifier): Replace s with load.
61 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
62 and {evex}. Replace S with Load.
63 * i386-tbl.h: Regenerated.
64
c1fe188b
L		 652017-03-09 H.J. Lu <hongjiu.lu@intel.com>
66
67 * i386-opc.tbl: Use CpuCET on rdsspq.
68 * i386-tbl.h: Regenerated.
69
4b8b687e
PB		 702017-03-08 Peter Bergner <bergner@vnet.ibm.com>
71
72 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
73 <vsx>: Do not use PPC_OPCODE_VSX3;
74
1437d063
PB		 752017-03-08 Peter Bergner <bergner@vnet.ibm.com>
76
77 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
78
603555e5
L		 792017-03-06 H.J. Lu <hongjiu.lu@intel.com>
80
81 * i386-dis.c (REG_0F1E_MOD_3): New enum.
82 (MOD_0F1E_PREFIX_1): Likewise.
83 (MOD_0F38F5_PREFIX_2): Likewise.
84 (MOD_0F38F6_PREFIX_0): Likewise.
85 (RM_0F1E_MOD_3_REG_7): Likewise.
86 (PREFIX_MOD_0_0F01_REG_5): Likewise.
87 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
88 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
89 (PREFIX_0F1E): Likewise.
90 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
91 (PREFIX_0F38F5): Likewise.
92 (dis386_twobyte): Use PREFIX_0F1E.
93 (reg_table): Add REG_0F1E_MOD_3.
94 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
95 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
96 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
97 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
98 (three_byte_table): Use PREFIX_0F38F5.
99 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
100 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
101 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
102 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
103 PREFIX_MOD_3_0F01_REG_5_RM_2.
104 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
105 (cpu_flags): Add CpuCET.
106 * i386-opc.h (CpuCET): New enum.
107 (CpuUnused): Commented out.
108 (i386_cpu_flags): Add cpucet.
109 * i386-opc.tbl: Add Intel CET instructions.
110 * i386-init.h: Regenerated.
111 * i386-tbl.h: Likewise.
112
73f07bff
AM		 1132017-03-06 Alan Modra <amodra@gmail.com>
114
115 PR 21124
116 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
117 (extract_raq, extract_ras, extract_rbx): New functions.
118 (powerpc_operands): Use opposite corresponding insert function.
119 (Q_MASK): Define.
120 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
121 register restriction.
122
65b48a81
PB		 1232017-02-28 Peter Bergner <bergner@vnet.ibm.com>
124
125 * disassemble.c Include "safe-ctype.h".
126 (disassemble_init_for_target): Handle s390 init.
127 (remove_whitespace_and_extra_commas): New function.
128 (disassembler_options_cmp): Likewise.
129 * arm-dis.c: Include "libiberty.h".
130 (NUM_ELEM): Delete.
131 (regnames): Use long disassembler style names.
132 Add force-thumb and no-force-thumb options.
133 (NUM_ARM_REGNAMES): Rename from this...
134 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
135 (get_arm_regname_num_options): Delete.
136 (set_arm_regname_option): Likewise.
137 (get_arm_regnames): Likewise.
138 (parse_disassembler_options): Likewise.
139 (parse_arm_disassembler_option): Rename from this...
140 (parse_arm_disassembler_options): ...to this. Make static.
141 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
142 (print_insn): Use parse_arm_disassembler_options.
143 (disassembler_options_arm): New function.
144 (print_arm_disassembler_options): Handle updated regnames.
145 * ppc-dis.c: Include "libiberty.h".
146 (ppc_opts): Add "32" and "64" entries.
147 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
148 (powerpc_init_dialect): Add break to switch statement.
149 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
150 (disassembler_options_powerpc): New function.
151 (print_ppc_disassembler_options): Use ARRAY_SIZE.
152 Remove printing of "32" and "64".
153 * s390-dis.c: Include "libiberty.h".
154 (init_flag): Remove unneeded variable.
155 (struct s390_options_t): New structure type.
156 (options): New structure.
157 (init_disasm): Rename from this...
158 (disassemble_init_s390): ...to this. Add initializations for
159 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
160 (print_insn_s390): Delete call to init_disasm.
161 (disassembler_options_s390): New function.
162 (print_s390_disassembler_options): Print using information from
163 struct 'options'.
164 * po/opcodes.pot: Regenerate.
165
15c7c1d8
JB		 1662017-02-28 Jan Beulich <jbeulich@suse.com>
167
168 * i386-dis.c (PCMPESTR_Fixup): New.
169 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
170 (prefix_table): Use PCMPESTR_Fixup.
171 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
172 PCMPESTR_Fixup.
173 (vex_w_table): Delete VPCMPESTR{I,M} entries.
174 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
175 Split 64-bit and non-64-bit variants.
176 * opcodes/i386-tbl.h: Re-generate.
177
582e12bf
RS		 1782017-02-24 Richard Sandiford <richard.sandiford@arm.com>
179
180 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
181 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
182 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
183 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
184 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
185 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
186 (OP_SVE_V_HSD): New macros.
187 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
188 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
189 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
190 (aarch64_opcode_table): Add new SVE instructions.
191 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
192 for rotation operands. Add new SVE operands.
193 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
194 (ins_sve_quad_index): Likewise.
195 (ins_imm_rotate): Split into...
196 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
197 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
198 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
199 functions.
200 (aarch64_ins_sve_addr_ri_s4): New function.
201 (aarch64_ins_sve_quad_index): Likewise.
202 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
203 * aarch64-asm-2.c: Regenerate.
204 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
205 (ext_sve_quad_index): Likewise.
206 (ext_imm_rotate): Split into...
207 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
208 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
209 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
210 functions.
211 (aarch64_ext_sve_addr_ri_s4): New function.
212 (aarch64_ext_sve_quad_index): Likewise.
213 (aarch64_ext_sve_index): Allow quad indices.
214 (do_misc_decoding): Likewise.
215 * aarch64-dis-2.c: Regenerate.
216 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
217 aarch64_field_kinds.
218 (OPD_F_OD_MASK): Widen by one bit.
219 (OPD_F_NO_ZR): Bump accordingly.
220 (get_operand_field_width): New function.
221 * aarch64-opc.c (fields): Add new SVE fields.
222 (operand_general_constraint_met_p): Handle new SVE operands.
223 (aarch64_print_operand): Likewise.
224 * aarch64-opc-2.c: Regenerate.
225
f482d304
RS		 2262017-02-24 Richard Sandiford <richard.sandiford@arm.com>
227
228 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
229 (aarch64_feature_compnum): ...this.
230 (SIMD_V8_3): Replace with...
231 (COMPNUM): ...this.
232 (CNUM_INSN): New macro.
233 (aarch64_opcode_table): Use it for the complex number instructions.
234
7db2c588
JB		 2352017-02-24 Jan Beulich <jbeulich@suse.com>
236
237 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
238
1e9d41d4
SL		 2392017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
240
241 Add support for associating SPARC ASIs with an architecture level.
242 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
243 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
244 decoding of SPARC ASIs.
245
53c4d625
JB		 2462017-02-23 Jan Beulich <jbeulich@suse.com>
247
248 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
249 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
250
11648de5
JB		 2512017-02-21 Jan Beulich <jbeulich@suse.com>
252
253 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
254 1 (instead of to itself). Correct typo.
255
f98d33be
AW		 2562017-02-14 Andrew Waterman <andrew@sifive.com>
257
258 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
259 pseudoinstructions.
260
773fb663
RS		 2612017-02-15 Richard Sandiford <richard.sandiford@arm.com>
262
263 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
264 (aarch64_sys_reg_supported_p): Handle them.
265
cc07cda6
CZ		 2662017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
267
268 * arc-opc.c (UIMM6_20R): Define.
269 (SIMM12_20): Use above.
270 (SIMM12_20R): Define.
271 (SIMM3_5_S): Use above.
272 (UIMM7_A32_11R_S): Define.
273 (UIMM7_9_S): Use above.
274 (UIMM3_13R_S): Define.
275 (SIMM11_A32_7_S): Use above.
276 (SIMM9_8R): Define.
277 (UIMM10_A32_8_S): Use above.
278 (UIMM8_8R_S): Define.
279 (W6): Use above.
280 (arc_relax_opcodes): Use all above defines.
281
66a5a740
VG		 2822017-02-15 Vineet Gupta <vgupta@synopsys.com>
283
284 * arc-regs.h: Distinguish some of the registers different on
285 ARC700 and HS38 cpus.
286
7e0de605
AM		 2872017-02-14 Alan Modra <amodra@gmail.com>
288
289 PR 21118
290 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
291 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
292
54064fdb
AM		 2932017-02-11 Stafford Horne <shorne@gmail.com>
294 Alan Modra <amodra@gmail.com>
295
296 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
297 Use insn_bytes_value and insn_int_value directly instead. Don't
298 free allocated memory until function exit.
299
dce75bf9
NP		 3002017-02-10 Nicholas Piggin <npiggin@gmail.com>
301
302 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
303
1b7e3d2f
NC		 3042017-02-03 Nick Clifton <nickc@redhat.com>
305
306 PR 21096
307 * aarch64-opc.c (print_register_list): Ensure that the register
308 list index will fir into the tb buffer.
309 (print_register_offset_address): Likewise.
310 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
311
8ec5cf65
AD		 3122017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
313
314 PR 21056
315 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
316 instructions when the previous fetch packet ends with a 32-bit
317 instruction.
318
a1aa5e81
DD		 3192017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
320
321 * pru-opc.c: Remove vague reference to a future GDB port.
322
add3afb2
NC		 3232017-01-20 Nick Clifton <nickc@redhat.com>
324
325 * po/ga.po: Updated Irish translation.
326
c13a63b0
SN		 3272017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
328
329 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
330
9608051a
YQ		 3312017-01-13 Yao Qi <yao.qi@linaro.org>
332
333 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
334 if FETCH_DATA returns 0.
335 (m68k_scan_mask): Likewise.
336 (print_insn_m68k): Update code to handle -1 return value.
337
f622ea96
YQ		 3382017-01-13 Yao Qi <yao.qi@linaro.org>
339
340 * m68k-dis.c (enum print_insn_arg_error): New.
341 (NEXTBYTE): Replace -3 with
342 PRINT_INSN_ARG_MEMORY_ERROR.
343 (NEXTULONG): Likewise.
344 (NEXTSINGLE): Likewise.
345 (NEXTDOUBLE): Likewise.
346 (NEXTDOUBLE): Likewise.
347 (NEXTPACKED): Likewise.
348 (FETCH_ARG): Likewise.
349 (FETCH_DATA): Update comments.
350 (print_insn_arg): Update comments. Replace magic numbers with
351 enum.
352 (match_insn_m68k): Likewise.
353
620214f7
IT		 3542017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
355
356 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
357 * i386-dis-evex.h (evex_table): Updated.
358 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
359 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
360 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
361 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
362 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
363 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
364 * i386-init.h: Regenerate.
365 * i386-tbl.h: Ditto.
366
d95014a2
YQ		 3672017-01-12 Yao Qi <yao.qi@linaro.org>
368
369 * msp430-dis.c (msp430_singleoperand): Return -1 if
370 msp430dis_opcode_signed returns false.
371 (msp430_doubleoperand): Likewise.
372 (msp430_branchinstr): Return -1 if
373 msp430dis_opcode_unsigned returns false.
374 (msp430x_calla_instr): Likewise.
375 (print_insn_msp430): Likewise.
376
0ae60c3e
NC		 3772017-01-05 Nick Clifton <nickc@redhat.com>
378
379 PR 20946
380 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
381 could not be matched.
382 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
383 NULL.
384
d74d4880
SN		 3852017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
386
387 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
388 (aarch64_opcode_table): Use RCPC_INSN.
389
cc917fd9
KC		 3902017-01-03 Kito Cheng <kito.cheng@gmail.com>
391
392 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
393 extension.
394 * riscv-opcodes/all-opcodes: Likewise.
395
b52d3cfc
DP		 3962017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
397
398 * riscv-dis.c (print_insn_args): Add fall through comment.
399
f90c58d5
NC		 4002017-01-03 Nick Clifton <nickc@redhat.com>
401
402 * po/sr.po: New Serbian translation.
403 * configure.ac (ALL_LINGUAS): Add sr.
404 * configure: Regenerate.
405
f47b0d4a
AM		 4062017-01-02 Alan Modra <amodra@gmail.com>
407
408 * epiphany-desc.h: Regenerate.
409 * epiphany-opc.h: Regenerate.
410 * fr30-desc.h: Regenerate.
411 * fr30-opc.h: Regenerate.
412 * frv-desc.h: Regenerate.
413 * frv-opc.h: Regenerate.
414 * ip2k-desc.h: Regenerate.
415 * ip2k-opc.h: Regenerate.
416 * iq2000-desc.h: Regenerate.
417 * iq2000-opc.h: Regenerate.
418 * lm32-desc.h: Regenerate.
419 * lm32-opc.h: Regenerate.
420 * m32c-desc.h: Regenerate.
421 * m32c-opc.h: Regenerate.
422 * m32r-desc.h: Regenerate.
423 * m32r-opc.h: Regenerate.
424 * mep-desc.h: Regenerate.
425 * mep-opc.h: Regenerate.
426 * mt-desc.h: Regenerate.
427 * mt-opc.h: Regenerate.
428 * or1k-desc.h: Regenerate.
429 * or1k-opc.h: Regenerate.
430 * xc16x-desc.h: Regenerate.
431 * xc16x-opc.h: Regenerate.
432 * xstormy16-desc.h: Regenerate.
433 * xstormy16-opc.h: Regenerate.
434
2571583a
AM		 4352017-01-02 Alan Modra <amodra@gmail.com>
436
437 Update year range in copyright notice of all files.
438
5c1ad6b5 439For older changes see ChangeLog-2016
3499769a 440\f
5c1ad6b5 441Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 442
443Copying and distribution of this file, with or without modification,
444are permitted in any medium without royalty provided the copyright
445notice and this notice are preserved.
446
447Local Variables:
448mode: change-log
449left-margin: 8
450fill-column: 74
451version-control: never
452End:
GDB Binutils - Deliverables
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