projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 9ba75c88 GM |
1 | 2016-06-13 Graham Markall <graham.markall@embecosm.com> |
| 2 | ||
| 3 | * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf | |
| 4 | * arc-opc.c: Add flag classes, insert/extract functions, and operands to | |
| 5 | support the above instructions. | |
| 6 | ||
| 14053c19 GM |
7 | 2016-06-13 Graham Markall <graham.markall@embecosm.com> |
| 8 | ||
| 9 | * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb, | |
| 10 | imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms, | |
| 11 | csma, cbba, zncv, and hofs. | |
| 12 | * arc-opc.c: Add flag classes, insert/extract functions, and operands to | |
| 13 | support the above instructions. | |
| 14 | ||
| 15 | 2016-06-06 Graham Markall <graham.markall@embecosm.com> | |
| 16 | ||
| 17 | * arc-nps400-tbl.h: Add andab and orab instructions. | |
| 18 | ||
| 19 | 2016-06-06 Graham Markall <graham.markall@embecosm.com> | |
| 20 | ||
| 21 | * arc-nps400-tbl.h: Add addl-like instructions. | |
| 22 | ||
| 23 | 2016-06-06 Graham Markall <graham.markall@embecosm.com> | |
| 24 | ||
| 25 | * arc-nps400-tbl.h: Add mxb and imxb instructions. | |
| 26 | ||
| 27 | 2016-06-06 Graham Markall <graham.markall@embecosm.com> | |
| 28 | ||
| 29 | * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey | |
| 30 | instructions. | |
| 31 | ||
| b2cc3f6f AK |
32 | 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| 33 | ||
| 34 | * s390-dis.c (option_use_insn_len_bits_p): New file scope | |
| 35 | variable. | |
| 36 | (init_disasm): Handle new command line option "insnlength". | |
| 37 | (print_s390_disassembler_options): Mention new option in help | |
| 38 | output. | |
| 39 | (print_insn_s390): Use the encoded insn length when dumping | |
| 40 | unknown instructions. | |
| 41 | ||
| 1857fe72 DC |
42 | 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com> |
| 43 | ||
| 44 | * avr-dis.c (avr_operand): Add default data address space origin (0x800000) | |
| 45 | to the address and set as symbol address for LDS/ STS immediate operands. | |
| 46 | ||
| 14b57c7c AM |
47 | 2016-06-07 Alan Modra <amodra@gmail.com> |
| 48 | ||
| 49 | * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default | |
| 50 | cpu for "vle" to e500. | |
| 51 | * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE. | |
| 52 | (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise. | |
| 53 | (PPCNONE): Delete, substitute throughout. | |
| 54 | (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated" | |
| 55 | except for major opcode 4 and 31. | |
| 56 | (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags. | |
| 57 | ||
| 4d1464f2 MW |
58 | 2016-06-07 Matthew Wahab <matthew.wahab@arm.com> |
| 59 | ||
| 60 | * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with | |
| 61 | ARM_EXT_RAS in relevant entries. | |
| 62 | ||
| 026122a6 PB |
63 | 2016-06-03 Peter Bergner <bergner@vnet.ibm.com> |
| 64 | ||
| 65 | PR binutils/20196 | |
| 66 | * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable | |
| 67 | opcodes for E6500. | |
| 68 | ||
| 07f5af7d L |
69 | 2016-06-03 H.J. Lu <hongjiu.lu@intel.com> |
| 70 | ||
| 71 | PR binutis/18386 | |
| 72 | * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode. | |
| 73 | (indir_v_mode): New. | |
| 74 | Add comments for '&'. | |
| 75 | (reg_table): Replace "{T|}" with "{&|}" on call and jmp. | |
| 76 | (putop): Handle '&'. | |
| 77 | (intel_operand_size): Handle indir_v_mode. | |
| 78 | (OP_E_register): Likewise. | |
| 79 | * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add | |
| 80 | 64-bit indirect call/jmp for AMD64. | |
| 81 | * i386-tbl.h: Regenerated | |
| 82 | ||
| 4eb6f892 AB |
83 | 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com> |
| 84 | ||
| 85 | * arc-dis.c (struct arc_operand_iterator): New structure. | |
| 86 | (find_format_from_table): All the old content from find_format, | |
| 87 | with some minor adjustments, and parameter renaming. | |
| 88 | (find_format_long_instructions): New function. | |
| 89 | (find_format): Rewritten. | |
| 90 | (arc_insn_length): Add LSB parameter. | |
| 91 | (extract_operand_value): New function. | |
| 92 | (operand_iterator_next): New function. | |
| 93 | (print_insn_arc): Use new functions to find opcode, and iterator | |
| 94 | over operands. | |
| 95 | * arc-opc.c (insert_nps_3bit_dst_short): New function. | |
| 96 | (extract_nps_3bit_dst_short): New function. | |
| 97 | (insert_nps_3bit_src2_short): New function. | |
| 98 | (extract_nps_3bit_src2_short): New function. | |
| 99 | (insert_nps_bitop1_size): New function. | |
| 100 | (extract_nps_bitop1_size): New function. | |
| 101 | (insert_nps_bitop2_size): New function. | |
| 102 | (extract_nps_bitop2_size): New function. | |
| 103 | (insert_nps_bitop_mod4_msb): New function. | |
| 104 | (extract_nps_bitop_mod4_msb): New function. | |
| 105 | (insert_nps_bitop_mod4_lsb): New function. | |
| 106 | (extract_nps_bitop_mod4_lsb): New function. | |
| 107 | (insert_nps_bitop_dst_pos3_pos4): New function. | |
| 108 | (extract_nps_bitop_dst_pos3_pos4): New function. | |
| 109 | (insert_nps_bitop_ins_ext): New function. | |
| 110 | (extract_nps_bitop_ins_ext): New function. | |
| 111 | (arc_operands): Add new operands. | |
| 112 | (arc_long_opcodes): New global array. | |
| 113 | (arc_num_long_opcodes): New global. | |
| 114 | * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes. | |
| 115 | ||
| 1fe0971e TS |
116 | 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
| 117 | ||
| 118 | * nds32-asm.h: Add extern "C". | |
| 119 | * sh-opc.h: Likewise. | |
| 120 | ||
| 315f180f GM |
121 | 2016-06-01 Graham Markall <graham.markall@embecosm.com> |
| 122 | ||
| 123 | * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and | |
| 124 | 0,b,limm to the rflt instruction. | |
| 125 | ||
| a2b5fccc TS |
126 | 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
| 127 | ||
| 128 | * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned | |
| 129 | constant. | |
| 130 | ||
| 0cbd0046 L |
131 | 2016-05-29 H.J. Lu <hongjiu.lu@intel.com> |
| 132 | ||
| 133 | PR gas/20145 | |
| 134 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS, | |
| 135 | CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS, | |
| 136 | CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS, | |
| 137 | CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS, | |
| 138 | CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS. | |
| 139 | * i386-init.h: Regenerated. | |
| 140 | ||
| 1848e567 L |
141 | 2016-05-27 H.J. Lu <hongjiu.lu@intel.com> |
| 142 | ||
| 143 | PR gas/20145 | |
| 144 | * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove | |
| 145 | CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from | |
| 146 | CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS. | |
| 147 | Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and | |
| 148 | CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from | |
| 149 | CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS, | |
| 150 | CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS. | |
| 151 | Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS, | |
| 152 | CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS, | |
| 153 | CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS, | |
| 154 | CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX | |
| 155 | for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable | |
| 156 | CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and | |
| 157 | CpuRegMask for AVX512. | |
| 158 | (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM | |
| 159 | and CpuRegMask. | |
| 160 | (set_bitfield_from_cpu_flag_init): New function. | |
| 161 | (set_bitfield): Remove const on f. Call | |
| 162 | set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS. | |
| 163 | * i386-opc.h (CpuRegMMX): New. | |
| 164 | (CpuRegXMM): Likewise. | |
| 165 | (CpuRegYMM): Likewise. | |
| 166 | (CpuRegZMM): Likewise. | |
| 167 | (CpuRegMask): Likewise. | |
| 168 | (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm | |
| 169 | and cpuregmask. | |
| 170 | * i386-init.h: Regenerated. | |
| 171 | * i386-tbl.h: Likewise. | |
| 172 | ||
| e92bae62 L |
173 | 2016-05-27 H.J. Lu <hongjiu.lu@intel.com> |
| 174 | ||
| 175 | PR gas/20154 | |
| 176 | * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64. | |
| 177 | (opcode_modifiers): Add AMD64 and Intel64. | |
| 178 | (main): Properly verify CpuMax. | |
| 179 | * i386-opc.h (CpuAMD64): Removed. | |
| 180 | (CpuIntel64): Likewise. | |
| 181 | (CpuMax): Set to CpuNo64. | |
| 182 | (i386_cpu_flags): Remove cpuamd64 and cpuintel64. | |
| 183 | (AMD64): New. | |
| 184 | (Intel64): Likewise. | |
| 185 | (i386_opcode_modifier): Add amd64 and intel64. | |
| 186 | (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 | |
| 187 | on call and jmp. | |
| 188 | * i386-init.h: Regenerated. | |
| 189 | * i386-tbl.h: Likewise. | |
| 190 | ||
| e89c5eaa L |
191 | 2016-05-27 H.J. Lu <hongjiu.lu@intel.com> |
| 192 | ||
| 193 | PR gas/20154 | |
| 194 | * i386-gen.c (main): Fail if CpuMax is incorrect. | |
| 195 | * i386-opc.h (CpuMax): Set to CpuIntel64. | |
| 196 | * i386-tbl.h: Regenerated. | |
| 197 | ||
| 77d66e7b NC |
198 | 2016-05-27 Nick Clifton <nickc@redhat.com> |
| 199 | ||
| 200 | PR target/20150 | |
| 201 | * msp430-dis.c (msp430dis_read_two_bytes): New function. | |
| 202 | (msp430dis_opcode_unsigned): New function. | |
| 203 | (msp430dis_opcode_signed): New function. | |
| 204 | (msp430_singleoperand): Use the new opcode reading functions. | |
| 205 | Only disassenmble bytes if they were successfully read. | |
| 206 | (msp430_doubleoperand): Likewise. | |
| 207 | (msp430_branchinstr): Likewise. | |
| 208 | (msp430x_callx_instr): Likewise. | |
| 209 | (print_insn_msp430): Check that it is safe to read bytes before | |
| 210 | attempting disassembly. Use the new opcode reading functions. | |
| 211 | ||
| 19dfcc89 PB |
212 | 2016-05-26 Peter Bergner <bergner@vnet.ibm.com> |
| 213 | ||
| 214 | * ppc-opc.c (CY): New define. Document it. | |
| 215 | (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics. | |
| 216 | ||
| f3ad7637 L |
217 | 2016-05-25 H.J. Lu <hongjiu.lu@intel.com> |
| 218 | ||
| 219 | * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS, | |
| 220 | CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS | |
| 221 | and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW, | |
| 222 | CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to | |
| 223 | CPU_ANY_AVX_FLAGS. | |
| 224 | * i386-init.h: Regenerated. | |
| 225 | ||
| f1360d58 L |
226 | 2016-05-25 H.J. Lu <hongjiu.lu@intel.com> |
| 227 | ||
| 228 | PR gas/20141 | |
| 229 | * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS, | |
| 230 | CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. | |
| 231 | * i386-init.h: Regenerated. | |
| 232 | ||
| 293f5f65 L |
233 | 2016-05-25 H.J. Lu <hongjiu.lu@intel.com> |
| 234 | ||
| 235 | * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to | |
| 236 | CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS. | |
| 237 | * i386-init.h: Regenerated. | |
| 238 | ||
| d9eca1df CZ |
239 | 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com> |
| 240 | ||
| 241 | * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type | |
| 242 | information. | |
| 243 | (print_insn_arc): Set insn_type information. | |
| 244 | * arc-opc.c (C_CC): Add F_CLASS_COND. | |
| 245 | * arc-tbl.h (bbit0, bbit1): Update subclass to COND. | |
| 246 | (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise. | |
| 247 | (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise. | |
| 248 | (breq, breq_s, brge, brhs, brlo, brlt): Likewise. | |
| 249 | (brne, brne_s, jeq_s, jne_s): Likewise. | |
| 250 | ||
| 87789e08 CZ |
251 | 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com> |
| 252 | ||
| 253 | * arc-tbl.h (neg): New instruction variant. | |
| 254 | ||
| c810e0b8 CZ |
255 | 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com> |
| 256 | ||
| 257 | * arc-dis.c (find_format, find_format, get_auxreg) | |
| 258 | (print_insn_arc): Changed. | |
| 259 | * arc-ext.h (INSERT_XOP): Likewise. | |
| 260 | ||
| 3d207518 TS |
261 | 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
| 262 | ||
| 263 | * tic54x-dis.c (sprint_mmr): Adjust. | |
| 264 | * tic54x-opc.c: Likewise. | |
| 265 | ||
| 514e58b7 AM |
266 | 2016-05-19 Alan Modra <amodra@gmail.com> |
| 267 | ||
| 268 | * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi. | |
| 269 | ||
| e43de63c AM |
270 | 2016-05-19 Alan Modra <amodra@gmail.com> |
| 271 | ||
| 272 | * ppc-opc.c: Formatting. | |
| 273 | (NSISIGNOPT): Define. | |
| 274 | (powerpc_opcodes <subis>): Use NSISIGNOPT. | |
| 275 | ||
| 1401d2fe MR |
276 | 2016-05-18 Maciej W. Rozycki <macro@imgtec.com> |
| 277 | ||
| 278 | * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand, | |
| 279 | replacing references to `micromips_ase' throughout. | |
| 280 | (_print_insn_mips): Don't use file-level microMIPS annotation to | |
| 281 | determine the disassembly mode with the symbol table. | |
| 282 | ||
| 1178da44 PB |
283 | 2016-05-13 Peter Bergner <bergner@vnet.ibm.com> |
| 284 | ||
| 285 | * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT. | |
| 286 | ||
| 8f4f9071 MF |
287 | 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com> |
| 288 | ||
| 289 | * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and | |
| 290 | mips64r6. | |
| 291 | * mips-opc.c (D34): New macro. | |
| 292 | (mips_builtin_opcodes): Define bposge32c for DSPr3. | |
| 293 | ||
| 8bc52696 AF |
294 | 2016-05-10 Alexander Fomin <alexander.fomin@intel.com> |
| 295 | ||
| 296 | * i386-dis.c (prefix_table): Add RDPID instruction. | |
| 297 | * i386-gen.c (cpu_flag_init): Add RDPID flag. | |
| 298 | (cpu_flags): Add RDPID bitfield. | |
| 299 | * i386-opc.h (enum): Add RDPID element. | |
| 300 | (i386_cpu_flags): Add RDPID field. | |
| 301 | * i386-opc.tbl: Add RDPID instruction. | |
| 302 | * i386-init.h: Regenerate. | |
| 303 | * i386-tbl.h: Regenerate. | |
| 304 | ||
| 39d911fc TP |
305 | 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 306 | ||
| 307 | * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get | |
| 308 | branch type of a symbol. | |
| 309 | (print_insn): Likewise. | |
| 310 | ||
| 16a1fa25 TP |
311 | 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 312 | ||
| 313 | * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M | |
| 314 | Mainline Security Extensions instructions. | |
| 315 | (thumb_opcodes): Add entries for narrow ARMv8-M Security | |
| 316 | Extensions instructions. | |
| 317 | (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions | |
| 318 | instructions. | |
| 319 | (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions | |
| 320 | special registers. | |
| 321 | ||
| d751b79e JM |
322 | 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 323 | ||
| 324 | * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai. | |
| 325 | ||
| 945e0f82 CZ |
326 | 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com> |
| 327 | ||
| 328 | * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP. | |
| 329 | (arcExtMap_genOpcode): Likewise. | |
| 330 | * arc-opc.c (arg_32bit_rc): Define new variable. | |
| 331 | (arg_32bit_u6): Likewise. | |
| 332 | (arg_32bit_limm): Likewise. | |
| 333 | ||
| 20f55f38 SN |
334 | 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| 335 | ||
| 336 | * aarch64-gen.c (VERIFIER): Define. | |
| 337 | * aarch64-opc.c (VERIFIER): Define. | |
| 338 | (verify_ldpsw): Use static linkage. | |
| 339 | * aarch64-opc.h (verify_ldpsw): Remove. | |
| 340 | * aarch64-tbl.h: Use VERIFIER for verifiers. | |
| 341 | ||
| 4bd13cde NC |
342 | 2016-04-28 Nick Clifton <nickc@redhat.com> |
| 343 | ||
| 344 | PR target/19722 | |
| 345 | * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present. | |
| 346 | * aarch64-opc.c (verify_ldpsw): New function. | |
| 347 | * aarch64-opc.h (verify_ldpsw): New prototype. | |
| 348 | * aarch64-tbl.h: Add initialiser for verifier field. | |
| 349 | (LDPSW): Set verifier to verify_ldpsw. | |
| 350 | ||
| c0f92bf9 L |
351 | 2016-04-23 H.J. Lu <hongjiu.lu@intel.com> |
| 352 | ||
| 353 | PR binutils/19983 | |
| 354 | PR binutils/19984 | |
| 355 | * i386-dis.c (print_insn): Return -1 if size of bfd_vma is | |
| 356 | smaller than address size. | |
| 357 | ||
| e6c7cdec TS |
358 | 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
| 359 | ||
| 360 | * alpha-dis.c: Regenerate. | |
| 361 | * crx-dis.c: Likewise. | |
| 362 | * disassemble.c: Likewise. | |
| 363 | * epiphany-opc.c: Likewise. | |
| 364 | * fr30-opc.c: Likewise. | |
| 365 | * frv-opc.c: Likewise. | |
| 366 | * ip2k-opc.c: Likewise. | |
| 367 | * iq2000-opc.c: Likewise. | |
| 368 | * lm32-opc.c: Likewise. | |
| 369 | * lm32-opinst.c: Likewise. | |
| 370 | * m32c-opc.c: Likewise. | |
| 371 | * m32r-opc.c: Likewise. | |
| 372 | * m32r-opinst.c: Likewise. | |
| 373 | * mep-opc.c: Likewise. | |
| 374 | * mt-opc.c: Likewise. | |
| 375 | * or1k-opc.c: Likewise. | |
| 376 | * or1k-opinst.c: Likewise. | |
| 377 | * tic80-opc.c: Likewise. | |
| 378 | * xc16x-opc.c: Likewise. | |
| 379 | * xstormy16-opc.c: Likewise. | |
| 380 | ||
| 537aefaf AB |
381 | 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com> |
| 382 | ||
| 383 | * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb, | |
| 384 | fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp, | |
| 385 | calcsd, and calcxd instructions. | |
| 386 | * arc-opc.c (insert_nps_bitop_size): Delete. | |
| 387 | (extract_nps_bitop_size): Delete. | |
| 388 | (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use. | |
| 389 | (extract_nps_qcmp_m3): Define. | |
| 390 | (extract_nps_qcmp_m2): Define. | |
| 391 | (extract_nps_qcmp_m1): Define. | |
| 392 | (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL. | |
| 393 | (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL | |
| 394 | (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE, | |
| 395 | NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST, | |
| 396 | NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and | |
| 397 | NPS_QCMP_M3. | |
| 398 | ||
| c8f785f2 AB |
399 | 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com> |
| 400 | ||
| 401 | * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions. | |
| 402 | ||
| 6fd8e7c2 L |
403 | 2016-04-15 H.J. Lu <hongjiu.lu@intel.com> |
| 404 | ||
| 405 | * Makefile.in: Regenerated with automake 1.11.6. | |
| 406 | * aclocal.m4: Likewise. | |
| 407 | ||
| 4b0c052e AB |
408 | 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com> |
| 409 | ||
| 410 | * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst | |
| 411 | instructions. | |
| 412 | * arc-opc.c (insert_nps_cmem_uimm16): New function. | |
| 413 | (extract_nps_cmem_uimm16): New function. | |
| 414 | (arc_operands): Add NPS_XLDST_UIMM16 operand. | |
| 415 | ||
| cb040366 AB |
416 | 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com> |
| 417 | ||
| 418 | * arc-dis.c (arc_insn_length): New function. | |
| 419 | (print_insn_arc): Use arc_insn_length, change insnLen to unsigned. | |
| 420 | (find_format): Change insnLen parameter to unsigned. | |
| 421 | ||
| accc0180 NC |
422 | 2016-04-13 Nick Clifton <nickc@redhat.com> |
| 423 | ||
| 424 | PR target/19937 | |
| 425 | * v850-opc.c (v850_opcodes): Correct masks for long versions of | |
| 426 | the LD.B and LD.BU instructions. | |
| 427 | ||
| f36e33da CZ |
428 | 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com> |
| 429 | ||
| 430 | * arc-dis.c (find_format): Check for extension flags. | |
| 431 | (print_flags): New function. | |
| 432 | (print_insn_arc): Update for .extCondCode, .extCoreRegister and | |
| 433 | .extAuxRegister. | |
| 434 | * arc-ext.c (arcExtMap_coreRegName): Use | |
| 435 | LAST_EXTENSION_CORE_REGISTER. | |
| 436 | (arcExtMap_coreReadWrite): Likewise. | |
| 437 | (dump_ARC_extmap): Update printing. | |
| 438 | * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag. | |
| 439 | (arc_aux_regs): Add cpu field. | |
| 440 | * arc-regs.h: Add cpu field, lower case name aux registers. | |
| 441 | ||
| 1c2e355e CZ |
442 | 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com> |
| 443 | ||
| 444 | * arc-tbl.h: Add rtsc, sleep with no arguments. | |
| 445 | ||
| b99747ae CZ |
446 | 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com> |
| 447 | ||
| 448 | * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf): | |
| 449 | Initialize. | |
| 450 | (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) | |
| 451 | (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) | |
| 452 | (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) | |
| 453 | (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) | |
| 454 | (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) | |
| 455 | (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) | |
| 456 | (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) | |
| 457 | (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) | |
| 458 | (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. | |
| 459 | (arc_opcode arc_opcodes): Null terminate the array. | |
| 460 | (arc_num_opcodes): Remove. | |
| 461 | * arc-ext.h (INSERT_XOP): Define. | |
| 462 | (extInstruction_t): Likewise. | |
| 463 | (arcExtMap_instName): Delete. | |
| 464 | (arcExtMap_insn): New function. | |
| 465 | (arcExtMap_genOpcode): Likewise. | |
| 466 | * arc-ext.c (ExtInstruction): Remove. | |
| 467 | (create_map): Zero initialize instruction fields. | |
| 468 | (arcExtMap_instName): Remove. | |
| 469 | (arcExtMap_insn): New function. | |
| 470 | (dump_ARC_extmap): More info while debuging. | |
| 471 | (arcExtMap_genOpcode): New function. | |
| 472 | * arc-dis.c (find_format): New function. | |
| 473 | (print_insn_arc): Use find_format. | |
| 474 | (arc_get_disassembler): Enable dump_ARC_extmap only when | |
| 475 | debugging. | |
| 476 | ||
| 92708cec MR |
477 | 2016-04-11 Maciej W. Rozycki <macro@imgtec.com> |
| 478 | ||
| 479 | * mips-dis.c (print_mips16_insn_arg): Mask unused extended | |
| 480 | instruction bits out. | |
| 481 | ||
| a42a4f84 AB |
482 | 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com> |
| 483 | ||
| 484 | * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions. | |
| 485 | * arc-opc.c (arc_flag_operands): Add new flags. | |
| 486 | (arc_flag_classes): Add new classes. | |
| 487 | ||
| 1328504b AB |
488 | 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com> |
| 489 | ||
| 490 | * arc-opc.c (arc_opcodes): Extend comment to discus table layout. | |
| 491 | ||
| 820f03ff AB |
492 | 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com> |
| 493 | ||
| 494 | * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0, | |
| 495 | encode1, rflt, crc16, and crc32 instructions. | |
| 496 | * arc-opc.c (arc_flag_operands): Add F_NPS_R. | |
| 497 | (arc_flag_classes): Add C_NPS_R. | |
| 498 | (insert_nps_bitop_size_2b): New function. | |
| 499 | (extract_nps_bitop_size_2b): Likewise. | |
| 500 | (insert_nps_bitop_uimm8): Likewise. | |
| 501 | (extract_nps_bitop_uimm8): Likewise. | |
| 502 | (arc_operands): Add new operand entries. | |
| 503 | ||
| 8ddf6b2a CZ |
504 | 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com> |
| 505 | ||
| b99747ae CZ |
506 | * arc-regs.h: Add a new subclass field. Add double assist |
| 507 | accumulator register values. | |
| 508 | * arc-tbl.h: Use DPA subclass to mark the double assist | |
| 509 | instructions. Use DPX/SPX subclas to mark the FPX instructions. | |
| 510 | * arc-opc.c (RSP): Define instead of SP. | |
| 511 | (arc_aux_regs): Add the subclass field. | |
| 8ddf6b2a | 512 | |
| 589a7d88 JW |
513 | 2016-04-05 Jiong Wang <jiong.wang@arm.com> |
| 514 | ||
| 515 | * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar). | |
| 516 | ||
| 0a191de9 | 517 | 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com> |
| 2cce10e7 AB |
518 | |
| 519 | * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and | |
| 520 | NPS_R_SRC1. | |
| 521 | ||
| 0a106562 AB |
522 | 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com> |
| 523 | ||
| 524 | * arc-nps400-tbl.h: Add a header comment, and fix some whitespace | |
| 525 | issues. No functional changes. | |
| 526 | ||
| bd05ac5f CZ |
527 | 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com> |
| 528 | ||
| b99747ae CZ |
529 | * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0) |
| 530 | (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1) | |
| 531 | (RTT): Remove duplicate. | |
| 532 | (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*) | |
| 533 | (PCT_CONFIG*): Remove. | |
| 534 | (D1L, D1H, D2H, D2L): Define. | |
| bd05ac5f | 535 | |
| 9885948f CZ |
536 | 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> |
| 537 | ||
| b99747ae | 538 | * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo. |
| 9885948f | 539 | |
| f2dd8838 CZ |
540 | 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com> |
| 541 | ||
| b99747ae CZ |
542 | * arc-tbl.h (invld07): Remove. |
| 543 | * arc-ext-tbl.h: New file. | |
| 544 | * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove. | |
| 545 | * arc-opc.c (arc_opcodes): Add ext-tbl include. | |
| f2dd8838 | 546 | |
| 0d2f91fe JK |
547 | 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com> |
| 548 | ||
| 549 | Fix -Wstack-usage warnings. | |
| 550 | * aarch64-dis.c (print_operands): Substitute size. | |
| 551 | * aarch64-opc.c (print_register_offset_address): Substitute tblen. | |
| 552 | ||
| a6b71f42 JM |
553 | 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 554 | ||
| 555 | * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order | |
| 556 | to get a proper diagnostic when an invalid ASR register is used. | |
| 557 | ||
| 9780e045 NC |
558 | 2016-03-22 Nick Clifton <nickc@redhat.com> |
| 559 | ||
| 560 | * configure: Regenerate. | |
| 561 | ||
| e23e8ebe AB |
562 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
| 563 | ||
| 564 | * arc-nps400-tbl.h: New file. | |
| 565 | * arc-opc.c: Add top level comment. | |
| 566 | (insert_nps_3bit_dst): New function. | |
| 567 | (extract_nps_3bit_dst): New function. | |
| 568 | (insert_nps_3bit_src2): New function. | |
| 569 | (extract_nps_3bit_src2): New function. | |
| 570 | (insert_nps_bitop_size): New function. | |
| 571 | (extract_nps_bitop_size): New function. | |
| 572 | (arc_flag_operands): Add nps400 entries. | |
| 573 | (arc_flag_classes): Add nps400 entries. | |
| 574 | (arc_operands): Add nps400 entries. | |
| 575 | (arc_opcodes): Add nps400 include. | |
| 576 | ||
| 1ae8ab47 AB |
577 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
| 578 | ||
| 579 | * arc-opc.c (arc_flag_classes): Convert all flag classes to use | |
| 580 | the new class enum values. | |
| 581 | ||
| 8699fc3e AB |
582 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
| 583 | ||
| 584 | * arc-dis.c (print_insn_arc): Handle nps400. | |
| 585 | ||
| 24740d83 AB |
586 | 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> |
| 587 | ||
| 588 | * arc-opc.c (BASE): Delete. | |
| 589 | ||
| 8678914f NC |
590 | 2016-03-18 Nick Clifton <nickc@redhat.com> |
| 591 | ||
| 592 | PR target/19721 | |
| 593 | * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand | |
| 594 | of MOV insn that aliases an ORR insn. | |
| 595 | ||
| cc933301 JW |
596 | 2016-03-16 Jiong Wang <jiong.wang@arm.com> |
| 597 | ||
| 598 | * arm-dis.c (neon_opcodes): Support new FP16 instructions. | |
| 599 | ||
| f86f5863 TS |
600 | 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> |
| 601 | ||
| 602 | * mcore-opc.h: Add const qualifiers. | |
| 603 | * microblaze-opc.h (struct op_code_struct): Likewise. | |
| 604 | * sh-opc.h: Likewise. | |
| 605 | * tic4x-dis.c (tic4x_print_indirect): Likewise. | |
| 606 | (tic4x_print_op): Likewise. | |
| 607 | ||
| 62de1c63 AM |
608 | 2016-03-02 Alan Modra <amodra@gmail.com> |
| 609 | ||
| d11698cd | 610 | * or1k-desc.h: Regenerate. |
| 62de1c63 | 611 | * fr30-ibld.c: Regenerate. |
| c697cf0b | 612 | * rl78-decode.c: Regenerate. |
| 62de1c63 | 613 | |
| 020efce5 NC |
614 | 2016-03-01 Nick Clifton <nickc@redhat.com> |
| 615 | ||
| 616 | PR target/19747 | |
| 617 | * rl78-dis.c (print_insn_rl78_common): Fix typo. | |
| 618 | ||
| b0c11777 RL |
619 | 2016-02-24 Renlin Li <renlin.li@arm.com> |
| 620 | ||
| 621 | * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries. | |
| 622 | (print_insn_coprocessor): Support fp16 instructions. | |
| 623 | ||
| 3e309328 RL |
624 | 2016-02-24 Renlin Li <renlin.li@arm.com> |
| 625 | ||
| 626 | * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm, | |
| 627 | vminnm, vrint(mpna). | |
| 628 | ||
| 8afc7bea RL |
629 | 2016-02-24 Renlin Li <renlin.li@arm.com> |
| 630 | ||
| 631 | * arm-dis.c (print_insn_coprocessor): Check co-processor number for | |
| 632 | cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2. | |
| 633 | ||
| 4fd7268a L |
634 | 2016-02-15 H.J. Lu <hongjiu.lu@intel.com> |
| 635 | ||
| 636 | * i386-dis.c (print_insn): Parenthesize expression to prevent | |
| 637 | truncated addresses. | |
| 638 | (OP_J): Likewise. | |
| 639 | ||
| 4670103e CZ |
640 | 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com> |
| 641 | Janek van Oirschot <jvanoirs@synopsys.com> | |
| 642 | ||
| b99747ae CZ |
643 | * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New |
| 644 | variable. | |
| 4670103e | 645 | |
| c1d9289f NC |
646 | 2016-02-04 Nick Clifton <nickc@redhat.com> |
| 647 | ||
| 648 | PR target/19561 | |
| 649 | * msp430-dis.c (print_insn_msp430): Add a special case for | |
| 650 | decoding an RRC instruction with the ZC bit set in the extension | |
| 651 | word. | |
| 652 | ||
| a143b004 AB |
653 | 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com> |
| 654 | ||
| 655 | * cgen-ibld.in (insert_normal): Rework calculation of shift. | |
| 656 | * epiphany-ibld.c: Regenerate. | |
| 657 | * fr30-ibld.c: Regenerate. | |
| 658 | * frv-ibld.c: Regenerate. | |
| 659 | * ip2k-ibld.c: Regenerate. | |
| 660 | * iq2000-ibld.c: Regenerate. | |
| 661 | * lm32-ibld.c: Regenerate. | |
| 662 | * m32c-ibld.c: Regenerate. | |
| 663 | * m32r-ibld.c: Regenerate. | |
| 664 | * mep-ibld.c: Regenerate. | |
| 665 | * mt-ibld.c: Regenerate. | |
| 666 | * or1k-ibld.c: Regenerate. | |
| 667 | * xc16x-ibld.c: Regenerate. | |
| 668 | * xstormy16-ibld.c: Regenerate. | |
| 669 | ||
| b89807c6 AB |
670 | 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com> |
| 671 | ||
| 672 | * epiphany-dis.c: Regenerated from latest cpu files. | |
| 673 | ||
| d8c823c8 MM |
674 | 2016-02-01 Michael McConville <mmcco@mykolab.com> |
| 675 | ||
| 676 | * cgen-dis.c (count_decodable_bits): Use unsigned value for mask | |
| 677 | test bit. | |
| 678 | ||
| 5bc5ae88 RL |
679 | 2016-01-25 Renlin Li <renlin.li@arm.com> |
| 680 | ||
| 681 | * arm-dis.c (mapping_symbol_for_insn): New function. | |
| 682 | (find_ifthen_state): Call mapping_symbol_for_insn(). | |
| 683 | ||
| 0bff6e2d MW |
684 | 2016-01-20 Matthew Wahab <matthew.wahab@arm.com> |
| 685 | ||
| 686 | * aarch64-opc.c (operand_general_constraint_met_p): Check validity | |
| 687 | of MSR UAO immediate operand. | |
| 688 | ||
| 100b4f2e MR |
689 | 2016-01-18 Maciej W. Rozycki <macro@imgtec.com> |
| 690 | ||
| 691 | * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS | |
| 692 | instruction support. | |
| 693 | ||
| 5c14705f AM |
694 | 2016-01-17 Alan Modra <amodra@gmail.com> |
| 695 | ||
| 696 | * configure: Regenerate. | |
| 697 | ||
| 4d82fe66 NC |
698 | 2016-01-14 Nick Clifton <nickc@redhat.com> |
| 699 | ||
| 700 | * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw | |
| 701 | instructions that can support stack pointer operations. | |
| 702 | * rl78-decode.c: Regenerate. | |
| 703 | * rl78-dis.c: Fix display of stack pointer in MOVW based | |
| 704 | instructions. | |
| 705 | ||
| 651657fa MW |
706 | 2016-01-14 Matthew Wahab <matthew.wahab@arm.com> |
| 707 | ||
| 708 | * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals | |
| 709 | testing for RAS support. Add checks for erxfr_el1, erxctlr_el1, | |
| 710 | erxtatus_el1 and erxaddr_el1. | |
| 711 | ||
| 105bde57 MW |
712 | 2016-01-12 Matthew Wahab <matthew.wahab@arm.com> |
| 713 | ||
| 714 | * arm-dis.c (arm_opcodes): Add "esb". | |
| 715 | (thumb_opcodes): Likewise. | |
| 716 | ||
| afa8d405 PB |
717 | 2016-01-11 Peter Bergner <bergner@vnet.ibm.com> |
| 718 | ||
| 719 | * ppc-opc.c <xscmpnedp>: Delete. | |
| 720 | <xvcmpnedp>: Likewise. | |
| 721 | <xvcmpnedp.>: Likewise. | |
| 722 | <xvcmpnesp>: Likewise. | |
| 723 | <xvcmpnesp.>: Likewise. | |
| 724 | ||
| 83c3256e AS |
725 | 2016-01-08 Andreas Schwab <schwab@linux-m68k.org> |
| 726 | ||
| 727 | PR gas/13050 | |
| 728 | * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in | |
| 729 | addition to ISA_A. | |
| 730 | ||
| 6f2750fe AM |
731 | 2016-01-01 Alan Modra <amodra@gmail.com> |
| 732 | ||
| 733 | Update year range in copyright notice of all files. | |
| 734 | ||
| 3499769a AM |
735 | For older changes see ChangeLog-2015 |
| 736 | \f | |
| 737 | Copyright (C) 2016 Free Software Foundation, Inc. | |
| 738 | ||
| 739 | Copying and distribution of this file, with or without modification, | |
| 740 | are permitted in any medium without royalty provided the copyright | |
| 741 | notice and this notice are preserved. | |
| 742 | ||
| 743 | Local Variables: | |
| 744 | mode: change-log | |
| 745 | left-margin: 8 | |
| 746 | fill-column: 74 | |
| 747 | version-control: never | |
| 748 | End: |