[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.

2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	(thumb32_opcodes): Likewise.
	(print_insn_thumb32): Handle 'S' control char.

2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>

	* lm32-desc.c: Regenerate.

2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-reg.tbl (riz): Add RegRex64.
	* i386-tbl.h: Regenerated.

2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	(aarch64_feature_crc): New static.
	(CRC): New macro.
	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.

2013-02-27  Alan Modra  <amodra@gmail.com>

	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	* rl78-decode.c: Regenerate.

2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>

	* rl78-decode.opc: Fix encoding of DIVWU insn.
	* rl78-decode.c: Regenerate.

2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/15159
	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.

	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	(cpu_flags): Add CpuSMAP.

	* i386-opc.h (CpuSMAP): New.
	(i386_cpu_flags): Add cpusmap.

	* i386-opc.tbl: Add clac and stac.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>

	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	which also makes the disassembler output be in little
	endian like it should be.

2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	fields to NULL.
	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.

2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	section disassembled.

2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c: Update strht pattern.

2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
	trunc.w.s macro for EE.

2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
            Andrew Jenner <andrew@codesourcery.com>

	Based on patches from Altera Corporation.

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	nios2-opc.c.
	* Makefile.in: Regenerated.
	* configure.in: Add case for bfd_nios2_arch.
	* configure: Regenerated.
	* disassemble.c (ARCH_nios2): Define.
	(disassembler): Add case for bfd_arch_nios2.
	* nios2-dis.c: New file.
	* nios2-opc.c: New file.

2013-02-04  Alan Modra  <amodra@gmail.com>

	* po/POTFILES.in: Regenerate.
	* rl78-decode.c: Regenerate.
	* rx-decode.c: Regenerate.

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

2013-01-24  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c: Add support for e3v5 architecture.
	* v850-opc.c: Likewise.

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): For
	AARCH64_MOD_LSL, move the range check on the shift amount before the
	alignment check; change to call set_sft_amount_out_of_range_error
	instead of set_imm_out_of_range_error.
	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	SIMD_IMM_SFT.

2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-01-15  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	values.
	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.

2013-01-14  Will Newton <will.newton@imgtec.com>

	* metag-dis.c (REG_WIDTH): Increase to 64.

2013-01-10  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	(SH6): Update.
	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.

2013-01-10  Will Newton <will.newton@imgtec.com>

	* Makefile.am: Add Meta.
	* configure.in: Add Meta.
	* disassemble.c: Add Meta support.
	* metag-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	(match_opcode): Rename to cr16_match_opcode.

2013-01-04  Juergen Urban <JuergenUrban@gmx.de>

	* mips-dis.c: Add names for CP0 registers of r5900.
	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	instructions sq and lq.
	Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and
	undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are
	not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the
	correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	will confuse less developers and compilers.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright year to 2013.

2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (match_opcode,make_instruction): Remove static
	declaration.
	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.

For older changes see ChangeLog-2012
\f
Copyright (C) 2013 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
dad60f8e SL	1	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	2
	3	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
	4
f5cb796a SL	5	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	6
	7	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
	8
21fde85c SL	9	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	10
	11	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
	12
dd5181d5 KT	13	2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	14
	15	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	16	(thumb32_opcodes): Likewise.
	17	(print_insn_thumb32): Handle 'S' control char.
	18
87a8d6cb NC	19	2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
	20
	21	* lm32-desc.c: Regenerate.
	22
99dce992 L	23	2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
	24
	25	* i386-reg.tbl (riz): Add RegRex64.
	26	* i386-tbl.h: Regenerated.
	27
e60bb1dd YZ	28	2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
	29
	30	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	31	(aarch64_feature_crc): New static.
	32	(CRC): New macro.
	33	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	34	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	35	* aarch64-asm-2.c: Re-generate.
	36	* aarch64-dis-2.c: Ditto.
	37	* aarch64-opc-2.c: Ditto.
	38
c7570fcd AM	39	2013-02-27 Alan Modra <amodra@gmail.com>
	40
	41	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	42	* rl78-decode.c: Regenerate.
	43
151fa98f NC	44	2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
	45
	46	* rl78-decode.opc: Fix encoding of DIVWU insn.
	47	* rl78-decode.c: Regenerate.
	48
5c111e37 L	49	2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
	50
	51	PR gas/15159
	52	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
	53
	54	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	55	(cpu_flags): Add CpuSMAP.
	56
	57	* i386-opc.h (CpuSMAP): New.
	58	(i386_cpu_flags): Add cpusmap.
	59
	60	* i386-opc.tbl: Add clac and stac.
	61
	62	* i386-init.h: Regenerated.
	63	* i386-tbl.h: Likewise.
	64
9d1df426 NC	65	2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
	66
	67	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	68	which also makes the disassembler output be in little
	69	endian like it should be.
	70
a1ccaec9 YZ	71	2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
	72
	73	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	74	fields to NULL.
	75	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
	76
ef068ef4	77	2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e MR	78
	79	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	80	section disassembled.
	81
6fe6ded9 RE	82	2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	83
	84	* arm-dis.c: Update strht pattern.
	85
0aa27725 RS	86	2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
	87
	88	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	89	single-float. Disable ll, lld, sc and scd for EE. Disable the
	90	trunc.w.s macro for EE.
	91
36591ba1 SL	92	2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
	93	Andrew Jenner <andrew@codesourcery.com>
	94
	95	Based on patches from Altera Corporation.
	96
	97	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	98	nios2-opc.c.
	99	* Makefile.in: Regenerated.
	100	* configure.in: Add case for bfd_nios2_arch.
	101	* configure: Regenerated.
	102	* disassemble.c (ARCH_nios2): Define.
	103	(disassembler): Add case for bfd_arch_nios2.
	104	* nios2-dis.c: New file.
	105	* nios2-opc.c: New file.
	106
545093a4 AM	107	2013-02-04 Alan Modra <amodra@gmail.com>
	108
	109	* po/POTFILES.in: Regenerate.
	110	* rl78-decode.c: Regenerate.
	111	* rx-decode.c: Regenerate.
	112
e30181a5 YZ	113	2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
	114
	115	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	116	ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
	117	* aarch64-asm.c (convert_xtl_to_shll): New function.
	118	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	119	calling convert_xtl_to_shll.
	120	* aarch64-dis.c (convert_shll_to_xtl): New function.
	121	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	122	calling convert_shll_to_xtl.
	123	* aarch64-gen.c: Update copyright year.
	124	* aarch64-asm-2.c: Re-generate.
	125	* aarch64-dis-2.c: Re-generate.
	126	* aarch64-opc-2.c: Re-generate.
	127
78c8d46c NC	128	2013-01-24 Nick Clifton <nickc@redhat.com>
	129
	130	* v850-dis.c: Add support for e3v5 architecture.
	131	* v850-opc.c: Likewise.
	132
f5555712 YZ	133	2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
	134
	135	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	136	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	137	* aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c	138	AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712 YZ	139	alignment check; change to call set_sft_amount_out_of_range_error
	140	instead of set_imm_out_of_range_error.
	141	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	142	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	143	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	144	SIMD_IMM_SFT.
	145
2f81ff92 L	146	2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
	147
	148	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
	149
	150	* i386-init.h: Regenerated.
	151	* i386-tbl.h: Likewise.
	152
dd42f060 NC	153	2013-01-15 Nick Clifton <nickc@redhat.com>
	154
	155	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	156	values.
	157	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
	158
a4533ed8 NC	159	2013-01-14 Will Newton <will.newton@imgtec.com>
	160
	161	* metag-dis.c (REG_WIDTH): Increase to 64.
	162
5817ffd1 PB	163	2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
	164
	165	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	166	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	167	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	168	(SH6): Update.
	169	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	170	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	171	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	172	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
	173
a3c62988 NC	174	2013-01-10 Will Newton <will.newton@imgtec.com>
	175
	176	* Makefile.am: Add Meta.
	177	* configure.in: Add Meta.
	178	* disassemble.c: Add Meta support.
	179	* metag-dis.c: New file.
	180	* Makefile.in: Regenerate.
	181	* configure: Regenerate.
	182
73335eae NC	183	2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
	184
	185	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	186	(match_opcode): Rename to cr16_match_opcode.
	187
e407c74b NC	188	2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
	189
	190	* mips-dis.c: Add names for CP0 registers of r5900.
	191	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	192	instructions sq and lq.
	193	Add support for MIPS r5900 CPU.
	194	Add support for 128 bit MMI (Multimedia Instructions).
	195	Add support for EE instructions (Emotion Engine).
	196	Disable unsupported floating point instructions (64 bit and
	197	undefined compare operations).
	198	Enable instructions of MIPS ISA IV which are supported by r5900.
	199	Disable 64 bit co processor instructions.
	200	Disable 64 bit multiplication and division instructions.
	201	Disable instructions for co-processor 2 and 3, because these are
	202	not supported (preparation for later VU0 support (Vector Unit)).
	203	Disable cvt.w.s because this behaves like trunc.w.s and the
	204	correct execution can't be ensured on r5900.
	205	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	206	will confuse less developers and compilers.
	207
a32c3ff8 NC	208	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
a32c3ff8 NC	209
fb098a1e YZ	210	* aarch64-opc.c (aarch64_print_operand): Change to print
	211	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	212	in comment.
	213	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	214	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	215	OP_MOV_IMM_WIDE.
	216
	217	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
	218
	219	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	220	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8	221
62658407 L	222	2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
	223
	224	* i386-gen.c (process_copyright): Update copyright year to 2013.
	225
bab4becb	226	2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7	227
bab4becb NC	228	* cr16-dis.c (match_opcode,make_instruction): Remove static
	229	declaration.
	230	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	231	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7	232
bab4becb	233	For older changes see ChangeLog-2012
252b5132	234	\f
bab4becb	235	Copyright (C) 2013 Free Software Foundation, Inc.
752937aa NC	236
	237	Copying and distribution of this file, with or without modification,
	238	are permitted in any medium without royalty provided the copyright
	239	notice and this notice are preserved.
	240
252b5132	241	Local Variables:
2f6d2f85 NC	242	mode: change-log
	243	left-margin: 8
	244	fill-column: 74
252b5132 RH	245	version-control: never
252b5132 RH	246	End: