Remove symbolp typedef
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
d777820b
IT
12018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2
3 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
4 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
5 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
6 (cpu_flags): Add CpuIBT, CpuSHSTK.
7 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
8 (i386_cpu_flags): Add cpuibt, cpushstk.
9 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
10 * i386-init.h: Regenerate.
11 * i386-tbl.h: Likewise.
12
f6efed01
NC
132018-01-16 Nick Clifton <nickc@redhat.com>
14
15 * po/pt_BR.po: Updated Brazilian Portugese translation.
16 * po/de.po: Updated German translation.
17
2721d702
JW
182018-01-15 Jim Wilson <jimw@sifive.com>
19
20 * riscv-opc.c (match_c_nop): New.
21 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
22
616dcb87
NC
232018-01-15 Nick Clifton <nickc@redhat.com>
24
25 * po/uk.po: Updated Ukranian translation.
26
3957a496
NC
272018-01-13 Nick Clifton <nickc@redhat.com>
28
29 * po/opcodes.pot: Regenerated.
30
769c7ea5
NC
312018-01-13 Nick Clifton <nickc@redhat.com>
32
33 * configure: Regenerate.
34
faf766e3
NC
352018-01-13 Nick Clifton <nickc@redhat.com>
36
37 2.30 branch created.
38
888a89da
IT
392018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
40
41 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
42 * i386-tbl.h: Regenerate.
43
cbda583a
JB
442018-01-10 Jan Beulich <jbeulich@suse.com>
45
46 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
47 * i386-tbl.h: Re-generate.
48
c9e92278
JB
492018-01-10 Jan Beulich <jbeulich@suse.com>
50
51 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
52 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
53 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
54 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
55 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
56 Disp8MemShift of AVX512VL forms.
57 * i386-tbl.h: Re-generate.
58
35fd2b2b
JW
592018-01-09 Jim Wilson <jimw@sifive.com>
60
61 * riscv-dis.c (maybe_print_address): If base_reg is zero,
62 then the hi_addr value is zero.
63
91d8b670
JG
642018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
65
66 * arm-dis.c (arm_opcodes): Add csdb.
67 (thumb32_opcodes): Add csdb.
68
be2e7d95
JG
692018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
70
71 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
72 * aarch64-asm-2.c: Regenerate.
73 * aarch64-dis-2.c: Regenerate.
74 * aarch64-opc-2.c: Regenerate.
75
704a705d
L
762018-01-08 H.J. Lu <hongjiu.lu@intel.com>
77
78 PR gas/22681
79 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
80 Remove AVX512 vmovd with 64-bit operands.
81 * i386-tbl.h: Regenerated.
82
35eeb78f
JW
832018-01-05 Jim Wilson <jimw@sifive.com>
84
85 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
86 jalr.
87
219d1afa
AM
882018-01-03 Alan Modra <amodra@gmail.com>
89
90 Update year range in copyright notice of all files.
91
1508bbf5
JB
922018-01-02 Jan Beulich <jbeulich@suse.com>
93
94 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
95 and OPERAND_TYPE_REGZMM entries.
96
1e563868 97For older changes see ChangeLog-2017
3499769a 98\f
1e563868 99Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM
100
101Copying and distribution of this file, with or without modification,
102are permitted in any medium without royalty provided the copyright
103notice and this notice are preserved.
104
105Local Variables:
106mode: change-log
107left-margin: 8
108fill-column: 74
109version-control: never
110End:
This page took 0.14342 seconds and 4 git commands to generate.