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gas/testsuite/
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a5dabbb0
L		 12008-05-30 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-opc.tbl: Add vmovd with 64bit operand.
4 * i386-tbl.h: Regenerated.
5
725a9891
MS		 62008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
7
8 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
9
cbc80391
L		 102008-05-22 H.J. Lu <hongjiu.lu@intel.com>
11
12 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
13 * i386-tbl.h: Regenerated.
14
116615c5
L		 152008-05-22 H.J. Lu <hongjiu.lu@intel.com>
16
17 PR gas/6517
18 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
19 into 32bit and 64bit. Remove Reg64|Qword and add
20 IgnoreSize|No_qSuf on 32bit version.
21 * i386-tbl.h: Regenerated.
22
d9479f2d
L		 232008-05-21 H.J. Lu <hongjiu.lu@intel.com>
24
25 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
26 * i386-tbl.h: Regenerated.
27
3ce6fddb
NC		 282008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
29
30 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
31
8944f3c2
AM		 322008-05-14 Alan Modra <amodra@bigpond.net.au>
33
34 * Makefile.am: Run "make dep-am".
35 * Makefile.in: Regenerate.
36
f1f8f695
L		 372008-05-02 H.J. Lu <hongjiu.lu@intel.com>
38
39 * i386-dis.c (MOVBE_Fixup): New.
40 (Mo): Likewise.
41 (PREFIX_0F3880): Likewise.
42 (PREFIX_0F3881): Likewise.
43 (PREFIX_0F38F0): Updated.
44 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
45 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
46 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
47
48 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
49 CPU_EPT_FLAGS.
50 (cpu_flags): Add CpuMovbe and CpuEPT.
51
52 * i386-opc.h (CpuMovbe): New.
53 (CpuEPT): Likewise.
54 (CpuLM): Updated.
55 (i386_cpu_flags): Add cpumovbe and cpuept.
56
57 * i386-opc.tbl: Add entries for movbe and EPT instructions.
58 * i386-init.h: Regenerated.
59 * i386-tbl.h: Likewise.
60
89aa3097
AN		 612008-04-29 Adam Nemet <anemet@caviumnetworks.com>
62
63 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
64 the two drem and the two dremu macros.
65
39c5c168
AN		 662008-04-28 Adam Nemet <anemet@caviumnetworks.com>
67
68 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
69 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
70 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
71 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
72
f04d18b7
DM		 732008-04-25 David S. Miller <davem@davemloft.net>
74
75 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
76 instead of %sys_tick_cmpr, as suggested in architecture manuals.
77
6194aaab
L		 782008-04-23 Paolo Bonzini <bonzini@gnu.org>
79
80 * aclocal.m4: Regenerate.
81 * configure: Regenerate.
82
1a6b486f
DM		 832008-04-23 David S. Miller <davem@davemloft.net>
84
85 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
86 extended values.
87 (prefetch_table): Add missing values.
88
81f8a913
L		 892008-04-22 H.J. Lu <hongjiu.lu@intel.com>
90
91 * i386-gen.c (opcode_modifiers): Add NoAVX.
92
93 * i386-opc.h (NoAVX): New.
94 (OldGcc): Updated.
95 (i386_opcode_modifier): Add noavx.
96
97 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
98 instructions which don't have AVX equivalent.
99 * i386-tbl.h: Regenerated.
100
dae39acc
L		 1012008-04-18 H.J. Lu <hongjiu.lu@intel.com>
102
103 * i386-dis.c (OP_VEX_FMA): New.
104 (OP_EX_VexImmW): Likewise.
105 (VexFMA): Likewise.
106 (Vex128FMA): Likewise.
107 (EXVexImmW): Likewise.
108 (get_vex_imm8): Likewise.
109 (OP_EX_VexReg): Likewise.
110 (vex_i4_done): Renamed to ...
111 (vex_w_done): This.
112 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
113 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
114 FMA instructions.
115 (print_insn): Updated.
116 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
117 (OP_REG_VexI4): Check invalid high registers.
118
ce886ab1
DR		 1192008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
120 Michael Meissner <michael.meissner@amd.com>
121
122 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
123 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 124
19a6653c
AM		 1252008-04-14 Edmar Wienskoski <edmar@freescale.com>
126
127 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
128 accept Power E500MC instructions.
129 (print_ppc_disassembler_options): Document -Me500mc.
130 * ppc-opc.c (DUIS, DUI, T): New.
131 (XRT, XRTRA): Likewise.
132 (E500MC): Likewise.
133 (powerpc_opcodes): Add new Power E500MC instructions.
134
112b7c50
AK		 1352008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
136
137 * s390-dis.c (init_disasm): Evaluate disassembler_options.
138 (print_s390_disassembler_options): New function.
139 * disassemble.c (disassembler_usage): Invoke
140 print_s390_disassembler_options.
141
7ff42648
AK		 1422008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
143
144 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
145 of local variables used for mnemonic parsing: prefix, suffix and
146 number.
147
45a5551e
AK		 1482008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
149
150 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
151 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
152 (s390_crb_extensions): New extensions table.
153 (insertExpandedMnemonic): Handle '$' tag.
154 * s390-opc.txt: Remove conditional jump variants which can now
155 be expanded automatically.
156 Replace '*' tag with '$' in the compare and branch instructions.
157
06c8514a
L		 1582008-04-07 H.J. Lu <hongjiu.lu@intel.com>
159
160 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
161 (PREFIX_VEX_3AXX): Likewis.
162
b122c285
L		 1632008-04-07 H.J. Lu <hongjiu.lu@intel.com>
164
165 * i386-opc.tbl: Remove 4 extra blank lines.
166
594ab6a3
L		 1672008-04-04 H.J. Lu <hongjiu.lu@intel.com>
168
169 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
170 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
171 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
172 * i386-opc.tbl: Likewise.
173
174 * i386-opc.h (CpuCLMUL): Renamed to ...
175 (CpuPCLMUL): This.
176 (CpuFMA): Updated.
177 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
178
179 * i386-init.h: Regenerated.
180
c0f3af97
L		 1812008-04-03 H.J. Lu <hongjiu.lu@intel.com>
182
183 * i386-dis.c (OP_E_register): New.
184 (OP_E_memory): Likewise.
185 (OP_VEX): Likewise.
186 (OP_EX_Vex): Likewise.
187 (OP_EX_VexW): Likewise.
188 (OP_XMM_Vex): Likewise.
189 (OP_XMM_VexW): Likewise.
190 (OP_REG_VexI4): Likewise.
191 (PCLMUL_Fixup): Likewise.
192 (VEXI4_Fixup): Likewise.
193 (VZERO_Fixup): Likewise.
194 (VCMP_Fixup): Likewise.
195 (VPERMIL2_Fixup): Likewise.
196 (rex_original): Likewise.
197 (rex_ignored): Likewise.
198 (Mxmm): Likewise.
199 (XMM): Likewise.
200 (EXxmm): Likewise.
201 (EXxmmq): Likewise.
202 (EXymmq): Likewise.
203 (Vex): Likewise.
204 (Vex128): Likewise.
205 (Vex256): Likewise.
206 (VexI4): Likewise.
207 (EXdVex): Likewise.
208 (EXqVex): Likewise.
209 (EXVexW): Likewise.
210 (EXdVexW): Likewise.
211 (EXqVexW): Likewise.
212 (XMVex): Likewise.
213 (XMVexW): Likewise.
214 (XMVexI4): Likewise.
215 (PCLMUL): Likewise.
216 (VZERO): Likewise.
217 (VCMP): Likewise.
218 (VPERMIL2): Likewise.
219 (xmm_mode): Likewise.
220 (xmmq_mode): Likewise.
221 (ymmq_mode): Likewise.
222 (vex_mode): Likewise.
223 (vex128_mode): Likewise.
224 (vex256_mode): Likewise.
225 (USE_VEX_C4_TABLE): Likewise.
226 (USE_VEX_C5_TABLE): Likewise.
227 (USE_VEX_LEN_TABLE): Likewise.
228 (VEX_C4_TABLE): Likewise.
229 (VEX_C5_TABLE): Likewise.
230 (VEX_LEN_TABLE): Likewise.
231 (REG_VEX_XX): Likewise.
232 (MOD_VEX_XXX): Likewise.
233 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
234 (PREFIX_0F3A44): Likewise.
235 (PREFIX_0F3ADF): Likewise.
236 (PREFIX_VEX_XXX): Likewise.
237 (VEX_OF): Likewise.
238 (VEX_OF38): Likewise.
239 (VEX_OF3A): Likewise.
240 (VEX_LEN_XXX): Likewise.
241 (vex): Likewise.
242 (need_vex): Likewise.
243 (need_vex_reg): Likewise.
244 (vex_i4_done): Likewise.
245 (vex_table): Likewise.
246 (vex_len_table): Likewise.
247 (OP_REG_VexI4): Likewise.
248 (vex_cmp_op): Likewise.
249 (pclmul_op): Likewise.
250 (vpermil2_op): Likewise.
251 (m_mode): Updated.
252 (es_reg): Likewise.
253 (PREFIX_0F38F0): Likewise.
254 (PREFIX_0F3A60): Likewise.
255 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
256 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
257 and PREFIX_VEX_XXX entries.
258 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
259 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
260 PREFIX_0F3ADF.
261 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
262 Add MOD_VEX_XXX entries.
263 (ckprefix): Initialize rex_original and rex_ignored. Store the
264 REX byte in rex_original.
265 (get_valid_dis386): Handle the implicit prefix in VEX prefix
266 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
267 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
268 calling get_valid_dis386. Use rex_original and rex_ignored when
269 printing out REX.
270 (putop): Handle "XY".
271 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
272 ymmq_mode.
273 (OP_E_extended): Updated to use OP_E_register and
274 OP_E_memory.
275 (OP_XMM): Handle VEX.
276 (OP_EX): Likewise.
277 (XMM_Fixup): Likewise.
278 (CMP_Fixup): Use ARRAY_SIZE.
279
280 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
281 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
282 (operand_type_init): Add OPERAND_TYPE_REGYMM and
283 OPERAND_TYPE_VEX_IMM4.
284 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
285 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
286 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
287 VexImmExt and SSE2AVX.
288 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
289
290 * i386-opc.h (CpuAVX): New.
291 (CpuAES): Likewise.
292 (CpuCLMUL): Likewise.
293 (CpuFMA): Likewise.
294 (Vex): Likewise.
295 (Vex256): Likewise.
296 (VexNDS): Likewise.
297 (VexNDD): Likewise.
298 (VexW0): Likewise.
299 (VexW1): Likewise.
300 (Vex0F): Likewise.
301 (Vex0F38): Likewise.
302 (Vex0F3A): Likewise.
303 (Vex3Sources): Likewise.
304 (VexImmExt): Likewise.
305 (SSE2AVX): Likewise.
306 (RegYMM): Likewise.
307 (Ymmword): Likewise.
308 (Vex_Imm4): Likewise.
309 (Implicit1stXmm0): Likewise.
310 (CpuXsave): Updated.
311 (CpuLM): Likewise.
312 (ByteOkIntel): Likewise.
313 (OldGcc): Likewise.
314 (Control): Likewise.
315 (Unspecified): Likewise.
316 (OTMax): Likewise.
317 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
318 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
319 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
320 vex3sources, veximmext and sse2avx.
321 (i386_operand_type): Add regymm, ymmword and vex_imm4.
322
323 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
324
325 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
326
327 * i386-init.h: Regenerated.
328 * i386-tbl.h: Likewise.
329
b21c9cb4
BS		 3302008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
331
332 From Robin Getz <robin.getz@analog.com>
333 * bfin-dis.c (bu32): Typedef.
334 (enum const_forms_t): Add c_uimm32 and c_huimm32.
335 (constant_formats[]): Add uimm32 and huimm16.
336 (fmtconst_val): New.
337 (uimm32): Define.
338 (huimm32): Define.
339 (imm16_val): Define.
340 (luimm16_val): Define.
341 (struct saved_state): Define.
342 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
343 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
344 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
345 (get_allreg): New.
346 (decode_LDIMMhalf_0): Print out the whole register value.
347
ee171c8f
BS		 348 From Jie Zhang <jie.zhang@analog.com>
349 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
350 multiply and multiply-accumulate to data register instruction.
351
086134ec
BS		 352 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
353 c_imm32, c_huimm32e): Define.
354 (constant_formats): Add flags for printing decimal, leading spaces, and
355 exact symbols.
356 (comment, parallel): Add global flags in all disassembly.
357 (fmtconst): Take advantage of new flags, and print default in hex.
358 (fmtconst_val): Likewise.
359 (decode_macfunc): Be consistant with spaces, tabs, comments,
360 capitalization in disassembly, fix minor coding style issues.
361 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
362 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
363 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
364 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
365 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
366 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
367 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
368 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
369 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
370 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
371 _print_insn_bfin, print_insn_bfin): Likewise.
372
58c85be7
RW		 3732008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
374
375 * aclocal.m4: Regenerate.
376 * configure: Likewise.
377 * Makefile.in: Likewise.
378
50e7d84b
AM		 3792008-03-13 Alan Modra <amodra@bigpond.net.au>
380
381 * Makefile.am: Run "make dep-am".
382 * Makefile.in: Regenerate.
383 * configure: Regenerate.
384
de866fcc
AM		 3852008-03-07 Alan Modra <amodra@bigpond.net.au>
386
387 * ppc-opc.c (powerpc_opcodes): Order and format.
388
28dbc079
L		 3892008-03-01 H.J. Lu <hongjiu.lu@intel.com>
390
391 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
392 * i386-tbl.h: Regenerated.
393
849830bd
L		 3942008-02-23 H.J. Lu <hongjiu.lu@intel.com>
395
396 * i386-opc.tbl: Disallow 16-bit near indirect branches for
397 x86-64.
398 * i386-tbl.h: Regenerated.
399
743ddb6b
JB		 4002008-02-21 Jan Beulich <jbeulich@novell.com>
401
402 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
403 and Fword for far indirect jmp. Allow Reg16 and Word for near
404 indirect jmp on x86-64. Disallow Fword for lcall.
405 * i386-tbl.h: Re-generate.
406
796d5313
NC		 4072008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
408
409 * cr16-opc.c (cr16_num_optab): Defined
410
65da13b5
L		 4112008-02-16 H.J. Lu <hongjiu.lu@intel.com>
412
413 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
414 * i386-init.h: Regenerated.
415
0e336180
NC		 4162008-02-14 Nick Clifton <nickc@redhat.com>
417
418 PR binutils/5524
419 * configure.in (SHARED_LIBADD): Select the correct host specific
420 file extension for shared libraries.
421 * configure: Regenerate.
422
b7240065
JB		 4232008-02-13 Jan Beulich <jbeulich@novell.com>
424
425 * i386-opc.h (RegFlat): New.
426 * i386-reg.tbl (flat): Add.
427 * i386-tbl.h: Re-generate.
428
34b772a6
JB		 4292008-02-13 Jan Beulich <jbeulich@novell.com>
430
431 * i386-dis.c (a_mode): New.
432 (cond_jump_mode): Adjust.
433 (Ma): Change to a_mode.
434 (intel_operand_size): Handle a_mode.
435 * i386-opc.tbl: Allow Dword and Qword for bound.
436 * i386-tbl.h: Re-generate.
437
a60de03c
JB		 4382008-02-13 Jan Beulich <jbeulich@novell.com>
439
440 * i386-gen.c (process_i386_registers): Process new fields.
441 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
442 unsigned char. Add dw2_regnum and Dw2Inval.
443 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
444 register names.
445 * i386-tbl.h: Re-generate.
446
f03fe4c1
L		 4472008-02-11 H.J. Lu <hongjiu.lu@intel.com>
448
4b6bc8eb 449 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 450 * i386-init.h: Updated.
451
475a2301
L		 4522008-02-11 H.J. Lu <hongjiu.lu@intel.com>
453
454 * i386-gen.c (cpu_flags): Add CpuXsave.
455
456 * i386-opc.h (CpuXsave): New.
4b6bc8eb 457 (CpuLM): Updated.
475a2301
L		 458 (i386_cpu_flags): Add cpuxsave.
459
460 * i386-dis.c (MOD_0FAE_REG_4): New.
461 (RM_0F01_REG_2): Likewise.
462 (MOD_0FAE_REG_5): Updated.
463 (RM_0F01_REG_3): Likewise.
464 (reg_table): Use MOD_0FAE_REG_4.
465 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
466 for xrstor.
467 (rm_table): Add RM_0F01_REG_2.
468
469 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
470 * i386-init.h: Regenerated.
471 * i386-tbl.h: Likewise.
472
595785c6 4732008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 474
595785c6
JB		 475 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
476 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
477 * i386-tbl.h: Re-generate.
478
bb8541b9
L		 4792008-02-04 H.J. Lu <hongjiu.lu@intel.com>
480
481 PR 5715
482 * configure: Regenerated.
483
57b592a3
AN		 4842008-02-04 Adam Nemet <anemet@caviumnetworks.com>
485
486 * mips-dis.c: Update copyright.
487 (mips_arch_choices): Add Octeon.
488 * mips-opc.c: Update copyright.
489 (IOCT): New macro.
490 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
491
930bb4cf
AM		 4922008-01-29 Alan Modra <amodra@bigpond.net.au>
493
494 * ppc-opc.c: Support optional L form mtmsr.
495
82c18208
L		 4962008-01-24 H.J. Lu <hongjiu.lu@intel.com>
497
498 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
499
599121aa
L		 5002008-01-23 H.J. Lu <hongjiu.lu@intel.com>
501
502 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
503 * i386-init.h: Regenerated.
504
80098f51
TG		 5052008-01-23 Tristan Gingold <gingold@adacore.com>
506
507 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
508 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
509
115c7c25
L		 5102008-01-22 H.J. Lu <hongjiu.lu@intel.com>
511
512 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
513 (cpu_flags): Likewise.
514
515 * i386-opc.h (CpuMMX2): Removed.
516 (CpuSSE): Updated.
517
518 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
519 * i386-init.h: Regenerated.
520 * i386-tbl.h: Likewise.
521
6305a203
L		 5222008-01-22 H.J. Lu <hongjiu.lu@intel.com>
523
524 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
525 CPU_SMX_FLAGS.
526 * i386-init.h: Regenerated.
527
fd07a1c8
L		 5282008-01-15 H.J. Lu <hongjiu.lu@intel.com>
529
530 * i386-opc.tbl: Use Qword on movddup.
531 * i386-tbl.h: Regenerated.
532
321fd21e
L		 5332008-01-15 H.J. Lu <hongjiu.lu@intel.com>
534
535 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
536 * i386-tbl.h: Regenerated.
537
4ee52178
L		 5382008-01-15 H.J. Lu <hongjiu.lu@intel.com>
539
540 * i386-dis.c (Mx): New.
541 (PREFIX_0FC3): Likewise.
542 (PREFIX_0FC7_REG_6): Updated.
543 (dis386_twobyte): Use PREFIX_0FC3.
544 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
545 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
546 movntss.
547
5c07affc
L		 5482008-01-14 H.J. Lu <hongjiu.lu@intel.com>
549
550 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
551 (operand_types): Add Mem.
552
553 * i386-opc.h (IntelSyntax): New.
554 * i386-opc.h (Mem): New.
555 (Byte): Updated.
556 (Opcode_Modifier_Max): Updated.
557 (i386_opcode_modifier): Add intelsyntax.
558 (i386_operand_type): Add mem.
559
560 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
561 instructions.
562
563 * i386-reg.tbl: Add size for accumulator.
564
565 * i386-init.h: Regenerated.
566 * i386-tbl.h: Likewise.
567
0d6a2f58
L		 5682008-01-13 H.J. Lu <hongjiu.lu@intel.com>
569
570 * i386-opc.h (Byte): Fix a typo.
571
7d5e4556
L		 5722008-01-12 H.J. Lu <hongjiu.lu@intel.com>
573
574 PR gas/5534
575 * i386-gen.c (operand_type_init): Add Dword to
576 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
577 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
578 Qword and Xmmword.
579 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
580 Xmmword, Unspecified and Anysize.
581 (set_bitfield): Make Mmword an alias of Qword. Make Oword
582 an alias of Xmmword.
583
584 * i386-opc.h (CheckSize): Removed.
585 (Byte): Updated.
586 (Word): Likewise.
587 (Dword): Likewise.
588 (Qword): Likewise.
589 (Xmmword): Likewise.
590 (FWait): Updated.
591 (OTMax): Likewise.
592 (i386_opcode_modifier): Remove checksize, byte, word, dword,
593 qword and xmmword.
594 (Fword): New.
595 (TBYTE): Likewise.
596 (Unspecified): Likewise.
597 (Anysize): Likewise.
598 (i386_operand_type): Add byte, word, dword, fword, qword,
599 tbyte xmmword, unspecified and anysize.
600
601 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
602 Tbyte, Xmmword, Unspecified and Anysize.
603
604 * i386-reg.tbl: Add size for accumulator.
605
606 * i386-init.h: Regenerated.
607 * i386-tbl.h: Likewise.
608
b5b1fc4f
L		 6092008-01-10 H.J. Lu <hongjiu.lu@intel.com>
610
611 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
612 (REG_0F18): Updated.
613 (reg_table): Updated.
614 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
615 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
616
50e8458f
L		 6172008-01-08 H.J. Lu <hongjiu.lu@intel.com>
618
619 * i386-gen.c (set_bitfield): Use fail () on error.
620
3d4d5afa
L		 6212008-01-08 H.J. Lu <hongjiu.lu@intel.com>
622
623 * i386-gen.c (lineno): New.
624 (filename): Likewise.
625 (set_bitfield): Report filename and line numer on error.
626 (process_i386_opcodes): Set filename and update lineno.
627 (process_i386_registers): Likewise.
628
e1d4d893
L		 6292008-01-05 H.J. Lu <hongjiu.lu@intel.com>
630
631 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
632 ATTSyntax.
633
634 * i386-opc.h (IntelMnemonic): Renamed to ..
635 (ATTSyntax): This
636 (Opcode_Modifier_Max): Updated.
637 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
638 and intelsyntax.
639
8944f3c2 640 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 641 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
642 * i386-tbl.h: Regenerated.
643
6f143e4d
L		 6442008-01-04 H.J. Lu <hongjiu.lu@intel.com>
645
646 * i386-gen.c: Update copyright to 2008.
647 * i386-opc.h: Likewise.
648 * i386-opc.tbl: Likewise.
649
650 * i386-init.h: Regenerated.
651 * i386-tbl.h: Likewise.
652
c6add537
L		 6532008-01-04 H.J. Lu <hongjiu.lu@intel.com>
654
655 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
656 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
657 * i386-tbl.h: Regenerated.
658
3629bb00
L		 6592008-01-03 H.J. Lu <hongjiu.lu@intel.com>
660
661 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
662 CpuSSE4_2_Or_ABM.
663 (cpu_flags): Likewise.
664
665 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
666 (CpuSSE4_2_Or_ABM): Likewise.
667 (CpuLM): Updated.
668 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
669
670 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
671 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
672 and CpuPadLock, respectively.
673 * i386-init.h: Regenerated.
674 * i386-tbl.h: Likewise.
675
24995bd6
L		 6762008-01-03 H.J. Lu <hongjiu.lu@intel.com>
677
678 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
679
680 * i386-opc.h (No_xSuf): Removed.
681 (CheckSize): Updated.
682
683 * i386-tbl.h: Regenerated.
684
e0329a22
L		 6852008-01-02 H.J. Lu <hongjiu.lu@intel.com>
686
687 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
688 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
689 CPU_SSE5_FLAGS.
690 (cpu_flags): Add CpuSSE4_2_Or_ABM.
691
692 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
693 (CpuLM): Updated.
694 (i386_cpu_flags): Add cpusse4_2_or_abm.
695
696 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
697 CpuABM|CpuSSE4_2 on popcnt.
698 * i386-init.h: Regenerated.
699 * i386-tbl.h: Likewise.
700
f2a9c676
L		 7012008-01-02 H.J. Lu <hongjiu.lu@intel.com>
702
703 * i386-opc.h: Update comments.
704
d978b5be
L		 7052008-01-02 H.J. Lu <hongjiu.lu@intel.com>
706
707 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
708 * i386-opc.h: Likewise.
709 * i386-opc.tbl: Likewise.
710
582d5edd
L		 7112008-01-02 H.J. Lu <hongjiu.lu@intel.com>
712
713 PR gas/5534
714 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
715 Byte, Word, Dword, QWord and Xmmword.
716
717 * i386-opc.h (No_xSuf): New.
718 (CheckSize): Likewise.
719 (Byte): Likewise.
720 (Word): Likewise.
721 (Dword): Likewise.
722 (QWord): Likewise.
723 (Xmmword): Likewise.
724 (FWait): Updated.
725 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
726 Dword, QWord and Xmmword.
727
728 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
729 used.
730 * i386-tbl.h: Regenerated.
731
3fe15143
MK		 7322008-01-02 Mark Kettenis <kettenis@gnu.org>
733
734 * m88k-dis.c (instructions): Fix fcvt.* instructions.
735 From Miod Vallat.
736
6c7ac64e 737For older changes see ChangeLog-2007
252b5132
RH		 738\f
739Local Variables:
2f6d2f85
NC		 740mode: change-log
741left-margin: 8
742fill-column: 74
252b5132
RH		 743version-control: never
744End:
GDB Binutils - Deliverables
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