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[MIPS/GAS] Add Loongson EXT2 Instructions support.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a693765e
CX		 12018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
2
3 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
4 option.
5 (print_mips_disassembler_options): Document -M loongson-ext.
6 * mips-opc.c (LEXT2): New macro.
7 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
8
bdc6c06e
CX		 92018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
10
11 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
12 descriptors.
13 (parse_mips_ase_option): Handle -M loongson-ext option.
14 (print_mips_disassembler_options): Document -M loongson-ext.
15 * mips-opc.c (IL3A): Delete.
16 * mips-opc.c (LEXT): New macro.
17 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
18 instructions.
19
716c08de
CX		 202018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
21
22 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
23 descriptors.
24 (parse_mips_ase_option): Handle -M loongson-cam option.
25 (print_mips_disassembler_options): Document -M loongson-cam.
26 * mips-opc.c (LCAM): New macro.
27 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
28 instructions.
29
9cf7e568
AM		 302018-08-21 Alan Modra <amodra@gmail.com>
31
32 * ppc-dis.c (operand_value_powerpc): Init "invalid".
33 (skip_optional_operands): Count optional operands, and update
34 ppc_optional_operand_value call.
35 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
36 (extract_vlensi): Likewise.
37 (extract_fxm): Return default value for missing optional operand.
38 (extract_ls, extract_raq, extract_tbr): Likewise.
39 (insert_sxl, extract_sxl): New functions.
40 (insert_esync, extract_esync): Remove Power9 handling and simplify.
41 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
42 flag and extra entry.
43 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
44 extract_sxl.
45
d203b41a 462018-08-20 Alan Modra <amodra@gmail.com>
f4107842 47
d203b41a 48 * sh-opc.h (MASK): Simplify.
f4107842 49
08a8fe2f 502018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 51
d203b41a
AM		 52 * s12z-dis.c (bm_decode): Deal with cases where the mode is
53 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 54 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 55
08a8fe2f 562018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 57
58 * s12z.h: Delete.
7ba3ba91 59
1bc60e56
L		 602018-08-14 H.J. Lu <hongjiu.lu@intel.com>
61
62 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
63 address with the addr32 prefix and without base nor index
64 registers.
65
d871f3f4
L		 662018-08-11 H.J. Lu <hongjiu.lu@intel.com>
67
68 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
69 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
70 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
71 (cpu_flags): Add CpuCMOV and CpuFXSR.
72 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
73 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
74 * i386-init.h: Regenerated.
75 * i386-tbl.h: Likewise.
76
b6523c37 772018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
78
79 * arc-regs.h: Update auxiliary registers.
80
e968fc9b
JB		 812018-08-06 Jan Beulich <jbeulich@suse.com>
82
83 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
84 (RegIP, RegIZ): Define.
85 * i386-reg.tbl: Adjust comments.
86 (rip): Use Qword instead of BaseIndex. Use RegIP.
87 (eip): Use Dword instead of BaseIndex. Use RegIP.
88 (riz): Add Qword. Use RegIZ.
89 (eiz): Add Dword. Use RegIZ.
90 * i386-tbl.h: Re-generate.
91
dbf8be89
JB		 922018-08-03 Jan Beulich <jbeulich@suse.com>
93
94 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
95 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
96 vpmovzxdq, vpmovzxwd): Remove NoRex64.
97 * i386-tbl.h: Re-generate.
98
c48dadc9
JB		 992018-08-03 Jan Beulich <jbeulich@suse.com>
100
101 * i386-gen.c (operand_types): Remove Mem field.
102 * i386-opc.h (union i386_operand_type): Remove mem field.
103 * i386-init.h, i386-tbl.h: Re-generate.
104
cb86a42a
AM		 1052018-08-01 Alan Modra <amodra@gmail.com>
106
107 * po/POTFILES.in: Regenerate.
108
07cc0450
NC		 1092018-07-31 Nick Clifton <nickc@redhat.com>
110
111 * po/sv.po: Updated Swedish translation.
112
1424ad86
JB		 1132018-07-31 Jan Beulich <jbeulich@suse.com>
114
115 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
116 * i386-init.h, i386-tbl.h: Re-generate.
117
ae2387fe
JB		 1182018-07-31 Jan Beulich <jbeulich@suse.com>
119
120 * i386-opc.h (ZEROING_MASKING) Rename to ...
121 (DYNAMIC_MASKING): ... this. Adjust comment.
122 * i386-opc.tbl (MaskingMorZ): Define.
123 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
124 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
125 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
126 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
127 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
128 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
129 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
130 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
131 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
132
6ff00b5e
JB		 1332018-07-31 Jan Beulich <jbeulich@suse.com>
134
135 * i386-opc.tbl: Use element rather than vector size for AVX512*
136 scatter/gather insns.
137 * i386-tbl.h: Re-generate.
138
e951d5ca
JB		 1392018-07-31 Jan Beulich <jbeulich@suse.com>
140
141 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
142 (cpu_flags): Drop CpuVREX.
143 * i386-opc.h (CpuVREX): Delete.
144 (union i386_cpu_flags): Remove cpuvrex.
145 * i386-init.h, i386-tbl.h: Re-generate.
146
eb41b248
JW		 1472018-07-30 Jim Wilson <jimw@sifive.com>
148
149 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
150 fields.
151 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
152
b8891f8d
AJ		 1532018-07-30 Andrew Jenner <andrew@codesourcery.com>
154
155 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
156 * Makefile.in: Regenerated.
157 * configure.ac: Add C-SKY.
158 * configure: Regenerated.
159 * csky-dis.c: New file.
160 * csky-opc.h: New file.
161 * disassemble.c (ARCH_csky): Define.
162 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
163 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
164
16065af1
AM		 1652018-07-27 Alan Modra <amodra@gmail.com>
166
167 * ppc-opc.c (insert_sprbat): Correct function parameter and
168 return type.
169 (extract_sprbat): Likewise, variable too.
170
fa758a70
AC		 1712018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
172 Alan Modra <amodra@gmail.com>
173
174 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
175 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
176 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
177 support disjointed BAT.
178 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
179 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
180 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
181
4a1b91ea
L		 1822018-07-25 H.J. Lu <hongjiu.lu@intel.com>
183 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
184
185 * i386-gen.c (adjust_broadcast_modifier): New function.
186 (process_i386_opcode_modifier): Add an argument for operands.
187 Adjust the Broadcast value based on operands.
188 (output_i386_opcode): Pass operand_types to
189 process_i386_opcode_modifier.
190 (process_i386_opcodes): Pass NULL as operands to
191 process_i386_opcode_modifier.
192 * i386-opc.h (BYTE_BROADCAST): New.
193 (WORD_BROADCAST): Likewise.
194 (DWORD_BROADCAST): Likewise.
195 (QWORD_BROADCAST): Likewise.
196 (i386_opcode_modifier): Expand broadcast to 3 bits.
197 * i386-tbl.h: Regenerated.
198
67ce483b
AM		 1992018-07-24 Alan Modra <amodra@gmail.com>
200
201 PR 23430
202 * or1k-desc.h: Regenerate.
203
4174bfff
JB		 2042018-07-24 Jan Beulich <jbeulich@suse.com>
205
206 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
207 vcvtusi2ss, and vcvtusi2sd.
208 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
209 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
210 * i386-tbl.h: Re-generate.
211
04e65276
CZ		 2122018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
213
214 * arc-opc.c (extract_w6): Fix extending the sign.
215
47e6f81c
CZ		 2162018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
217
218 * arc-tbl.h (vewt): Allow it for ARC EM family.
219
bb71536f
AM		 2202018-07-23 Alan Modra <amodra@gmail.com>
221
222 PR 23419
223 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
224 opcode variants for mtspr/mfspr encodings.
225
8095d2f7
CX		 2262018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
227 Maciej W. Rozycki <macro@mips.com>
228
229 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
230 loongson3a descriptors.
231 (parse_mips_ase_option): Handle -M loongson-mmi option.
232 (print_mips_disassembler_options): Document -M loongson-mmi.
233 * mips-opc.c (LMMI): New macro.
234 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
235 instructions.
236
5f32791e
JB		 2372018-07-19 Jan Beulich <jbeulich@suse.com>
238
239 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
240 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
241 IgnoreSize and [XYZ]MMword where applicable.
242 * i386-tbl.h: Re-generate.
243
625cbd7a
JB		 2442018-07-19 Jan Beulich <jbeulich@suse.com>
245
246 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
247 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
248 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
249 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
250 * i386-tbl.h: Re-generate.
251
86b15c32
JB		 2522018-07-19 Jan Beulich <jbeulich@suse.com>
253
254 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
255 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
256 VPCLMULQDQ templates into their respective AVX512VL counterparts
257 where possible, using Disp8ShiftVL and CheckRegSize instead of
258 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
259 * i386-tbl.h: Re-generate.
260
cf769ed5
JB		 2612018-07-19 Jan Beulich <jbeulich@suse.com>
262
263 * i386-opc.tbl: Fold AVX512DQ templates into their respective
264 AVX512VL counterparts where possible, using Disp8ShiftVL and
265 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
266 IgnoreSize) as appropriate.
267 * i386-tbl.h: Re-generate.
268
8282b7ad
JB		 2692018-07-19 Jan Beulich <jbeulich@suse.com>
270
271 * i386-opc.tbl: Fold AVX512BW templates into their respective
272 AVX512VL counterparts where possible, using Disp8ShiftVL and
273 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
274 IgnoreSize) as appropriate.
275 * i386-tbl.h: Re-generate.
276
755908cc
JB		 2772018-07-19 Jan Beulich <jbeulich@suse.com>
278
279 * i386-opc.tbl: Fold AVX512CD templates into their respective
280 AVX512VL counterparts where possible, using Disp8ShiftVL and
281 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
282 IgnoreSize) as appropriate.
283 * i386-tbl.h: Re-generate.
284
7091c612
JB		 2852018-07-19 Jan Beulich <jbeulich@suse.com>
286
287 * i386-opc.h (DISP8_SHIFT_VL): New.
288 * i386-opc.tbl (Disp8ShiftVL): Define.
289 (various): Fold AVX512VL templates into their respective
290 AVX512F counterparts where possible, using Disp8ShiftVL and
291 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
292 IgnoreSize) as appropriate.
293 * i386-tbl.h: Re-generate.
294
c30be56e
JB		 2952018-07-19 Jan Beulich <jbeulich@suse.com>
296
297 * Makefile.am: Change dependencies and rule for
298 $(srcdir)/i386-init.h.
299 * Makefile.in: Re-generate.
300 * i386-gen.c (process_i386_opcodes): New local variable
301 "marker". Drop opening of input file. Recognize marker and line
302 number directives.
303 * i386-opc.tbl (OPCODE_I386_H): Define.
304 (i386-opc.h): Include it.
305 (None): Undefine.
306
11a322db
L		 3072018-07-18 H.J. Lu <hongjiu.lu@intel.com>
308
309 PR gas/23418
310 * i386-opc.h (Byte): Update comments.
311 (Word): Likewise.
312 (Dword): Likewise.
313 (Fword): Likewise.
314 (Qword): Likewise.
315 (Tbyte): Likewise.
316 (Xmmword): Likewise.
317 (Ymmword): Likewise.
318 (Zmmword): Likewise.
319 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
320 vcvttps2uqq.
321 * i386-tbl.h: Regenerated.
322
cde3679e
NC		 3232018-07-12 Sudakshina Das <sudi.das@arm.com>
324
325 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
326 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
327 * aarch64-asm-2.c: Regenerate.
328 * aarch64-dis-2.c: Regenerate.
329 * aarch64-opc-2.c: Regenerate.
330
45a28947
TC		 3312018-07-12 Tamar Christina <tamar.christina@arm.com>
332
333 PR binutils/23192
334 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
335 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
336 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
337 sqdmulh, sqrdmulh): Use Em16.
338
c597cc3d
SD		 3392018-07-11 Sudakshina Das <sudi.das@arm.com>
340
341 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
342 csdb together with them.
343 (thumb32_opcodes): Likewise.
344
a79eaed6
JB		 3452018-07-11 Jan Beulich <jbeulich@suse.com>
346
347 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
348 requiring 32-bit registers as operands 2 and 3. Improve
349 comments.
350 (mwait, mwaitx): Fold templates. Improve comments.
351 OPERAND_TYPE_INOUTPORTREG.
352 * i386-tbl.h: Re-generate.
353
2fb5be8d
JB		 3542018-07-11 Jan Beulich <jbeulich@suse.com>
355
356 * i386-gen.c (operand_type_init): Remove
357 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
358 OPERAND_TYPE_INOUTPORTREG.
359 * i386-init.h: Re-generate.
360
7f5cad30
JB		 3612018-07-11 Jan Beulich <jbeulich@suse.com>
362
363 * i386-opc.tbl (wrssd, wrussd): Add Dword.
364 (wrssq, wrussq): Add Qword.
365 * i386-tbl.h: Re-generate.
366
f0a85b07
JB		 3672018-07-11 Jan Beulich <jbeulich@suse.com>
368
369 * i386-opc.h: Rename OTMax to OTNum.
370 (OTNumOfUints): Adjust calculation.
371 (OTUnused): Directly alias to OTNum.
372
9dcb0ba4
MR		 3732018-07-09 Maciej W. Rozycki <macro@mips.com>
374
375 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
376 `reg_xys'.
377 (lea_reg_xys): Likewise.
378 (print_insn_loop_primitive): Rename `reg' local variable to
379 `reg_dxy'.
380
f311ba7e
TC		 3812018-07-06 Tamar Christina <tamar.christina@arm.com>
382
383 PR binutils/23242
384 * aarch64-tbl.h (ldarh): Fix disassembly mask.
385
cba05feb
TC		 3862018-07-06 Tamar Christina <tamar.christina@arm.com>
387
388 PR binutils/23369
389 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
390 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
391
471b9d15
MR		 3922018-07-02 Maciej W. Rozycki <macro@mips.com>
393
394 PR tdep/8282
395 * mips-dis.c (mips_option_arg_t): New enumeration.
396 (mips_options): New variable.
397 (disassembler_options_mips): New function.
398 (print_mips_disassembler_options): Reimplement in terms of
399 `disassembler_options_mips'.
400 * arm-dis.c (disassembler_options_arm): Adapt to using the
401 `disasm_options_and_args_t' structure.
402 * ppc-dis.c (disassembler_options_powerpc): Likewise.
403 * s390-dis.c (disassembler_options_s390): Likewise.
404
c0c468d5
TP		 4052018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
406
407 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
408 expected result.
409 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
410 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
411 * testsuite/ld-arm/tls-longplt.d: Likewise.
412
369c9167
TC		 4132018-06-29 Tamar Christina <tamar.christina@arm.com>
414
415 PR binutils/23192
416 * aarch64-asm-2.c: Regenerate.
417 * aarch64-dis-2.c: Likewise.
418 * aarch64-opc-2.c: Likewise.
419 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
420 * aarch64-opc.c (operand_general_constraint_met_p,
421 aarch64_print_operand): Likewise.
422 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
423 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
424 fmlal2, fmlsl2.
425 (AARCH64_OPERANDS): Add Em2.
426
30aa1306
NC		 4272018-06-26 Nick Clifton <nickc@redhat.com>
428
429 * po/uk.po: Updated Ukranian translation.
430 * po/de.po: Updated German translation.
431 * po/pt_BR.po: Updated Brazilian Portuguese translation.
432
eca4b721
NC		 4332018-06-26 Nick Clifton <nickc@redhat.com>
434
435 * nfp-dis.c: Fix spelling mistake.
436
71300e2c
NC		 4372018-06-24 Nick Clifton <nickc@redhat.com>
438
439 * configure: Regenerate.
440 * po/opcodes.pot: Regenerate.
441
719d8288
NC		 4422018-06-24 Nick Clifton <nickc@redhat.com>
443
444 2.31 branch created.
445
514cd3a0
TC		 4462018-06-19 Tamar Christina <tamar.christina@arm.com>
447
448 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
449 * aarch64-asm-2.c: Regenerate.
450 * aarch64-dis-2.c: Likewise.
451
385e4d0f
MR		 4522018-06-21 Maciej W. Rozycki <macro@mips.com>
453
454 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
455 `-M ginv' option description.
456
160d1b3d
SH		 4572018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
458
459 PR gas/23305
460 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
461 la and lla.
462
d0ac1c44
SM		 4632018-06-19 Simon Marchi <simon.marchi@ericsson.com>
464
465 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
466 * configure.ac: Remove AC_PREREQ.
467 * Makefile.in: Re-generate.
468 * aclocal.m4: Re-generate.
469 * configure: Re-generate.
470
6f20c942
FS		 4712018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
472
473 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
474 mips64r6 descriptors.
475 (parse_mips_ase_option): Handle -Mginv option.
476 (print_mips_disassembler_options): Document -Mginv.
477 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
478 (GINV): New macro.
479 (mips_opcodes): Define ginvi and ginvt.
480
730c3174
SE		 4812018-06-13 Scott Egerton <scott.egerton@imgtec.com>
482 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
483
484 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
485 * mips-opc.c (CRC, CRC64): New macros.
486 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
487 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
488 crc32cd for CRC64.
489
cb366992
EB		 4902018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
491
492 PR 20319
493 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
494 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
495
ce72cd46
AM		 4962018-06-06 Alan Modra <amodra@gmail.com>
497
498 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
499 setjmp. Move init for some other vars later too.
500
4b8e28c7
MF		 5012018-06-04 Max Filippov <jcmvbkbc@gmail.com>
502
503 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
504 (dis_private): Add new fields for property section tracking.
505 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
506 (xtensa_instruction_fits): New functions.
507 (fetch_data): Bump minimal fetch size to 4.
508 (print_insn_xtensa): Make struct dis_private static.
509 Load and prepare property table on section change.
510 Don't disassemble literals. Don't disassemble instructions that
511 cross property table boundaries.
512
55e99962
L		 5132018-06-01 H.J. Lu <hongjiu.lu@intel.com>
514
515 * configure: Regenerated.
516
733bd0ab
JB		 5172018-06-01 Jan Beulich <jbeulich@suse.com>
518
519 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
520 * i386-tbl.h: Re-generate.
521
dfd27d41
JB		 5222018-06-01 Jan Beulich <jbeulich@suse.com>
523
524 * i386-opc.tbl (sldt, str): Add NoRex64.
525 * i386-tbl.h: Re-generate.
526
64795710
JB		 5272018-06-01 Jan Beulich <jbeulich@suse.com>
528
529 * i386-opc.tbl (invpcid): Add Oword.
530 * i386-tbl.h: Re-generate.
531
030157d8
AM		 5322018-06-01 Alan Modra <amodra@gmail.com>
533
534 * sysdep.h (_bfd_error_handler): Don't declare.
535 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
536 * rl78-decode.opc: Likewise.
537 * msp430-decode.c: Regenerate.
538 * rl78-decode.c: Regenerate.
539
a9660a6f
AP		 5402018-05-30 Amit Pawar <Amit.Pawar@amd.com>
541
542 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
543 * i386-init.h : Regenerated.
544
277eb7f6
AM		 5452018-05-25 Alan Modra <amodra@gmail.com>
546
547 * Makefile.in: Regenerate.
548 * po/POTFILES.in: Regenerate.
549
98553ad3
PB		 5502018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
551
552 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
553 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
554 (insert_bab, extract_bab, insert_btab, extract_btab,
555 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
556 (BAT, BBA VBA RBS XB6S): Delete macros.
557 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
558 (BB, BD, RBX, XC6): Update for new macros.
559 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
560 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
561 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
562 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
563
7b4ae824
JD		 5642018-05-18 John Darrington <john@darrington.wattle.id.au>
565
566 * Makefile.am: Add support for s12z architecture.
567 * configure.ac: Likewise.
568 * disassemble.c: Likewise.
569 * disassemble.h: Likewise.
570 * Makefile.in: Regenerate.
571 * configure: Regenerate.
572 * s12z-dis.c: New file.
573 * s12z.h: New file.
574
29e0f0a1
AM		 5752018-05-18 Alan Modra <amodra@gmail.com>
576
577 * nfp-dis.c: Don't #include libbfd.h.
578 (init_nfp3200_priv): Use bfd_get_section_contents.
579 (nit_nfp6000_mecsr_sec): Likewise.
580
809276d2
NC		 5812018-05-17 Nick Clifton <nickc@redhat.com>
582
583 * po/zh_CN.po: Updated simplified Chinese translation.
584
ff329288
TC		 5852018-05-16 Tamar Christina <tamar.christina@arm.com>
586
587 PR binutils/23109
588 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
589 * aarch64-dis-2.c: Regenerate.
590
f9830ec1
TC		 5912018-05-15 Tamar Christina <tamar.christina@arm.com>
592
593 PR binutils/21446
594 * aarch64-asm.c (opintl.h): Include.
595 (aarch64_ins_sysreg): Enforce read/write constraints.
596 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
597 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
598 (F_REG_READ, F_REG_WRITE): New.
599 * aarch64-opc.c (aarch64_print_operand): Generate notes for
600 AARCH64_OPND_SYSREG.
601 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
602 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
603 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
604 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
605 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
606 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
607 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
608 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
609 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
610 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
611 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
612 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
613 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
614 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
615 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
616 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
617 msr (F_SYS_WRITE), mrs (F_SYS_READ).
618
7d02540a
TC		 6192018-05-15 Tamar Christina <tamar.christina@arm.com>
620
621 PR binutils/21446
622 * aarch64-dis.c (no_notes: New.
623 (parse_aarch64_dis_option): Support notes.
624 (aarch64_decode_insn, print_operands): Likewise.
625 (print_aarch64_disassembler_options): Document notes.
626 * aarch64-opc.c (aarch64_print_operand): Support notes.
627
561a72d4
TC		 6282018-05-15 Tamar Christina <tamar.christina@arm.com>
629
630 PR binutils/21446
631 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
632 and take error struct.
633 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
634 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
635 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
636 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
637 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
638 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
639 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
640 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
641 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
642 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
643 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
644 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
645 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
646 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
647 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
648 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
649 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
650 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
651 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
652 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
653 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
654 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
655 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
656 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
657 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
658 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
659 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
660 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
661 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
662 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
663 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
664 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
665 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
666 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
667 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
668 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
669 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
670 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
671 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
672 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
673 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
674 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
675 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
676 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
677 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
678 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
679 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
680 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
681 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
682 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
683 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
684 (determine_disassembling_preference, aarch64_decode_insn,
685 print_insn_aarch64_word, print_insn_data): Take errors struct.
686 (print_insn_aarch64): Use errors.
687 * aarch64-asm-2.c: Regenerate.
688 * aarch64-dis-2.c: Regenerate.
689 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
690 boolean in aarch64_insert_operan.
691 (print_operand_extractor): Likewise.
692 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
693
1678bd35
FT		 6942018-05-15 Francois H. Theron <francois.theron@netronome.com>
695
696 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
697
06cfb1c8
L		 6982018-05-09 H.J. Lu <hongjiu.lu@intel.com>
699
700 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
701
84f9f8c3
AM		 7022018-05-09 Sebastian Rasmussen <sebras@gmail.com>
703
704 * cr16-opc.c (cr16_instruction): Comment typo fix.
705 * hppa-dis.c (print_insn_hppa): Likewise.
706
e6f372ba
JW		 7072018-05-08 Jim Wilson <jimw@sifive.com>
708
709 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
710 (match_c_slli64, match_srxi_as_c_srxi): New.
711 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
712 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
713 <c.slli, c.srli, c.srai>: Use match_s_slli.
714 <c.slli64, c.srli64, c.srai64>: New.
715
f413a913
AM		 7162018-05-08 Alan Modra <amodra@gmail.com>
717
718 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
719 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
720 partition opcode space for index lookup.
721
a87a6478
PB		 7222018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
723
724 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
725 <insn_length>: ...with this. Update usage.
726 Remove duplicate call to *info->memory_error_func.
727
c0a30a9f
L		 7282018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
729 H.J. Lu <hongjiu.lu@intel.com>
730
731 * i386-dis.c (Gva): New.
732 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
733 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
734 (prefix_table): New instructions (see prefix above).
735 (mod_table): New instructions (see prefix above).
736 (OP_G): Handle va_mode.
737 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
738 CPU_MOVDIR64B_FLAGS.
739 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
740 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
741 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
742 * i386-opc.tbl: Add movidir{i,64b}.
743 * i386-init.h: Regenerated.
744 * i386-tbl.h: Likewise.
745
75c0a438
L		 7462018-05-07 H.J. Lu <hongjiu.lu@intel.com>
747
748 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
749 AddrPrefixOpReg.
750 * i386-opc.h (AddrPrefixOp0): Renamed to ...
751 (AddrPrefixOpReg): This.
752 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
753 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
754
2ceb7719
PB		 7552018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
756
757 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
758 (vle_num_opcodes): Likewise.
759 (spe2_num_opcodes): Likewise.
760 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
761 initialization loop.
762 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
763 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
764 only once.
765
b3ac5c6c
TC		 7662018-05-01 Tamar Christina <tamar.christina@arm.com>
767
768 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
769
fe944acf
FT		 7702018-04-30 Francois H. Theron <francois.theron@netronome.com>
771
772 Makefile.am: Added nfp-dis.c.
773 configure.ac: Added bfd_nfp_arch.
774 disassemble.h: Added print_insn_nfp prototype.
775 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
776 nfp-dis.c: New, for NFP support.
777 po/POTFILES.in: Added nfp-dis.c to the list.
778 Makefile.in: Regenerate.
779 configure: Regenerate.
780
e2195274
JB		 7812018-04-26 Jan Beulich <jbeulich@suse.com>
782
783 * i386-opc.tbl: Fold various non-memory operand AVX512VL
784 templates into their base ones.
785 * i386-tlb.h: Re-generate.
786
59ef5df4
JB		 7872018-04-26 Jan Beulich <jbeulich@suse.com>
788
789 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
790 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
791 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
792 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
793 * i386-init.h: Re-generate.
794
6e041cf4
JB		 7952018-04-26 Jan Beulich <jbeulich@suse.com>
796
797 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
798 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
799 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
800 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
801 comment.
802 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
803 and CpuRegMask.
804 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
805 CpuRegMask: Delete.
806 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
807 cpuregzmm, and cpuregmask.
808 * i386-init.h: Re-generate.
809 * i386-tbl.h: Re-generate.
810
0e0eea78
JB		 8112018-04-26 Jan Beulich <jbeulich@suse.com>
812
813 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
814 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
815 * i386-init.h: Re-generate.
816
2f1bada2
JB		 8172018-04-26 Jan Beulich <jbeulich@suse.com>
818
819 * i386-gen.c (VexImmExt): Delete.
820 * i386-opc.h (VexImmExt, veximmext): Delete.
821 * i386-opc.tbl: Drop all VexImmExt uses.
822 * i386-tlb.h: Re-generate.
823
bacd1457
JB		 8242018-04-25 Jan Beulich <jbeulich@suse.com>
825
826 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
827 register-only forms.
828 * i386-tlb.h: Re-generate.
829
10bba94b
TC		 8302018-04-25 Tamar Christina <tamar.christina@arm.com>
831
832 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
833
c48935d7
IT		 8342018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
835
836 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
837 PREFIX_0F1C.
838 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
839 (cpu_flags): Add CpuCLDEMOTE.
840 * i386-init.h: Regenerate.
841 * i386-opc.h (enum): Add CpuCLDEMOTE,
842 (i386_cpu_flags): Add cpucldemote.
843 * i386-opc.tbl: Add cldemote.
844 * i386-tbl.h: Regenerate.
845
211dc24b
AM		 8462018-04-16 Alan Modra <amodra@gmail.com>
847
848 * Makefile.am: Remove sh5 and sh64 support.
849 * configure.ac: Likewise.
850 * disassemble.c: Likewise.
851 * disassemble.h: Likewise.
852 * sh-dis.c: Likewise.
853 * sh64-dis.c: Delete.
854 * sh64-opc.c: Delete.
855 * sh64-opc.h: Delete.
856 * Makefile.in: Regenerate.
857 * configure: Regenerate.
858 * po/POTFILES.in: Regenerate.
859
a9a4b302
AM		 8602018-04-16 Alan Modra <amodra@gmail.com>
861
862 * Makefile.am: Remove w65 support.
863 * configure.ac: Likewise.
864 * disassemble.c: Likewise.
865 * disassemble.h: Likewise.
866 * w65-dis.c: Delete.
867 * w65-opc.h: Delete.
868 * Makefile.in: Regenerate.
869 * configure: Regenerate.
870 * po/POTFILES.in: Regenerate.
871
04cb01fd
AM		 8722018-04-16 Alan Modra <amodra@gmail.com>
873
874 * configure.ac: Remove we32k support.
875 * configure: Regenerate.
876
c2bf1eec
AM		 8772018-04-16 Alan Modra <amodra@gmail.com>
878
879 * Makefile.am: Remove m88k support.
880 * configure.ac: Likewise.
881 * disassemble.c: Likewise.
882 * disassemble.h: Likewise.
883 * m88k-dis.c: Delete.
884 * Makefile.in: Regenerate.
885 * configure: Regenerate.
886 * po/POTFILES.in: Regenerate.
887
6793974d
AM		 8882018-04-16 Alan Modra <amodra@gmail.com>
889
890 * Makefile.am: Remove i370 support.
891 * configure.ac: Likewise.
892 * disassemble.c: Likewise.
893 * disassemble.h: Likewise.
894 * i370-dis.c: Delete.
895 * i370-opc.c: Delete.
896 * Makefile.in: Regenerate.
897 * configure: Regenerate.
898 * po/POTFILES.in: Regenerate.
899
e82aa794
AM		 9002018-04-16 Alan Modra <amodra@gmail.com>
901
902 * Makefile.am: Remove h8500 support.
903 * configure.ac: Likewise.
904 * disassemble.c: Likewise.
905 * disassemble.h: Likewise.
906 * h8500-dis.c: Delete.
907 * h8500-opc.h: Delete.
908 * Makefile.in: Regenerate.
909 * configure: Regenerate.
910 * po/POTFILES.in: Regenerate.
911
fceadf09
AM		 9122018-04-16 Alan Modra <amodra@gmail.com>
913
914 * configure.ac: Remove tahoe support.
915 * configure: Regenerate.
916
ae1d3843
L		 9172018-04-15 H.J. Lu <hongjiu.lu@intel.com>
918
919 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
920 umwait.
921 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
922 64-bit mode.
923 * i386-tbl.h: Regenerated.
924
de89d0a3
IT		 9252018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
926
927 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
928 PREFIX_MOD_1_0FAE_REG_6.
929 (va_mode): New.
930 (OP_E_register): Use va_mode.
931 * i386-dis-evex.h (prefix_table):
932 New instructions (see prefixes above).
933 * i386-gen.c (cpu_flag_init): Add WAITPKG.
934 (cpu_flags): Likewise.
935 * i386-opc.h (enum): Likewise.
936 (i386_cpu_flags): Likewise.
937 * i386-opc.tbl: Add umonitor, umwait, tpause.
938 * i386-init.h: Regenerate.
939 * i386-tbl.h: Likewise.
940
a8eb42a8
AM		 9412018-04-11 Alan Modra <amodra@gmail.com>
942
943 * opcodes/i860-dis.c: Delete.
944 * opcodes/i960-dis.c: Delete.
945 * Makefile.am: Remove i860 and i960 support.
946 * configure.ac: Likewise.
947 * disassemble.c: Likewise.
948 * disassemble.h: Likewise.
949 * Makefile.in: Regenerate.
950 * configure: Regenerate.
951 * po/POTFILES.in: Regenerate.
952
caf0678c
L		 9532018-04-04 H.J. Lu <hongjiu.lu@intel.com>
954
955 PR binutils/23025
956 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
957 to 0.
958 (print_insn): Clear vex instead of vex.evex.
959
4fb0d2b9
NC		 9602018-04-04 Nick Clifton <nickc@redhat.com>
961
962 * po/es.po: Updated Spanish translation.
963
c39e5b26
JB		 9642018-03-28 Jan Beulich <jbeulich@suse.com>
965
966 * i386-gen.c (opcode_modifiers): Delete VecESize.
967 * i386-opc.h (VecESize): Delete.
968 (struct i386_opcode_modifier): Delete vecesize.
969 * i386-opc.tbl: Drop VecESize.
970 * i386-tlb.h: Re-generate.
971
8e6e0792
JB		 9722018-03-28 Jan Beulich <jbeulich@suse.com>
973
974 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
975 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
976 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
977 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
978 * i386-tlb.h: Re-generate.
979
9f123b91
JB		 9802018-03-28 Jan Beulich <jbeulich@suse.com>
981
982 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
983 Fold AVX512 forms
984 * i386-tlb.h: Re-generate.
985
9646c87b
JB		 9862018-03-28 Jan Beulich <jbeulich@suse.com>
987
988 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
989 (vex_len_table): Drop Y for vcvt*2si.
990 (putop): Replace plain 'Y' handling by abort().
991
c8d59609
NC		 9922018-03-28 Nick Clifton <nickc@redhat.com>
993
994 PR 22988
995 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
996 instructions with only a base address register.
997 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
998 handle AARHC64_OPND_SVE_ADDR_R.
999 (aarch64_print_operand): Likewise.
1000 * aarch64-asm-2.c: Regenerate.
1001 * aarch64_dis-2.c: Regenerate.
1002 * aarch64-opc-2.c: Regenerate.
1003
b8c169f3
JB		 10042018-03-22 Jan Beulich <jbeulich@suse.com>
1005
1006 * i386-opc.tbl: Drop VecESize from register only insn forms and
1007 memory forms not allowing broadcast.
1008 * i386-tlb.h: Re-generate.
1009
96bc132a
JB		 10102018-03-22 Jan Beulich <jbeulich@suse.com>
1011
1012 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1013 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1014 sha256*): Drop Disp<N>.
1015
9f79e886
JB		 10162018-03-22 Jan Beulich <jbeulich@suse.com>
1017
1018 * i386-dis.c (EbndS, bnd_swap_mode): New.
1019 (prefix_table): Use EbndS.
1020 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1021 * i386-opc.tbl (bndmov): Move misplaced Load.
1022 * i386-tlb.h: Re-generate.
1023
d6793fa1
JB		 10242018-03-22 Jan Beulich <jbeulich@suse.com>
1025
1026 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1027 templates allowing memory operands and folded ones for register
1028 only flavors.
1029 * i386-tlb.h: Re-generate.
1030
f7768225
JB		 10312018-03-22 Jan Beulich <jbeulich@suse.com>
1032
1033 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1034 256-bit templates. Drop redundant leftover Disp<N>.
1035 * i386-tlb.h: Re-generate.
1036
0e35537d
JW		 10372018-03-14 Kito Cheng <kito.cheng@gmail.com>
1038
1039 * riscv-opc.c (riscv_insn_types): New.
1040
b4a3689a
NC		 10412018-03-13 Nick Clifton <nickc@redhat.com>
1042
1043 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1044
d3d50934
L		 10452018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1046
1047 * i386-opc.tbl: Add Optimize to clr.
1048 * i386-tbl.h: Regenerated.
1049
bd5dea88
L		 10502018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1051
1052 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1053 * i386-opc.h (OldGcc): Removed.
1054 (i386_opcode_modifier): Remove oldgcc.
1055 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1056 instructions for old (<= 2.8.1) versions of gcc.
1057 * i386-tbl.h: Regenerated.
1058
e771e7c9
JB		 10592018-03-08 Jan Beulich <jbeulich@suse.com>
1060
1061 * i386-opc.h (EVEXDYN): New.
1062 * i386-opc.tbl: Fold various AVX512VL templates.
1063 * i386-tlb.h: Re-generate.
1064
ed438a93
JB		 10652018-03-08 Jan Beulich <jbeulich@suse.com>
1066
1067 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1068 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1069 vpexpandd, vpexpandq): Fold AFX512VF templates.
1070 * i386-tlb.h: Re-generate.
1071
454172a9
JB		 10722018-03-08 Jan Beulich <jbeulich@suse.com>
1073
1074 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1075 Fold 128- and 256-bit VEX-encoded templates.
1076 * i386-tlb.h: Re-generate.
1077
36824150
JB		 10782018-03-08 Jan Beulich <jbeulich@suse.com>
1079
1080 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1081 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1082 vpexpandd, vpexpandq): Fold AVX512F templates.
1083 * i386-tlb.h: Re-generate.
1084
e7f5c0a9
JB		 10852018-03-08 Jan Beulich <jbeulich@suse.com>
1086
1087 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1088 64-bit templates. Drop Disp<N>.
1089 * i386-tlb.h: Re-generate.
1090
25a4277f
JB		 10912018-03-08 Jan Beulich <jbeulich@suse.com>
1092
1093 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1094 and 256-bit templates.
1095 * i386-tlb.h: Re-generate.
1096
d2224064
JB		 10972018-03-08 Jan Beulich <jbeulich@suse.com>
1098
1099 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1100 * i386-tlb.h: Re-generate.
1101
1b193f0b
JB		 11022018-03-08 Jan Beulich <jbeulich@suse.com>
1103
1104 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1105 Drop NoAVX.
1106 * i386-tlb.h: Re-generate.
1107
f2f6a710
JB		 11082018-03-08 Jan Beulich <jbeulich@suse.com>
1109
1110 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1111 * i386-tlb.h: Re-generate.
1112
38e314eb
JB		 11132018-03-08 Jan Beulich <jbeulich@suse.com>
1114
1115 * i386-gen.c (opcode_modifiers): Delete FloatD.
1116 * i386-opc.h (FloatD): Delete.
1117 (struct i386_opcode_modifier): Delete floatd.
1118 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1119 FloatD by D.
1120 * i386-tlb.h: Re-generate.
1121
d53e6b98
JB		 11222018-03-08 Jan Beulich <jbeulich@suse.com>
1123
1124 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1125
2907c2f5
JB		 11262018-03-08 Jan Beulich <jbeulich@suse.com>
1127
1128 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1129 * i386-tlb.h: Re-generate.
1130
73053c1f
JB		 11312018-03-08 Jan Beulich <jbeulich@suse.com>
1132
1133 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1134 forms.
1135 * i386-tlb.h: Re-generate.
1136
52fe4420
AM		 11372018-03-07 Alan Modra <amodra@gmail.com>
1138
1139 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1140 bfd_arch_rs6000.
1141 * disassemble.h (print_insn_rs6000): Delete.
1142 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1143 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1144 (print_insn_rs6000): Delete.
1145
a6743a54
AM		 11462018-03-03 Alan Modra <amodra@gmail.com>
1147
1148 * sysdep.h (opcodes_error_handler): Define.
1149 (_bfd_error_handler): Declare.
1150 * Makefile.am: Remove stray #.
1151 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1152 EDIT" comment.
1153 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1154 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1155 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1156 opcodes_error_handler to print errors. Standardize error messages.
1157 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1158 and include opintl.h.
1159 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1160 * i386-gen.c: Standardize error messages.
1161 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1162 * Makefile.in: Regenerate.
1163 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1164 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1165 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1166 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1167 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1168 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1169 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1170 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1171 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1172 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1173 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1174 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1175 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1176
8305403a
L		 11772018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1178
1179 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1180 vpsub[bwdq] instructions.
1181 * i386-tbl.h: Regenerated.
1182
e184813f
AM		 11832018-03-01 Alan Modra <amodra@gmail.com>
1184
1185 * configure.ac (ALL_LINGUAS): Sort.
1186 * configure: Regenerate.
1187
5b616bef
TP		 11882018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1189
1190 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1191 macro by assignements.
1192
b6f8c7c4
L		 11932018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1194
1195 PR gas/22871
1196 * i386-gen.c (opcode_modifiers): Add Optimize.
1197 * i386-opc.h (Optimize): New enum.
1198 (i386_opcode_modifier): Add optimize.
1199 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1200 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1201 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1202 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1203 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1204 vpxord and vpxorq.
1205 * i386-tbl.h: Regenerated.
1206
e95b887f
AM		 12072018-02-26 Alan Modra <amodra@gmail.com>
1208
1209 * crx-dis.c (getregliststring): Allocate a large enough buffer
1210 to silence false positive gcc8 warning.
1211
0bccfb29
JW		 12122018-02-22 Shea Levy <shea@shealevy.com>
1213
1214 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1215
6b6b6807
L		 12162018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1217
1218 * i386-opc.tbl: Add {rex},
1219 * i386-tbl.h: Regenerated.
1220
75f31665
MR		 12212018-02-20 Maciej W. Rozycki <macro@mips.com>
1222
1223 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1224 (mips16_opcodes): Replace `M' with `m' for "restore".
1225
e207bc53
TP		 12262018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1227
1228 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1229
87993319
MR		 12302018-02-13 Maciej W. Rozycki <macro@mips.com>
1231
1232 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1233 variable to `function_index'.
1234
68d20676
NC		 12352018-02-13 Nick Clifton <nickc@redhat.com>
1236
1237 PR 22823
1238 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1239 about truncation of printing.
1240
d2159fdc
HW		 12412018-02-12 Henry Wong <henry@stuffedcow.net>
1242
1243 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1244
f174ef9f
NC		 12452018-02-05 Nick Clifton <nickc@redhat.com>
1246
1247 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1248
be3a8dca
IT		 12492018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1250
1251 * i386-dis.c (enum): Add pconfig.
1252 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1253 (cpu_flags): Add CpuPCONFIG.
1254 * i386-opc.h (enum): Add CpuPCONFIG.
1255 (i386_cpu_flags): Add cpupconfig.
1256 * i386-opc.tbl: Add PCONFIG instruction.
1257 * i386-init.h: Regenerate.
1258 * i386-tbl.h: Likewise.
1259
3233d7d0
IT		 12602018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1261
1262 * i386-dis.c (enum): Add PREFIX_0F09.
1263 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1264 (cpu_flags): Add CpuWBNOINVD.
1265 * i386-opc.h (enum): Add CpuWBNOINVD.
1266 (i386_cpu_flags): Add cpuwbnoinvd.
1267 * i386-opc.tbl: Add WBNOINVD instruction.
1268 * i386-init.h: Regenerate.
1269 * i386-tbl.h: Likewise.
1270
e925c834
JW		 12712018-01-17 Jim Wilson <jimw@sifive.com>
1272
1273 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1274
d777820b
IT		 12752018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1276
1277 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1278 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1279 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1280 (cpu_flags): Add CpuIBT, CpuSHSTK.
1281 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1282 (i386_cpu_flags): Add cpuibt, cpushstk.
1283 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1284 * i386-init.h: Regenerate.
1285 * i386-tbl.h: Likewise.
1286
f6efed01
NC		 12872018-01-16 Nick Clifton <nickc@redhat.com>
1288
1289 * po/pt_BR.po: Updated Brazilian Portugese translation.
1290 * po/de.po: Updated German translation.
1291
2721d702
JW		 12922018-01-15 Jim Wilson <jimw@sifive.com>
1293
1294 * riscv-opc.c (match_c_nop): New.
1295 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1296
616dcb87
NC		 12972018-01-15 Nick Clifton <nickc@redhat.com>
1298
1299 * po/uk.po: Updated Ukranian translation.
1300
3957a496
NC		 13012018-01-13 Nick Clifton <nickc@redhat.com>
1302
1303 * po/opcodes.pot: Regenerated.
1304
769c7ea5
NC		 13052018-01-13 Nick Clifton <nickc@redhat.com>
1306
1307 * configure: Regenerate.
1308
faf766e3
NC		 13092018-01-13 Nick Clifton <nickc@redhat.com>
1310
1311 2.30 branch created.
1312
888a89da
IT		 13132018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1314
1315 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1316 * i386-tbl.h: Regenerate.
1317
cbda583a
JB		 13182018-01-10 Jan Beulich <jbeulich@suse.com>
1319
1320 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1321 * i386-tbl.h: Re-generate.
1322
c9e92278
JB		 13232018-01-10 Jan Beulich <jbeulich@suse.com>
1324
1325 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1326 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1327 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1328 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1329 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1330 Disp8MemShift of AVX512VL forms.
1331 * i386-tbl.h: Re-generate.
1332
35fd2b2b
JW		 13332018-01-09 Jim Wilson <jimw@sifive.com>
1334
1335 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1336 then the hi_addr value is zero.
1337
91d8b670
JG		 13382018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1339
1340 * arm-dis.c (arm_opcodes): Add csdb.
1341 (thumb32_opcodes): Add csdb.
1342
be2e7d95
JG		 13432018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1344
1345 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1346 * aarch64-asm-2.c: Regenerate.
1347 * aarch64-dis-2.c: Regenerate.
1348 * aarch64-opc-2.c: Regenerate.
1349
704a705d
L		 13502018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1351
1352 PR gas/22681
1353 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1354 Remove AVX512 vmovd with 64-bit operands.
1355 * i386-tbl.h: Regenerated.
1356
35eeb78f
JW		 13572018-01-05 Jim Wilson <jimw@sifive.com>
1358
1359 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1360 jalr.
1361
219d1afa
AM		 13622018-01-03 Alan Modra <amodra@gmail.com>
1363
1364 Update year range in copyright notice of all files.
1365
1508bbf5
JB		 13662018-01-02 Jan Beulich <jbeulich@suse.com>
1367
1368 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1369 and OPERAND_TYPE_REGZMM entries.
1370
1e563868 1371For older changes see ChangeLog-2017
3499769a 1372\f
1e563868 1373Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1374
1375Copying and distribution of this file, with or without modification,
1376are permitted in any medium without royalty provided the copyright
1377notice and this notice are preserved.
1378
1379Local Variables:
1380mode: change-log
1381left-margin: 8
1382fill-column: 74
1383version-control: never
1384End:
GDB Binutils - Deliverables
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