Add a note to the GDB/NEWS file mentioning that the ARM simulator now
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
2cf200a4
IT
12014-04-04 Ilya Tocar <ilya.tocar@intel.com>
2
3 * i386-dis.c (rm_table): Add encls, enclu.
4 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
5 (cpu_flags): Add CpuSE1.
6 * i386-opc.h (enum): Add CpuSE1.
7 (i386_cpu_flags): Add cpuse1.
8 * i386-opc.tbl: Add encls, enclu.
9 * i386-init.h: Regenerated.
10 * i386-tbl.h: Likewise.
11
31c981bc
AG
122014-04-02 Anthony Green <green@moxielogic.com>
13
14 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
15 instructions, sex.b and sex.s.
16
76dfed02
YZ
172014-03-26 Jiong Wang <jiong.wang@arm.com>
18
19 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
20 instructions.
21
5fc35d96
IT
222014-03-20 Ilya Tocar <ilya.tocar@intel.com>
23
24 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
25 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
26 vscatterqps.
27 * i386-tbl.h: Regenerate.
28
ec92c392
JM
292014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
30
31 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
32 %hstick_enable added.
33
b8985e5c
NC
342014-03-19 Nick Clifton <nickc@redhat.com>
35
36 * rx-decode.opc (bwl): Allow for bogus instructions with a size
37 field of 3.
b41c812c 38 (sbwl, ubwl, SCALE): Likewise.
b8985e5c
NC
39 * rx-decode.c: Regenerate.
40
fa47fa92
AM
412014-03-12 Alan Modra <amodra@gmail.com>
42
43 * Makefile.in: Regenerate.
44
4b95cf5c
AM
452014-03-05 Alan Modra <amodra@gmail.com>
46
47 Update copyright years.
48
cd0c81e9 492014-03-04 Heiher <r@hev.cc>
4ba154f5
RS
50
51 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
52
079b5aec
RS
532014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
54
55 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
56 so that they come after the Loongson extensions.
57
2c80b753
AM
582014-03-03 Alan Modra <amodra@gmail.com>
59
60 * i386-gen.c (process_copyright): Emit copyright notice on one line.
61
b721f1fa
AM
622014-02-28 Alan Modra <amodra@gmail.com>
63
64 * msp430-decode.c: Regenerate.
65
f17c8bfc
YZ
662014-02-27 Jiong Wang <jiong.wang@arm.com>
67
68 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
69 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
70
a58549dd
YZ
712014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
72
73 * aarch64-opc.c (print_register_offset_address): Call
74 get_int_reg_name to prepare the register name.
75
d6e9dd78
IT
762014-02-25 Ilya Tocar <ilya.tocar@intel.com>
77
78 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
79 * i386-tbl.h: Regenerate.
80
812014-02-20 Ilya Tocar <ilya.tocar@intel.com>
dcf893b5
IT
82
83 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
84 (cpu_flags): Add CpuPREFETCHWT1.
85 * i386-init.h: Regenerate.
86 * i386-opc.h (CpuPREFETCHWT1): New.
87 (i386_cpu_flags): Add cpuprefetchwt1.
88 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
89 * i386-tbl.h: Regenerate.
90
957d0955
IT
912014-02-20 Ilya Tocar <ilya.tocar@intel.com>
92
93 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
94 to CpuAVX512F.
95 * i386-tbl.h: Regenerate.
96
10632b79
L
972014-02-19 H.J. Lu <hongjiu.lu@intel.com>
98
99 * i386-gen.c (output_cpu_flags): Don't output trailing space.
100 (output_opcode_modifier): Likewise.
101 (output_operand_type): Likewise.
102 * i386-init.h: Regenerated.
103 * i386-tbl.h: Likewise.
104
963f3586
IT
1052014-02-12 Ilya Tocar <ilya.tocar@intel.com>
106
107 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
108 MOD_0FC7_REG_5.
109 (PREFIX enum): Add PREFIX_0FAE_REG_7.
110 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
111 (prefix_table): Add clflusopt.
112 (mod_table): Add xrstors, xsavec, xsaves.
113 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
114 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
115 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
116 * i386-init.h: Regenerate.
117 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
118 xsaves64, xsavec, xsavec64.
119 * i386-tbl.h: Regenerate.
120
c1c69e83
AM
1212014-02-10 Alan Modra <amodra@gmail.com>
122
123 * po/POTFILES.in: Regenerate.
124 * po/opcodes.pot: Regenerate.
125
eaa9d1ad
MZ
1262014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
127 Jan Beulich <jbeulich@suse.com>
128
129 PR binutils/16490
130 * i386-dis.c (OP_E_memory): Fix shift computation for
131 vex_vsib_q_w_dq_mode.
132
e2e6193d
RM
1332014-01-09 Bradley Nelson <bradnelson@google.com>
134 Roland McGrath <mcgrathr@google.com>
135
136 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
137 last_rex_prefix is -1.
138
221fd5d5
L
1392014-01-08 H.J. Lu <hongjiu.lu@intel.com>
140
141 * i386-gen.c (process_copyright): Update copyright year to 2014.
142
b0b0c9fc
MR
1432014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
144
145 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
146
5fb776a6 147For older changes see ChangeLog-2013
252b5132 148\f
5fb776a6 149Copyright (C) 2014 Free Software Foundation, Inc.
752937aa
NC
150
151Copying and distribution of this file, with or without modification,
152are permitted in any medium without royalty provided the copyright
153notice and this notice are preserved.
154
252b5132 155Local Variables:
2f6d2f85
NC
156mode: change-log
157left-margin: 8
158fill-column: 74
252b5132
RH
159version-control: never
160End:
This page took 0.67746 seconds and 4 git commands to generate.