Commit | Line | Data |
---|---|---|
539e75ad L |
1 | 2006-09-23 H.J. Lu <hongjiu.lu@intel.com> |
2 | ||
3 | PR binutils/3235 | |
4 | * i386-dis.c (OP_OFF64): Get 32bit offset if there is an | |
5 | address size prefix. | |
6 | ||
1c0d3aa6 NC |
7 | 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn> |
8 | ||
9 | * score-dis.c: New file. | |
10 | * score-opc.h: New file. | |
11 | * Makefile.am: Add Score files. | |
12 | * Makefile.in: Regenerate. | |
13 | * configure.in: Add support for Score target. | |
14 | * configure: Regenerate. | |
15 | * disassemble.c: Add support for Score target. | |
16 | ||
0112cd26 NC |
17 | 2006-09-16 Nick Clifton <nickc@redhat.com> |
18 | Pedro Alves <pedro_alves@portugalmail.pt> | |
19 | ||
20 | * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ | |
21 | macros defined in bfd.h. | |
22 | * cris-dis.c: Likewise. | |
23 | * h8300-dis.c: Likewise. | |
24 | * i386-dis.c: Likewise. | |
25 | * ia64-gen.c: Likewise. | |
26 | * mips-dis: Likewise. | |
27 | ||
428e3f1f PB |
28 | 2006-09-04 Paul Brook <paul@codesourcery.com> |
29 | ||
30 | * arm-dis.c (neon_opcode): Fix suffix on VMOVN. | |
31 | ||
96fbad73 L |
32 | 2006-08-23 H.J. Lu <hongjiu.lu@intel.com> |
33 | ||
34 | * i386-dis.c (three_byte_table): Expand to 256 elements. | |
35 | ||
36 | 2006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> | |
4d9567e0 | 37 | |
a7a8d8e5 | 38 | PR binutils/3000 |
4d9567e0 MM |
39 | * i386-dis.c (MXC,EMC): Define. |
40 | (OP_MXC): New function to handle cvt* (convert instructions) between | |
41 | %xmm and %mm register correctly. | |
42 | (OP_EMC): ditto. | |
96fbad73 | 43 | (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi |
4d9567e0 MM |
44 | instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately |
45 | with EMC/MXC. | |
46 | ||
777b13b9 RS |
47 | 2006-07-29 Richard Sandiford <richard@codesourcery.com> |
48 | ||
49 | * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire | |
50 | "fdaddl" entry. | |
51 | ||
401a54cf PB |
52 | 2006-07-19 Paul Brook <paul@codesourcery.com> |
53 | ||
54 | * armd-dis.c (arm_opcodes): Fix rbit opcode. | |
55 | ||
2b516b72 L |
56 | 2006-07-18 H.J. Lu <hongjiu.lu@intel.com> |
57 | ||
58 | * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to | |
59 | "sldt", "str" and "smsw". | |
60 | ||
10505f38 L |
61 | 2006-07-15 H.J. Lu <hongjiu.lu@intel.com> |
62 | ||
63 | PR binutils/2829 | |
64 | * i386-dis.c (GRP11_C6): NEW. | |
65 | (GRP11_C7): Likewise. | |
66 | (GRP12): Updated. | |
67 | (GRP13): Likewise. | |
68 | (GRP14): Likewise. | |
69 | (GRP15): Likewise. | |
70 | (GRP16): Likewise. | |
71 | (GRPAMD): Likewise. | |
72 | (GRPPADLCK1): Likewise. | |
73 | (GRPPADLCK2): Likewise. | |
74 | (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7, | |
75 | respectively. | |
76 | (grps): Add entries for GRP11_C6 and GRP11_C7. | |
77 | ||
050dfa73 MM |
78 | 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> |
79 | Michael Meissner <michael.meissner@amd.com> | |
80 | ||
81 | * i386-dis.c (dis386): Add support for 4 operand instructions. Add | |
82 | support for amdfam10 SSE4a/ABM instructions. Modify all | |
83 | initializer macros to have additional arguments. Disallow REP | |
84 | prefix for non-string instructions. | |
85 | (print_insn): Ditto. | |
86 | ||
87 | ||
e8b42ce4 JB |
88 | 2006-07-05 Julian Brown <julian@codesourcery.com> |
89 | ||
90 | * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax. | |
91 | ||
15965411 L |
92 | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> |
93 | ||
94 | * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f. | |
95 | (twobyte_has_modrm): Set 1 for 0x1f. | |
96 | ||
46e883c5 L |
97 | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> |
98 | ||
99 | * i386-dis.c (NOP_Fixup): Removed. | |
100 | (NOP_Fixup1): New. | |
101 | (NOP_Fixup2): Likewise. | |
102 | (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90. | |
103 | ||
4e9d3b81 JB |
104 | 2006-06-12 Julian Brown <julian@codesourcery.com> |
105 | ||
106 | * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed | |
107 | on 64-bit hosts. | |
108 | ||
b3882df9 L |
109 | 2006-06-10 H.J. Lu <hongjiu.lu@intel.com> |
110 | ||
111 | * i386.c (GRP10): Renamed to ... | |
112 | (GRP12): This. | |
113 | (GRP11): Renamed to ... | |
114 | (GRP13): This. | |
115 | (GRP12): Renamed to ... | |
116 | (GRP14): This. | |
117 | (GRP13): Renamed to ... | |
118 | (GRP15): This. | |
119 | (GRP14): Renamed to ... | |
120 | (GRP16): This. | |
121 | (dis386_twobyte): Updated. | |
122 | (grps): Likewise. | |
123 | ||
5f4df3dd NC |
124 | 2006-06-09 Nick Clifton <nickc@redhat.com> |
125 | ||
126 | * po/fi.po: Updated Finnish translation. | |
127 | ||
6648b7cf JM |
128 | 2006-06-07 Joseph S. Myers <joseph@codesourcery.com> |
129 | ||
130 | * po/Make-in (pdf, ps): New dummy targets. | |
131 | ||
c22aaad1 PB |
132 | 2006-06-06 Paul Brook <paul@codesourcery.com> |
133 | ||
134 | * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm | |
135 | instructions. | |
136 | (neon_opcodes): Add conditional execution specifiers. | |
137 | (thumb_opcodes): Ditto. | |
138 | (thumb32_opcodes): Ditto. | |
139 | (arm_conditional): Change 0xe to "al" and add "" to end. | |
140 | (ifthen_state, ifthen_next_state, ifthen_address): New. | |
141 | (IFTHEN_COND): Define. | |
142 | (print_insn_coprocessor, print_insn_neon): Print thumb conditions. | |
143 | (print_insn_arm): Change %c to use new values of arm_conditional. | |
144 | (print_insn_thumb16): Print thumb conditions. Add %I. | |
145 | (print_insn_thumb32): Print thumb conditions. | |
146 | (find_ifthen_state): New function. | |
147 | (print_insn): Track IT block state. | |
148 | ||
9622b051 AM |
149 | 2006-06-06 Ben Elliston <bje@au.ibm.com> |
150 | Anton Blanchard <anton@samba.org> | |
151 | Peter Bergner <bergner@vnet.ibm.com> | |
152 | ||
153 | * ppc-dis.c (powerpc_dialect): Handle power6 option. | |
154 | (print_ppc_disassembler_options): Mention power6. | |
155 | ||
65263ce3 TS |
156 | 2006-06-06 Thiemo Seufer <ths@mips.com> |
157 | Chao-ying Fu <fu@mips.com> | |
158 | ||
159 | * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2. | |
160 | * mips-opc.c: Add DSP64 instructions. | |
161 | ||
92ce91bb AM |
162 | 2006-06-06 Alan Modra <amodra@bigpond.net.au> |
163 | ||
164 | * m68hc11-dis.c (print_insn): Warning fix. | |
165 | ||
4cfe2c59 DJ |
166 | 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com> |
167 | ||
168 | * po/Make-in (top_builddir): Define. | |
169 | ||
7ff1a5b5 AM |
170 | 2006-06-05 Alan Modra <amodra@bigpond.net.au> |
171 | ||
172 | * Makefile.am: Run "make dep-am". | |
173 | * Makefile.in: Regenerate. | |
174 | * config.in: Regenerate. | |
175 | ||
20e95c23 DJ |
176 | 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com> |
177 | ||
178 | * Makefile.am (INCLUDES): Use @INCINTL@. | |
179 | * acinclude.m4: Include new gettext macros. | |
180 | * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS. | |
181 | Remove local code for po/Makefile. | |
182 | * Makefile.in, aclocal.m4, configure: Regenerated. | |
183 | ||
eebf07fb NC |
184 | 2006-05-30 Nick Clifton <nickc@redhat.com> |
185 | ||
186 | * po/es.po: Updated Spanish translation. | |
187 | ||
a596001e RS |
188 | 2006-05-25 Richard Sandiford <richard@codesourcery.com> |
189 | ||
190 | * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd | |
191 | and fmovem entries. Put register list entries before immediate | |
192 | mask entries. Use "l" rather than "L" in the fmovem entries. | |
193 | * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it | |
194 | out from INFO. | |
195 | (m68k_scan_mask): New function, split out from... | |
196 | (print_insn_m68k): ...here. If no architecture has been set, | |
197 | first try printing an m680x0 instruction, then try a Coldfire one. | |
198 | ||
4a4d496a NC |
199 | 2006-05-24 Nick Clifton <nickc@redhat.com> |
200 | ||
201 | * po/ga.po: Updated Irish translation. | |
202 | ||
a854efa3 NC |
203 | 2006-05-22 Nick Clifton <nickc@redhat.com> |
204 | ||
205 | * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts. | |
206 | ||
0bd79061 NC |
207 | 2006-05-22 Nick Clifton <nickc@redhat.com> |
208 | ||
209 | * po/nl.po: Updated translation. | |
210 | ||
00988f49 AM |
211 | 2006-05-18 Alan Modra <amodra@bigpond.net.au> |
212 | ||
213 | * avr-dis.c: Formatting fix. | |
214 | ||
9b3f89ee TS |
215 | 2006-05-14 Thiemo Seufer <ths@mips.com> |
216 | ||
217 | * mips16-opc.c (I1, I32, I64): New shortcut defines. | |
218 | (mips16_opcodes): Change membership of instructions to their | |
219 | lowest baseline ISA. | |
220 | ||
cb6d3433 L |
221 | 2006-05-09 H.J. Lu <hongjiu.lu@intel.com> |
222 | ||
223 | * i386-dis.c (grps): Update sgdt/sidt for 64bit. | |
224 | ||
1f3c39b9 JB |
225 | 2006-05-05 Julian Brown <julian@codesourcery.com> |
226 | ||
227 | * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as | |
228 | vldm/vstm. | |
229 | ||
d43b4baf TS |
230 | 2006-05-05 Thiemo Seufer <ths@mips.com> |
231 | David Ung <davidu@mips.com> | |
232 | ||
233 | * mips-opc.c: Add macro for cache instruction. | |
234 | ||
39a7806d TS |
235 | 2006-05-04 Thiemo Seufer <ths@mips.com> |
236 | Nigel Stephens <nigel@mips.com> | |
237 | David Ung <davidu@mips.com> | |
238 | ||
239 | * mips-dis.c (mips_arch_choices): Add smartmips instruction | |
240 | decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release | |
241 | 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to | |
242 | MIPS64R2. | |
243 | * mips-opc.c: fix random typos in comments. | |
244 | (INSN_SMARTMIPS): New defines. | |
245 | (mips_builtin_opcodes): Add paired single support for MIPS32R2. | |
246 | Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd, | |
247 | flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the | |
248 | FP_S and FP_D flags to denote single and double register | |
249 | accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards. | |
250 | Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1 | |
251 | for MIPS32R2. Add SmartMIPS instructions. Add two-argument | |
252 | variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to | |
253 | release 2 ISAs. | |
254 | * mips16-opc.c (mips16_opcodes): Add sdbbp instruction. | |
255 | ||
104b4fab TS |
256 | 2006-05-03 Thiemo Seufer <ths@mips.com> |
257 | ||
258 | * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order. | |
259 | ||
022fac6d TS |
260 | 2006-05-02 Thiemo Seufer <ths@mips.com> |
261 | Nigel Stephens <nigel@mips.com> | |
262 | David Ung <davidu@mips.com> | |
263 | ||
264 | * mips-dis.c (print_insn_args): Force mips16 to odd addresses. | |
265 | (print_mips16_insn_arg): Force mips16 to odd addresses. | |
266 | ||
9bcd4f99 TS |
267 | 2006-04-30 Thiemo Seufer <ths@mips.com> |
268 | David Ung <davidu@mips.com> | |
269 | ||
270 | * mips-opc.c (mips_builtin_opcodes): Add udi instructions | |
271 | "udi0" to "udi15". | |
272 | * mips-dis.c (print_insn_args): Adds udi argument handling. | |
273 | ||
f095b97b JW |
274 | 2006-04-28 James E Wilson <wilson@specifix.com> |
275 | ||
276 | * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing | |
277 | error message. | |
278 | ||
59c455b3 TS |
279 | 2006-04-28 Thiemo Seufer <ths@mips.com> |
280 | David Ung <davidu@mips.com> | |
bdb09db1 | 281 | Nigel Stephens <nigel@mips.com> |
59c455b3 TS |
282 | |
283 | * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register | |
284 | names. | |
285 | ||
cc0ca239 | 286 | 2006-04-28 Thiemo Seufer <ths@mips.com> |
bdb09db1 | 287 | Nigel Stephens <nigel@mips.com> |
cc0ca239 TS |
288 | David Ung <davidu@mips.com> |
289 | ||
290 | * mips-dis.c (print_insn_args): Add mips_opcode argument. | |
291 | (print_insn_mips): Adjust print_insn_args call. | |
292 | ||
0d09bfe6 | 293 | 2006-04-28 Thiemo Seufer <ths@mips.com> |
bdb09db1 | 294 | Nigel Stephens <nigel@mips.com> |
0d09bfe6 TS |
295 | |
296 | * mips-dis.c (print_insn_args): Print $fcc only for FP | |
297 | instructions, use $cc elsewise. | |
298 | ||
654c225a | 299 | 2006-04-28 Thiemo Seufer <ths@mips.com> |
bdb09db1 | 300 | Nigel Stephens <nigel@mips.com> |
654c225a TS |
301 | |
302 | * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): | |
303 | Map MIPS16 registers to O32 names. | |
304 | (print_mips16_insn_arg): Use mips16_reg_names. | |
305 | ||
0dbde4cf JB |
306 | 2006-04-26 Julian Brown <julian@codesourcery.com> |
307 | ||
308 | * arm-dis.c (print_insn_neon): Disassemble floating-point constant | |
309 | VMOV. | |
310 | ||
16980d0b JB |
311 | 2006-04-26 Nathan Sidwell <nathan@codesourcery.com> |
312 | Julian Brown <julian@codesourcery.com> | |
313 | ||
314 | * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert | |
315 | %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?]. | |
316 | Add unified load/store instruction names. | |
317 | (neon_opcode_table): New. | |
318 | (arm_opcodes): Expand meaning of %<bitfield>['`?]. | |
319 | (arm_decode_bitfield): New. | |
320 | (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers. | |
321 | Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y. | |
322 | (print_insn_neon): New. | |
323 | (print_insn_arm): Adjust print_insn_coprocessor call. Call | |
324 | print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers. | |
325 | (print_insn_thumb32): Likewise. | |
326 | ||
ec3fcc56 AM |
327 | 2006-04-19 Alan Modra <amodra@bigpond.net.au> |
328 | ||
329 | * Makefile.am: Run "make dep-am". | |
330 | * Makefile.in: Regenerate. | |
331 | ||
241a6c40 AM |
332 | 2006-04-19 Alan Modra <amodra@bigpond.net.au> |
333 | ||
7c6646cd AM |
334 | * avr-dis.c (avr_operand): Warning fix. |
335 | ||
241a6c40 AM |
336 | * configure: Regenerate. |
337 | ||
e7403566 DJ |
338 | 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com> |
339 | ||
340 | * po/POTFILES.in: Regenerated. | |
341 | ||
52f16a0e NC |
342 | 2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de> |
343 | ||
344 | PR binutils/2454 | |
345 | * avr-dis.c (avr_operand): Arrange for a comment to appear before | |
346 | the symolic form of an address, so that the output of objdump -d | |
347 | can be reassembled. | |
348 | ||
e78efa90 DD |
349 | 2006-04-10 DJ Delorie <dj@redhat.com> |
350 | ||
351 | * m32c-asm.c: Regenerate. | |
352 | ||
108a6f8e CD |
353 | 2006-04-06 Carlos O'Donell <carlos@codesourcery.com> |
354 | ||
355 | * Makefile.am: Add install-html target. | |
356 | * Makefile.in: Regenerate. | |
357 | ||
a135cb2c NC |
358 | 2006-04-06 Nick Clifton <nickc@redhat.com> |
359 | ||
360 | * po/vi/po: Updated Vietnamese translation. | |
361 | ||
47426b41 AM |
362 | 2006-03-31 Paul Koning <ni1d@arrl.net> |
363 | ||
364 | * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction. | |
365 | ||
331f1cbe BS |
366 | 2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com> |
367 | ||
368 | * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the | |
369 | logic to identify halfword shifts. | |
370 | ||
c16d2bf0 PB |
371 | 2006-03-16 Paul Brook <paul@codesourcery.com> |
372 | ||
373 | * arm-dis.c (arm_opcodes): Rename swi to svc. | |
374 | (thumb_opcodes): Ditto. | |
375 | ||
5348b81e DD |
376 | 2006-03-13 DJ Delorie <dj@redhat.com> |
377 | ||
5398310a DD |
378 | * m32c-asm.c: Regenerate. |
379 | * m32c-desc.c: Likewise. | |
380 | * m32c-desc.h: Likewise. | |
381 | * m32c-dis.c: Likewise. | |
382 | * m32c-ibld.c: Likewise. | |
5348b81e DD |
383 | * m32c-opc.c: Likewise. |
384 | * m32c-opc.h: Likewise. | |
385 | ||
253d272c DD |
386 | 2006-03-10 DJ Delorie <dj@redhat.com> |
387 | ||
388 | * m32c-desc.c: Regenerate with mul.l, mulu.l. | |
389 | * m32c-opc.c: Likewise. | |
390 | * m32c-opc.h: Likewise. | |
391 | ||
392 | ||
f530741d NC |
393 | 2006-03-09 Nick Clifton <nickc@redhat.com> |
394 | ||
395 | * po/sv.po: Updated Swedish translation. | |
396 | ||
35c52694 L |
397 | 2006-03-07 H.J. Lu <hongjiu.lu@intel.com> |
398 | ||
399 | PR binutils/2428 | |
400 | * i386-dis.c (REP_Fixup): New function. | |
401 | (AL): Remove duplicate. | |
402 | (Xbr): New. | |
403 | (Xvr): Likewise. | |
404 | (Ybr): Likewise. | |
405 | (Yvr): Likewise. | |
406 | (indirDXr): Likewise. | |
407 | (ALr): Likewise. | |
408 | (eAXr): Likewise. | |
409 | (dis386): Updated entries of ins, outs, movs, lods and stos. | |
410 | ||
ed963e2d NC |
411 | 2006-03-05 Nick Clifton <nickc@redhat.com> |
412 | ||
413 | * cgen-ibld.in (insert_normal): Cope with attempts to insert a | |
414 | signed 32-bit value into an unsigned 32-bit field when the host is | |
415 | a 64-bit machine. | |
416 | * fr30-ibld.c: Regenerate. | |
417 | * frv-ibld.c: Regenerate. | |
418 | * ip2k-ibld.c: Regenerate. | |
419 | * iq2000-asm.c: Regenerate. | |
420 | * iq2000-ibld.c: Regenerate. | |
421 | * m32c-ibld.c: Regenerate. | |
422 | * m32r-ibld.c: Regenerate. | |
423 | * openrisc-ibld.c: Regenerate. | |
424 | * xc16x-ibld.c: Regenerate. | |
425 | * xstormy16-ibld.c: Regenerate. | |
426 | ||
c7d41dc5 NC |
427 | 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com) |
428 | ||
429 | * xc16x-asm.c: Regenerate. | |
430 | * xc16x-dis.c: Regenerate. | |
c7d41dc5 | 431 | |
f7d9e5c3 CD |
432 | 2006-02-27 Carlos O'Donell <carlos@codesourcery.com> |
433 | ||
434 | * po/Make-in: Add html target. | |
435 | ||
331d2d0d L |
436 | 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> |
437 | ||
438 | * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by | |
439 | Intel Merom New Instructions. | |
440 | (THREE_BYTE_0): Likewise. | |
441 | (THREE_BYTE_1): Likewise. | |
442 | (three_byte_table): Likewise. | |
443 | (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use | |
444 | THREE_BYTE_1 for entry 0x3a. | |
445 | (twobyte_has_modrm): Updated. | |
446 | (twobyte_uses_SSE_prefix): Likewise. | |
447 | (print_insn): Handle 3-byte opcodes used by Intel Merom New | |
448 | Instructions. | |
449 | ||
ff3f9d5b DM |
450 | 2006-02-24 David S. Miller <davem@sunset.davemloft.net> |
451 | ||
452 | * sparc-dis.c (v9_priv_reg_names): Add "gl" entry. | |
453 | (v9_hpriv_reg_names): New table. | |
454 | (print_insn_sparc): Allow values up to 16 for '?' and '!'. | |
455 | New cases '$' and '%' for read/write hyperprivileged register. | |
456 | * sparc-opc.c (sparc_opcodes): Add new entries for UA2005 | |
457 | window handling and rdhpr/wrhpr instructions. | |
458 | ||
6772dd07 DD |
459 | 2006-02-24 DJ Delorie <dj@redhat.com> |
460 | ||
461 | * m32c-desc.c: Regenerate with linker relaxation attributes. | |
462 | * m32c-desc.h: Likewise. | |
463 | * m32c-dis.c: Likewise. | |
464 | * m32c-opc.c: Likewise. | |
465 | ||
62b3e311 PB |
466 | 2006-02-24 Paul Brook <paul@codesourcery.com> |
467 | ||
468 | * arm-dis.c (arm_opcodes): Add V7 instructions. | |
469 | (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants. | |
470 | (print_arm_address): New function. | |
471 | (print_insn_arm): Use it. Add 'P' and 'U' cases. | |
472 | (psr_name): New function. | |
473 | (print_insn_thumb32): Add 'U', 'C' and 'D' cases. | |
474 | ||
59cf82fe L |
475 | 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> |
476 | ||
477 | * ia64-opc-i.c (bXc): New. | |
478 | (mXc): Likewise. | |
479 | (OpX2TaTbYaXcC): Likewise. | |
480 | (TF). Likewise. | |
481 | (TFCM). Likewise. | |
482 | (ia64_opcodes_i): Add instructions for tf. | |
483 | ||
484 | * ia64-opc.h (IMMU5b): New. | |
485 | ||
486 | * ia64-asmtab.c: Regenerated. | |
487 | ||
19a7219f L |
488 | 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> |
489 | ||
490 | * ia64-gen.c: Update copyright years. | |
491 | * ia64-opc-b.c: Likewise. | |
492 | ||
7f3dfb9c L |
493 | 2006-02-22 H.J. Lu <hongjiu.lu@intel.com> |
494 | ||
495 | * ia64-gen.c (lookup_regindex): Handle ".vm". | |
496 | (print_dependency_table): Handle '\"'. | |
497 | ||
498 | * ia64-ic.tbl: Updated from SDM 2.2. | |
499 | * ia64-raw.tbl: Likewise. | |
500 | * ia64-waw.tbl: Likewise. | |
501 | * ia64-asmtab.c: Regenerated. | |
502 | ||
503 | * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1. | |
504 | ||
d70c5fc7 NC |
505 | 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com> |
506 | Anil Paranjape <anilp1@kpitcummins.com> | |
507 | Shilin Shakti <shilins@kpitcummins.com> | |
508 | ||
509 | * xc16x-desc.h: New file | |
510 | * xc16x-desc.c: New file | |
511 | * xc16x-opc.h: New file | |
512 | * xc16x-opc.c: New file | |
513 | * xc16x-ibld.c: New file | |
514 | * xc16x-asm.c: New file | |
515 | * xc16x-dis.c: New file | |
516 | * Makefile.am: Entries for xc16x | |
517 | * Makefile.in: Regenerate | |
518 | * cofigure.in: Add xc16x target information. | |
519 | * configure: Regenerate. | |
520 | * disassemble.c: Add xc16x target information. | |
521 | ||
a1cfb73e L |
522 | 2006-02-11 H.J. Lu <hongjiu.lu@intel.com> |
523 | ||
524 | * i386-dis.c (dis386_twobyte): Use "movZ" for debug register | |
525 | moves. | |
526 | ||
6dd5059a L |
527 | 2006-02-11 H.J. Lu <hongjiu.lu@intel.com> |
528 | ||
529 | * i386-dis.c ('Z'): Add a new macro. | |
530 | (dis386_twobyte): Use "movZ" for control register moves. | |
531 | ||
8536c657 NC |
532 | 2006-02-10 Nick Clifton <nickc@redhat.com> |
533 | ||
534 | * iq2000-asm.c: Regenerate. | |
535 | ||
266abb8f NS |
536 | 2006-02-07 Nathan Sidwell <nathan@codesourcery.com> |
537 | ||
538 | * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features. | |
539 | ||
f1a64f49 DU |
540 | 2006-01-26 David Ung <davidu@mips.com> |
541 | ||
542 | * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx, | |
543 | ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d, | |
544 | floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d, | |
545 | nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d, | |
546 | rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s. | |
547 | ||
9e919b5f AM |
548 | 2006-01-18 Arnold Metselaar <arnoldm@sourceware.org> |
549 | ||
550 | * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d, | |
551 | ld_d_r, pref_xd_cb): Use signed char to hold data to be | |
552 | disassembled. | |
553 | * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes | |
554 | buffer overflows when disassembling instructions like | |
555 | ld (ix+123),0x23 | |
556 | * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed | |
557 | operand, if the offset is negative. | |
558 | ||
c9021189 AM |
559 | 2006-01-17 Arnold Metselaar <arnoldm@sourceware.org> |
560 | ||
561 | * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use | |
562 | unsigned char to hold data to be disassembled. | |
563 | ||
d99b6465 AS |
564 | 2006-01-17 Andreas Schwab <schwab@suse.de> |
565 | ||
566 | PR binutils/1486 | |
567 | * disassemble.c (disassemble_init_for_target): Set | |
568 | disassembler_needs_relocs for bfd_arch_arm. | |
569 | ||
c2fe9327 PB |
570 | 2006-01-16 Paul Brook <paul@codesourcery.com> |
571 | ||
e88d958a | 572 | * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss, |
c2fe9327 PB |
573 | f?add?, and f?sub? instructions. |
574 | ||
32fba81d NC |
575 | 2006-01-16 Nick Clifton <nickc@redhat.com> |
576 | ||
577 | * po/zh_CN.po: New Chinese (simplified) translation. | |
578 | * configure.in (ALL_LINGUAS): Add "zh_CH". | |
579 | * configure: Regenerate. | |
580 | ||
1b3a26b5 PB |
581 | 2006-01-05 Paul Brook <paul@codesourcery.com> |
582 | ||
583 | * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry. | |
584 | ||
db313fa6 DD |
585 | 2006-01-06 DJ Delorie <dj@redhat.com> |
586 | ||
587 | * m32c-desc.c: Regenerate. | |
588 | * m32c-opc.c: Regenerate. | |
589 | * m32c-opc.h: Regenerate. | |
590 | ||
54d46aca DD |
591 | 2006-01-03 DJ Delorie <dj@redhat.com> |
592 | ||
593 | * cgen-ibld.in (extract_normal): Avoid memory range errors. | |
594 | * m32c-ibld.c: Regenerated. | |
595 | ||
e88d958a | 596 | For older changes see ChangeLog-2005 |
252b5132 RH |
597 | \f |
598 | Local Variables: | |
2f6d2f85 NC |
599 | mode: change-log |
600 | left-margin: 8 | |
601 | fill-column: 74 | |
252b5132 RH |
602 | version-control: never |
603 | End: |