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[AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
8eab4136
L		 12015-12-09 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-dis.c (MOD_0F01_REG_5): New.
4 (RM_0F01_REG_5): Likewise.
5 (reg_table): Use MOD_0F01_REG_5.
6 (mod_table): Add MOD_0F01_REG_5.
7 (rm_table): Add RM_0F01_REG_5.
8 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
9 (cpu_flags): Add CpuOSPKE.
10 * i386-opc.h (CpuOSPKE): New.
11 (i386_cpu_flags): Add cpuospke.
12 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
13 * i386-init.h: Regenerated.
14 * i386-tbl.h: Likewise.
15
1eac08cc
DD		 162015-12-07 DJ Delorie <dj@redhat.com>
17
18 * rl78-decode.opc: Enable MULU for all ISAs.
19 * rl78-decode.c: Regenerate.
20
dd2887fc
AM		 212015-12-07 Alan Modra <amodra@gmail.com>
22
23 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
24 major opcode/xop.
25
24b368f8
CZ		 262015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
27
28 * arc-dis.c (special_flag_p): Match full mnemonic.
29 * arc-opc.c (print_insn_arc): Check section size to read
30 appropriate number of bytes. Fix printing.
31 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
32 arguments.
33
3395762e
AV		 342015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
35
36 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
37 <ldah>: ... to this.
38
622b9eb1
MW		 392015-11-27 Matthew Wahab <matthew.wahab@arm.com>
40
41 * aarch64-asm-2.c: Regenerate.
42 * aarch64-dis-2.c: Regenerate.
43 * aarch64-opc-2.c: Regenerate.
44 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
45 (QL_INT2FP_H, QL_FP2INT_H): New.
46 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
47 (QL_DST_H): New.
48 (QL_FCCMP_H): New.
49 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
50 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
51 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
52 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
53 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
54 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
55 fcsel.
56
cf86120b
MW		 572015-11-27 Matthew Wahab <matthew.wahab@arm.com>
58
59 * aarch64-opc.c (half_conv_t): New.
60 (expand_fp_imm): Replace is_dp flag with the parameter size to
61 specify the number of bytes for the required expansion. Treat
62 a 16-bit expansion like a 32-bit expansion. Add check for an
63 unsupported size request. Update comment.
64 (aarch64_print_operand): Update to support 16-bit floating point
65 values. Update for changes to expand_fp_imm.
66
3bd894a7
MW		 672015-11-27 Matthew Wahab <matthew.wahab@arm.com>
68
69 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
70 (FP_F16): New.
71
64357d2e
MW		 722015-11-27 Matthew Wahab <matthew.wahab@arm.com>
73
74 * aarch64-asm-2.c: Regenerate.
75 * aarch64-dis-2.c: Regenerate.
76 * aarch64-opc-2.c: Regenerate.
77 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
78 "rev64".
79
d685192a
MW		 802015-11-27 Matthew Wahab <matthew.wahab@arm.com>
81
82 * aarch64-asm-2.c: Regenerate.
83 * aarch64-asm.c (convert_bfc_to_bfm): New.
84 (convert_to_real): Add case for OP_BFC.
85 * aarch64-dis-2.c: Regenerate.
86 * aarch64-dis.c: (convert_bfm_to_bfc): New.
87 (convert_to_alias): Add case for OP_BFC.
88 * aarch64-opc-2.c: Regenerate.
89 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
90 to allow width operand in three-operand instructions.
91 * aarch64-tbl.h (QL_BF1): New.
92 (aarch64_feature_v8_2): New.
93 (ARMV8_2): New.
94 (aarch64_opcode_table): Add "bfc".
95
35822b38
MW		 962015-11-27 Matthew Wahab <matthew.wahab@arm.com>
97
98 * aarch64-asm-2.c: Regenerate.
99 * aarch64-dis-2.c: Regenerate.
100 * aarch64-dis.c: Weaken assert.
101 * aarch64-gen.c: Include the instruction in the list of its
102 possible aliases.
103
1a04d1a7
MW		 1042015-11-27 Matthew Wahab <matthew.wahab@arm.com>
105
106 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
107 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
108 feature test.
109
e49d43ff
TG		 1102015-11-23 Tristan Gingold <gingold@adacore.com>
111
112 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
113
250aafa4
MW		 1142015-11-20 Matthew Wahab <matthew.wahab@arm.com>
115
116 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
117 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
118 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
119 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
120 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
121 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
122 cnthv_ctl_el2, cnthv_cval_el2.
123 (aarch64_sys_reg_supported_p): Update for the new system
124 registers.
125
a915c10f
NC		 1262015-11-20 Nick Clifton <nickc@redhat.com>
127
128 PR binutils/19224
129 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
130
f8c2a965
NC		 1312015-11-20 Nick Clifton <nickc@redhat.com>
132
133 * po/zh_CN.po: Updated simplified Chinese translation.
134
c2825638
MW		 1352015-11-19 Matthew Wahab <matthew.wahab@arm.com>
136
137 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
138 of MSR PAN immediate operand.
139
e7286c56
NC		 1402015-11-16 Nick Clifton <nickc@redhat.com>
141
142 * rx-dis.c (condition_names): Replace always and never with
143 invalid, since the always/never conditions can never be legal.
144
d8bd95ef
TG		 1452015-11-13 Tristan Gingold <gingold@adacore.com>
146
147 * configure: Regenerate.
148
a680de9a
PB		 1492015-11-11 Alan Modra <amodra@gmail.com>
150 Peter Bergner <bergner@vnet.ibm.com>
151
152 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
153 Add PPC_OPCODE_VSX3 to the vsx entry.
154 (powerpc_init_dialect): Set default dialect to power9.
155 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
156 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
157 extract_l1 insert_xtq6, extract_xtq6): New static functions.
158 (insert_esync): Test for illegal L operand value.
159 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
160 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
161 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
162 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
163 PPCVSX3): New defines.
164 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
165 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
166 <mcrxr>: Use XBFRARB_MASK.
167 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
168 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
169 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
170 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
171 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
172 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
173 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
174 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
175 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
176 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
177 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
178 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
179 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
180 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
181 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
182 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
183 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
184 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
185 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
186 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
187 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
188 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
189 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
190 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
191 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
192 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
193 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
194 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
195 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
196 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
197 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
198 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
199
854eb72b
NC		 2002015-11-02 Nick Clifton <nickc@redhat.com>
201
202 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
203 instructions.
204 * rx-decode.c: Regenerate.
205
e292aa7a
NC		 2062015-11-02 Nick Clifton <nickc@redhat.com>
207
208 * rx-decode.opc (rx_disp): If the displacement is zero, set the
209 type to RX_Operand_Zero_Indirect.
210 * rx-decode.c: Regenerate.
211 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
212
43cdf5ae
YQ		 2132015-10-28 Yao Qi <yao.qi@linaro.org>
214
215 * aarch64-dis.c (aarch64_decode_insn): Add one argument
216 noaliases_p. Update comments. Pass noaliases_p rather than
217 no_aliases to aarch64_opcode_decode.
218 (print_insn_aarch64_word): Pass no_aliases to
219 aarch64_decode_insn.
220
c2f28758
VK		 2212015-10-27 Vinay <Vinay.G@kpit.com>
222
223 PR binutils/19159
224 * rl78-decode.opc (MOV): Added offset to DE register in index
225 addressing mode.
226 * rl78-decode.c: Regenerate.
227
46662804
VK		 2282015-10-27 Vinay Kumar <vinay.g@kpit.com>
229
230 PR binutils/19158
231 * rl78-decode.opc: Add 's' print operator to instructions that
232 access system registers.
233 * rl78-decode.c: Regenerate.
234 * rl78-dis.c (print_insn_rl78_common): Decode all system
235 registers.
236
02f12cd4
VK		 2372015-10-27 Vinay Kumar <vinay.g@kpit.com>
238
239 PR binutils/19157
240 * rl78-decode.opc: Add 'a' print operator to mov instructions
241 using stack pointer plus index addressing.
242 * rl78-decode.c: Regenerate.
243
485f23cf
AK		 2442015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
245
246 * s390-opc.c: Fix comment.
247 * s390-opc.txt: Change instruction type for troo, trot, trto, and
248 trtt to RRF_U0RER since the second parameter does not need to be a
249 register pair.
250
3f94e60d
NC		 2512015-10-08 Nick Clifton <nickc@redhat.com>
252
253 * arc-dis.c (print_insn_arc): Initiallise insn array.
254
875880c6
YQ		 2552015-10-07 Yao Qi <yao.qi@linaro.org>
256
257 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
258 'name' rather than 'template'.
259 * aarch64-opc.c (aarch64_print_operand): Likewise.
260
886a2506
NC		 2612015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
262
263 * arc-dis.c: Revamped file for ARC support
264 * arc-dis.h: Likewise.
265 * arc-ext.c: Likewise.
266 * arc-ext.h: Likewise.
267 * arc-opc.c: Likewise.
268 * arc-fxi.h: New file.
269 * arc-regs.h: Likewise.
270 * arc-tbl.h: Likewise.
271
36f4aab1
YQ		 2722015-10-02 Yao Qi <yao.qi@linaro.org>
273
274 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
275 argument insn type to aarch64_insn. Rename to ...
276 (aarch64_decode_insn): ... it.
277 (print_insn_aarch64_word): Caller updated.
278
7232d389
YQ		 2792015-10-02 Yao Qi <yao.qi@linaro.org>
280
281 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
282 (print_insn_aarch64_word): Caller updated.
283
7ecc513a
DV		 2842015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
285
286 * s390-mkopc.c (main): Parse htm and vx flag.
287 * s390-opc.txt: Mark instructions from the hardware transactional
288 memory and vector facilities with the "htm"/"vx" flag.
289
b08b78e7
NC		 2902015-09-28 Nick Clifton <nickc@redhat.com>
291
292 * po/de.po: Updated German translation.
293
36f7a941
TR		 2942015-09-28 Tom Rix <tom@bumblecow.com>
295
296 * ppc-opc.c (PPC500): Mark some opcodes as invalid
297
b6518b38
NC		 2982015-09-23 Nick Clifton <nickc@redhat.com>
299
300 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
301 function.
302 * tic30-dis.c (print_branch): Likewise.
303 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
304 value before left shifting.
305 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
306 * hppa-dis.c (print_insn_hppa): Likewise.
307 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
308 array.
309 * msp430-dis.c (msp430_singleoperand): Likewise.
310 (msp430_doubleoperand): Likewise.
311 (print_insn_msp430): Likewise.
312 * nds32-asm.c (parse_operand): Likewise.
313 * sh-opc.h (MASK): Likewise.
314 * v850-dis.c (get_operand_value): Likewise.
315
f04265ec
NC		 3162015-09-22 Nick Clifton <nickc@redhat.com>
317
318 * rx-decode.opc (bwl): Use RX_Bad_Size.
319 (sbwl): Likewise.
320 (ubwl): Likewise. Rename to ubw.
321 (uBWL): Rename to uBW.
322 Replace all references to uBWL with uBW.
323 * rx-decode.c: Regenerate.
324 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
325 (opsize_names): Likewise.
326 (print_insn_rx): Detect and report RX_Bad_Size.
327
6dca4fd1
AB		 3282015-09-22 Anton Blanchard <anton@samba.org>
329
330 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
331
38074311
JM		 3322015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
333
334 * sparc-dis.c (print_insn_sparc): Handle the privileged register
335 %pmcdper.
336
5f40e14d
JS		 3372015-08-24 Jan Stancek <jstancek@redhat.com>
338
339 * i386-dis.c (print_insn): Fix decoding of three byte operands.
340
ab4e4ed5
AF		 3412015-08-21 Alexander Fomin <alexander.fomin@intel.com>
342
343 PR binutils/18257
344 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
345 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
346 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
347 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
348 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
349 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
350 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
351 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
352 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
353 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
354 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
355 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
356 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
357 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
358 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
359 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
360 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
361 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
362 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
363 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
364 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
365 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
366 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
367 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
368 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
369 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
370 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
371 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
372 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
373 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
374 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
375 (vex_w_table): Replace terminals with MOD_TABLE entries for
376 most of mask instructions.
377
919b75f7
AM		 3782015-08-17 Alan Modra <amodra@gmail.com>
379
380 * cgen.sh: Trim trailing space from cgen output.
381 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
382 (print_dis_table): Likewise.
383 * opc2c.c (dump_lines): Likewise.
384 (orig_filename): Warning fix.
385 * ia64-asmtab.c: Regenerate.
386
4ab90a7a
AV		 3872015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
388
389 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
390 and higher with ARM instruction set will now mark the 26-bit
391 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
392 (arm_opcodes): Fix for unpredictable nop being recognized as a
393 teq.
394
40fc1451
SD		 3952015-08-12 Simon Dardis <simon.dardis@imgtec.com>
396
397 * micromips-opc.c (micromips_opcodes): Re-order table so that move
398 based on 'or' is first.
399 * mips-opc.c (mips_builtin_opcodes): Ditto.
400
922c5db5
NC		 4012015-08-11 Nick Clifton <nickc@redhat.com>
402
403 PR 18800
404 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
405 instruction.
406
75fb7498
RS		 4072015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
408
409 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
410
36aed29d
AP		 4112015-08-07 Amit Pawar <Amit.Pawar@amd.com>
412
413 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
414 * i386-init.h: Regenerated.
415
a8484f96
L		 4162015-07-30 H.J. Lu <hongjiu.lu@intel.com>
417
418 PR binutils/13571
419 * i386-dis.c (MOD_0FC3): New.
420 (PREFIX_0FC3): Renamed to ...
421 (PREFIX_MOD_0_0FC3): This.
422 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
423 (prefix_table): Replace Ma with Ev on movntiS.
424 (mod_table): Add MOD_0FC3.
425
37a42ee9
L		 4262015-07-27 H.J. Lu <hongjiu.lu@intel.com>
427
428 * configure: Regenerated.
429
070fe95d
AM		 4302015-07-23 Alan Modra <amodra@gmail.com>
431
432 PR 18708
433 * i386-dis.c (get64): Avoid signed integer overflow.
434
20c2a615
L		 4352015-07-22 Alexander Fomin <alexander.fomin@intel.com>
436
437 PR binutils/18631
438 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
439 "EXEvexHalfBcstXmmq" for the second operand.
440 (EVEX_W_0F79_P_2): Likewise.
441 (EVEX_W_0F7A_P_2): Likewise.
442 (EVEX_W_0F7B_P_2): Likewise.
443
6f1c2142
AM		 4442015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
445
446 * arm-dis.c (print_insn_coprocessor): Added support for quarter
447 float bitfield format.
448 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
449 quarter float bitfield format.
450
8a643cc3
L		 4512015-07-14 H.J. Lu <hongjiu.lu@intel.com>
452
453 * configure: Regenerated.
454
ef5a96d5
AM		 4552015-07-03 Alan Modra <amodra@gmail.com>
456
457 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
458 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
459 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
460
c8c8175b
SL		 4612015-07-01 Sandra Loosemore <sandra@codesourcery.com>
462 Cesar Philippidis <cesar@codesourcery.com>
463
464 * nios2-dis.c (nios2_extract_opcode): New.
465 (nios2_disassembler_state): New.
466 (nios2_find_opcode_hash): Use mach parameter to select correct
467 disassembler state.
468 (nios2_print_insn_arg): Extend to support new R2 argument letters
469 and formats.
470 (print_insn_nios2): Check for 16-bit instruction at end of memory.
471 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
472 (NIOS2_NUM_OPCODES): Rename to...
473 (NIOS2_NUM_R1_OPCODES): This.
474 (nios2_r2_opcodes): New.
475 (NIOS2_NUM_R2_OPCODES): New.
476 (nios2_num_r2_opcodes): New.
477 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
478 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
479 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
480 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
481 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
482
9916071f
AP		 4832015-06-30 Amit Pawar <Amit.Pawar@amd.com>
484
485 * i386-dis.c (OP_Mwaitx): New.
486 (rm_table): Add monitorx/mwaitx.
487 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
488 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
489 (operand_type_init): Add CpuMWAITX.
490 * i386-opc.h (CpuMWAITX): New.
491 (i386_cpu_flags): Add cpumwaitx.
492 * i386-opc.tbl: Add monitorx and mwaitx.
493 * i386-init.h: Regenerated.
494 * i386-tbl.h: Likewise.
495
7b934113
PB		 4962015-06-22 Peter Bergner <bergner@vnet.ibm.com>
497
498 * ppc-opc.c (insert_ls): Test for invalid LS operands.
499 (insert_esync): New function.
500 (LS, WC): Use insert_ls.
501 (ESYNC): Use insert_esync.
502
bdc4de1b
NC		 5032015-06-22 Nick Clifton <nickc@redhat.com>
504
505 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
506 requested region lies beyond it.
507 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
508 looking for 32-bit insns.
509 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
510 data.
511 * sh-dis.c (print_insn_sh): Likewise.
512 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
513 blocks of instructions.
514 * vax-dis.c (print_insn_vax): Check that the requested address
515 does not clash with the stop_vma.
516
11a0cf2e
PB		 5172015-06-19 Peter Bergner <bergner@vnet.ibm.com>
518
070fe95d 519 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 520 * ppc-opc.c (FXM4): Add non-zero optional value.
521 (TBR): Likewise.
522 (SXL): Likewise.
523 (insert_fxm): Handle new default operand value.
524 (extract_fxm): Likewise.
525 (insert_tbr): Likewise.
526 (extract_tbr): Likewise.
527
bdfa8b95
MW		 5282015-06-16 Matthew Wahab <matthew.wahab@arm.com>
529
530 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
531
24b4cf66
SN		 5322015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
533
534 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
535
99a2c561
PB		 5362015-06-12 Peter Bergner <bergner@vnet.ibm.com>
537
538 * ppc-opc.c: Add comment accidentally removed by old commit.
539 (MTMSRD_L): Delete.
540
40f77f82
AM		 5412015-06-04 Peter Bergner <bergner@vnet.ibm.com>
542
543 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
544
13be46a2
NC		 5452015-06-04 Nick Clifton <nickc@redhat.com>
546
547 PR 18474
548 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
549
ddfded2f
MW		 5502015-06-02 Matthew Wahab <matthew.wahab@arm.com>
551
552 * arm-dis.c (arm_opcodes): Add "setpan".
553 (thumb_opcodes): Add "setpan".
554
1af1dd51
MW		 5552015-06-02 Matthew Wahab <matthew.wahab@arm.com>
556
557 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
558 macros.
559
9e1f0fa7
MW		 5602015-06-02 Matthew Wahab <matthew.wahab@arm.com>
561
562 * aarch64-tbl.h (aarch64_feature_rdma): New.
563 (RDMA): New.
564 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
565 * aarch64-asm-2.c: Regenerate.
566 * aarch64-dis-2.c: Regenerate.
567 * aarch64-opc-2.c: Regenerate.
568
290806fd
MW		 5692015-06-02 Matthew Wahab <matthew.wahab@arm.com>
570
571 * aarch64-tbl.h (aarch64_feature_lor): New.
572 (LOR): New.
573 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
574 "stllrb", "stllrh".
575 * aarch64-asm-2.c: Regenerate.
576 * aarch64-dis-2.c: Regenerate.
577 * aarch64-opc-2.c: Regenerate.
578
f21cce2c
MW		 5792015-06-01 Matthew Wahab <matthew.wahab@arm.com>
580
581 * aarch64-opc.c (F_ARCHEXT): New.
582 (aarch64_sys_regs): Add "pan".
583 (aarch64_sys_reg_supported_p): New.
584 (aarch64_pstatefields): Add "pan".
585 (aarch64_pstatefield_supported_p): New.
586
d194d186
JB		 5872015-06-01 Jan Beulich <jbeulich@suse.com>
588
589 * i386-tbl.h: Regenerate.
590
3a8547d2
JB		 5912015-06-01 Jan Beulich <jbeulich@suse.com>
592
593 * i386-dis.c (print_insn): Swap rounding mode specifier and
594 general purpose register in Intel mode.
595
015c54d5
JB		 5962015-06-01 Jan Beulich <jbeulich@suse.com>
597
598 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
599 * i386-tbl.h: Regenerate.
600
071f0063
L		 6012015-05-18 H.J. Lu <hongjiu.lu@intel.com>
602
603 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
604 * i386-init.h: Regenerated.
605
5db04b09
L		 6062015-05-15 H.J. Lu <hongjiu.lu@intel.com>
607
608 PR binutis/18386
609 * i386-dis.c: Add comments for '@'.
610 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
611 (enum x86_64_isa): New.
612 (isa64): Likewise.
613 (print_i386_disassembler_options): Add amd64 and intel64.
614 (print_insn): Handle amd64 and intel64.
615 (putop): Handle '@'.
616 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
617 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
618 * i386-opc.h (AMD64): New.
619 (CpuIntel64): Likewise.
620 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
621 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
622 Mark direct call/jmp without Disp16|Disp32 as Intel64.
623 * i386-init.h: Regenerated.
624 * i386-tbl.h: Likewise.
625
4bc0608a
PB		 6262015-05-14 Peter Bergner <bergner@vnet.ibm.com>
627
628 * ppc-opc.c (IH) New define.
629 (powerpc_opcodes) <wait>: Do not enable for POWER7.
630 <tlbie>: Add RS operand for POWER7.
631 <slbia>: Add IH operand for POWER6.
632
70cead07
L		 6332015-05-11 H.J. Lu <hongjiu.lu@intel.com>
634
635 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
636 direct branch.
637 (jmp): Likewise.
638 * i386-tbl.h: Regenerated.
639
7b6d09fb
L		 6402015-05-11 H.J. Lu <hongjiu.lu@intel.com>
641
642 * configure.ac: Support bfd_iamcu_arch.
643 * disassemble.c (disassembler): Support bfd_iamcu_arch.
644 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
645 CPU_IAMCU_COMPAT_FLAGS.
646 (cpu_flags): Add CpuIAMCU.
647 * i386-opc.h (CpuIAMCU): New.
648 (i386_cpu_flags): Add cpuiamcu.
649 * configure: Regenerated.
650 * i386-init.h: Likewise.
651 * i386-tbl.h: Likewise.
652
31955f99
L		 6532015-05-08 H.J. Lu <hongjiu.lu@intel.com>
654
655 PR binutis/18386
656 * i386-dis.c (X86_64_E8): New.
657 (X86_64_E9): Likewise.
658 Update comments on 'T', 'U', 'V'. Add comments for '^'.
659 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
660 (x86_64_table): Add X86_64_E8 and X86_64_E9.
661 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
662 (putop): Handle '^'.
663 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
664 REX_W.
665
0952813b
DD		 6662015-04-30 DJ Delorie <dj@redhat.com>
667
668 * disassemble.c (disassembler): Choose suitable disassembler based
669 on E_ABI.
670 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
671 it to decode mul/div insns.
672 * rl78-decode.c: Regenerate.
673 * rl78-dis.c (print_insn_rl78): Rename to...
674 (print_insn_rl78_common): ...this, take ISA parameter.
675 (print_insn_rl78): New.
676 (print_insn_rl78_g10): New.
677 (print_insn_rl78_g13): New.
678 (print_insn_rl78_g14): New.
679 (rl78_get_disassembler): New.
680
f9d3ecaa
NC		 6812015-04-29 Nick Clifton <nickc@redhat.com>
682
683 * po/fr.po: Updated French translation.
684
4fff86c5
PB		 6852015-04-27 Peter Bergner <bergner@vnet.ibm.com>
686
687 * ppc-opc.c (DCBT_EO): New define.
688 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
689 <lharx>: Likewise.
690 <stbcx.>: Likewise.
691 <sthcx.>: Likewise.
692 <waitrsv>: Do not enable for POWER7 and later.
693 <waitimpl>: Likewise.
694 <dcbt>: Default to the two operand form of the instruction for all
695 "old" cpus. For "new" cpus, use the operand ordering that matches
696 whether the cpu is server or embedded.
697 <dcbtst>: Likewise.
698
3b78cfe1
AK		 6992015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
700
701 * s390-opc.c: New instruction type VV0UU2.
702 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
703 and WFC.
704
04d824a4
JB		 7052015-04-23 Jan Beulich <jbeulich@suse.com>
706
707 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
708 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
709 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
710 (vfpclasspd, vfpclassps): Add %XZ.
711
09708981
L		 7122015-04-15 H.J. Lu <hongjiu.lu@intel.com>
713
714 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
715 (PREFIX_UD_REPZ): Likewise.
716 (PREFIX_UD_REPNZ): Likewise.
717 (PREFIX_UD_DATA): Likewise.
718 (PREFIX_UD_ADDR): Likewise.
719 (PREFIX_UD_LOCK): Likewise.
720
3888916d
L		 7212015-04-15 H.J. Lu <hongjiu.lu@intel.com>
722
723 * i386-dis.c (prefix_requirement): Removed.
724 (print_insn): Don't set prefix_requirement. Check
725 dp->prefix_requirement instead of prefix_requirement.
726
f24bcbaa
L		 7272015-04-15 H.J. Lu <hongjiu.lu@intel.com>
728
729 PR binutils/17898
730 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
731 (PREFIX_MOD_0_0FC7_REG_6): This.
732 (PREFIX_MOD_3_0FC7_REG_6): New.
733 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
734 (prefix_table): Replace PREFIX_0FC7_REG_6 with
735 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
736 PREFIX_MOD_3_0FC7_REG_7.
737 (mod_table): Replace PREFIX_0FC7_REG_6 with
738 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
739 PREFIX_MOD_3_0FC7_REG_7.
740
507bd325
L		 7412015-04-15 H.J. Lu <hongjiu.lu@intel.com>
742
743 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
744 (PREFIX_MANDATORY_REPNZ): Likewise.
745 (PREFIX_MANDATORY_DATA): Likewise.
746 (PREFIX_MANDATORY_ADDR): Likewise.
747 (PREFIX_MANDATORY_LOCK): Likewise.
748 (PREFIX_MANDATORY): Likewise.
749 (PREFIX_UD_SHIFT): Set to 8
750 (PREFIX_UD_REPZ): Updated.
751 (PREFIX_UD_REPNZ): Likewise.
752 (PREFIX_UD_DATA): Likewise.
753 (PREFIX_UD_ADDR): Likewise.
754 (PREFIX_UD_LOCK): Likewise.
755 (PREFIX_IGNORED_SHIFT): New.
756 (PREFIX_IGNORED_REPZ): Likewise.
757 (PREFIX_IGNORED_REPNZ): Likewise.
758 (PREFIX_IGNORED_DATA): Likewise.
759 (PREFIX_IGNORED_ADDR): Likewise.
760 (PREFIX_IGNORED_LOCK): Likewise.
761 (PREFIX_OPCODE): Likewise.
762 (PREFIX_IGNORED): Likewise.
763 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
764 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
765 (three_byte_table): Likewise.
766 (mod_table): Likewise.
767 (mandatory_prefix): Renamed to ...
768 (prefix_requirement): This.
769 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
770 Update PREFIX_90 entry.
771 (get_valid_dis386): Check prefix_requirement to see if a prefix
772 should be ignored.
773 (print_insn): Replace mandatory_prefix with prefix_requirement.
774
f0fba320
RL		 7752015-04-15 Renlin Li <renlin.li@arm.com>
776
777 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
778 use it for ssat and ssat16.
779 (print_insn_thumb32): Add handle case for 'D' control code.
780
bf890a93
IT		 7812015-04-06 Ilya Tocar <ilya.tocar@intel.com>
782 H.J. Lu <hongjiu.lu@intel.com>
783
784 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
785 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
786 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
787 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
788 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
789 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
790 Fill prefix_requirement field.
791 (struct dis386): Add prefix_requirement field.
792 (dis386): Fill prefix_requirement field.
793 (dis386_twobyte): Ditto.
794 (twobyte_has_mandatory_prefix_: Remove.
795 (reg_table): Fill prefix_requirement field.
796 (prefix_table): Ditto.
797 (x86_64_table): Ditto.
798 (three_byte_table): Ditto.
799 (xop_table): Ditto.
800 (vex_table): Ditto.
801 (vex_len_table): Ditto.
802 (vex_w_table): Ditto.
803 (mod_table): Ditto.
804 (bad_opcode): Ditto.
805 (print_insn): Use prefix_requirement.
806 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
807 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
808 (float_reg): Ditto.
809
2f783c1f
MF		 8102015-03-30 Mike Frysinger <vapier@gentoo.org>
811
812 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
813
b9d94d62
L		 8142015-03-29 H.J. Lu <hongjiu.lu@intel.com>
815
816 * Makefile.in: Regenerated.
817
27c49e9a
AB		 8182015-03-25 Anton Blanchard <anton@samba.org>
819
820 * ppc-dis.c (disassemble_init_powerpc): Only initialise
821 powerpc_opcd_indices and vle_opcd_indices once.
822
c4e676f1
AB		 8232015-03-25 Anton Blanchard <anton@samba.org>
824
825 * ppc-opc.c (powerpc_opcodes): Add slbfee.
826
823d2571
TG		 8272015-03-24 Terry Guo <terry.guo@arm.com>
828
829 * arm-dis.c (opcode32): Updated to use new arm feature struct.
830 (opcode16): Likewise.
831 (coprocessor_opcodes): Replace bit with feature struct.
832 (neon_opcodes): Likewise.
833 (arm_opcodes): Likewise.
834 (thumb_opcodes): Likewise.
835 (thumb32_opcodes): Likewise.
836 (print_insn_coprocessor): Likewise.
837 (print_insn_arm): Likewise.
838 (select_arm_features): Follow new feature struct.
839
029f3522
GG		 8402015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
841
842 * i386-dis.c (rm_table): Add clzero.
843 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
844 Add CPU_CLZERO_FLAGS.
845 (cpu_flags): Add CpuCLZERO.
846 * i386-opc.h: Add CpuCLZERO.
847 * i386-opc.tbl: Add clzero.
848 * i386-init.h: Re-generated.
849 * i386-tbl.h: Re-generated.
850
6914869a
AB		 8512015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
852
853 * mips-opc.c (decode_mips_operand): Fix constraint issues
854 with u and y operands.
855
21e20815
AB		 8562015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
857
858 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
859
6b1d7593
AK		 8602015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
861
862 * s390-opc.c: Add new IBM z13 instructions.
863 * s390-opc.txt: Likewise.
864
c8f89a34
JW		 8652015-03-10 Renlin Li <renlin.li@arm.com>
866
867 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
868 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
869 related alias.
870 * aarch64-asm-2.c: Regenerate.
871 * aarch64-dis-2.c: Likewise.
872 * aarch64-opc-2.c: Likewise.
873
d8282f0e
JW		 8742015-03-03 Jiong Wang <jiong.wang@arm.com>
875
876 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
877
ac994365
OE		 8782015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
879
880 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
881 arch_sh_up.
882 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
883 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
884
fd63f640
V		 8852015-02-23 Vinay <Vinay.G@kpit.com>
886
887 * rl78-decode.opc (MOV): Added space between two operands for
888 'mov' instruction in index addressing mode.
889 * rl78-decode.c: Regenerate.
890
f63c1776
PA		 8912015-02-19 Pedro Alves <palves@redhat.com>
892
893 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
894
07774fcc
PA		 8952015-02-10 Pedro Alves <palves@redhat.com>
896 Tom Tromey <tromey@redhat.com>
897
898 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
899 microblaze_and, microblaze_xor.
900 * microblaze-opc.h (opcodes): Adjust.
901
3f8107ab
AM		 9022015-01-28 James Bowman <james.bowman@ftdichip.com>
903
904 * Makefile.am: Add FT32 files.
905 * configure.ac: Handle FT32.
906 * disassemble.c (disassembler): Call print_insn_ft32.
907 * ft32-dis.c: New file.
908 * ft32-opc.c: New file.
909 * Makefile.in: Regenerate.
910 * configure: Regenerate.
911 * po/POTFILES.in: Regenerate.
912
e5fe4957
KLC		 9132015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
914
915 * nds32-asm.c (keyword_sr): Add new system registers.
916
1e2e8c52
AK		 9172015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
918
919 * s390-dis.c (s390_extract_operand): Support vector register
920 operands.
921 (s390_print_insn_with_opcode): Support new operands types and add
922 new handling of optional operands.
923 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
924 and include opcode/s390.h instead.
925 (struct op_struct): New field `flags'.
926 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
927 (dumpTable): Dump flags.
928 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
929 string.
930 * s390-opc.c: Add new operands types, instruction formats, and
931 instruction masks.
932 (s390_opformats): Add new formats for .insn.
933 * s390-opc.txt: Add new instructions.
934
b90efa5b 9352015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 936
b90efa5b 937 Update year range in copyright notice of all files.
bffb6004 938
b90efa5b 939For older changes see ChangeLog-2014
252b5132 940\f
b90efa5b 941Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 942
943Copying and distribution of this file, with or without modification,
944are permitted in any medium without royalty provided the copyright
945notice and this notice are preserved.
946
252b5132 947Local Variables:
2f6d2f85
NC		 948mode: change-log
949left-margin: 8
950fill-column: 74
252b5132
RH		 951version-control: never
952End:
GDB Binutils - Deliverables
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