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* mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
af478898
MR		 12010-10-28 Maciej W. Rozycki <macro@codesourcery.com>
2
3 * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".
4
be7a250d
AK		 52010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
6
7 * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
8
d958d1a3
CF		 92010-10-25 Chao-ying Fu <fu@mips.com>
10
11 * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
12
c0621d88
NS		 132010-10-25 Nathan Sidwell <nathan@codesourcery.com>
14
15 * tic6x-dis.c: Add attribution.
16
a43817df
AM		 172010-10-22 Alan Modra <amodra@gmail.com>
18
19 * Makefile.am (CLEANFILES): Add stamp-lm32. Sort.
20 * Makefile.in: Regenerate.
21
704897fb
MR		 222010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
23
24 * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
25 macros before their corresponding MIPS III hardware instructions.
26
da98bb4c
L		 272010-10-16 H.J. Lu <hongjiu.lu@intel.com>
28
29 * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
30
31 * i386-init.h: Regenerated.
32
e1791cb8
MF		 332010-10-15 Mike Frysinger <vapier@gentoo.org>
34
35 * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M.
36
553d0a74
L		 372010-10-14 H.J. Lu <hongjiu.lu@intel.com>
38
39 * i386-opc.tbl: Remove CheckRegSize from movq.
40 * i386-tbl.h: Regenerated.
41
cfc08d49
L		 422010-10-14 H.J. Lu <hongjiu.lu@intel.com>
43
44 * i386-opc.tbl: Remove CheckRegSize from instructions with
45 0, 1 or fixed operands.
46 * i386-tbl.h: Regenerated.
47
56ffb741
L		 482010-10-14 H.J. Lu <hongjiu.lu@intel.com>
49
50 * i386-gen.c (opcode_modifiers): Add CheckRegSize.
51
52 * i386-opc.h (CheckRegSize): New.
53 (i386_opcode_modifier): Add checkregsize.
54
55 * i386-opc.tbl: Add CheckRegSize to instructions which
56 require register size check.
57 * i386-tbl.h: Regenerated.
58
1a2dab1f
AS		 592010-10-12 Andreas Schwab <schwab@linux-m68k.org>
60
61 * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
62
a3ec2691
AK		 632010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
64
65 * s390-opc.c: Make the instruction masks for the load/store on
66 condition instructions to cover the condition code mask as well.
67 * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
68
d92fa646
JK		 692010-10-11 Jan Kratochvil <jan.kratochvil@redhat.com>
70 Jiang Jilin <freephp@gmail.com>
71
72 * Makefile.am (libopcodes_a_SOURCES): New as empty.
73 * Makefile.in: Regenerate.
74
4469d2be
AM		 752010-10-09 Matt Rice <ratmice@gmail.com>
76
77 * fr30-desc.h: Regenerate.
78 * frv-desc.h: Regenerate.
79 * ip2k-desc.h: Regenerate.
80 * iq2000-desc.h: Regenerate.
81 * lm32-desc.h: Regenerate.
82 * m32c-desc.h: Regenerate.
83 * m32r-desc.h: Regenerate.
84 * mep-desc.h: Regenerate.
85 * mep-opc.c: Regenerate.
86 * mt-desc.h: Regenerate.
87 * openrisc-desc.h: Regenerate.
88 * xc16x-desc.h: Regenerate.
89 * xstormy16-desc.h: Regenerate.
90
9ccb8af9
AM		 912010-10-08 Pierre Muller <muller@ics.u-strasbg.fr>
92
93 Fix build with -DDEBUG=7
94 * frv-opc.c: Regenerate.
95 * or32-dis.c (DEBUG): Don't redefine.
96 (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
97 Adapt DEBUG code to some type changes throughout.
98 * or32-opc.c (or32_extract): Likewise.
99
5d4c71e1
BS		 1002010-10-07 Bernd Schmidt <bernds@codesourcery.com>
101
102 * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
103 in SPKERNEL instructions.
104
9ce00134
L		 1052010-10-02 H.J. Lu <hongjiu.lu@intel.com>
106
107 PR binutils/12076
108 * i386-dis.c (RMAL): Remove duplicate.
109
e7390eec
PM		 1102010-09-30 Pierre Muller <muller@ics.u-strasbg.fr>
111
112 * s390-mkopc.c (main): Exit with error 1 if sscanf fails
113 to parse all 6 parameters.
114
d2ae9c84
PM		 1152010-09-28 Pierre Muller <muller@ics.u-strasbg.fr>
116
117 * s390-mkopc.c (main): Change description array size to 80.
118 Add maximum length of 79 to description parsing.
119
3cac54d2
RW		 1202010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
121
122 * configure: Regenerate.
123
d9aee5d7
AK		 1242010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
125
126 * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
127 (main): Recognize the new CPU string.
128 * s390-opc.c: Add new instruction formats and masks.
129 * s390-opc.txt: Add new z196 instructions.
130
02cbf767
AK		 1312010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
132
133 * s390-dis.c (print_insn_s390): Pick instruction with most
134 specific mask.
135 * s390-opc.c: Add unused bits to the insn mask.
136 * s390-opc.txt: Reorder some instructions to prefer more recent
137 versions.
138
6844b2c2
MGD		 1392010-09-27 Tejas Belagod <tejas.belagod@arm.com>
140
141 * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
142 correction to unaligned PCs while printing comment.
143
90ec0d68
MGD		 1442010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
145
146 * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
147 (thumb32_opcodes): Likewise.
148 (banked_regname): New function.
149 (print_insn_arm): Add Virtualization Extensions support.
150 (print_insn_thumb32): Likewise.
151
eea54501
MGD		 1522010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
153
154 * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
155 ARM state.
156
f4c65163
MGD		 1572010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
158
159 * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
160 (thumb32_opcodes): Likewise.
161
60e5ef9f
MGD		 1622010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
163
164 * arm-dis.c (arm_opcodes): Add support for pldw.
165 (thumb32_opcodes): Likewise.
166
7a360e83
MF		 1672010-09-22 Robin Getz <robin.getz@analog.com>
168
169 * bfin-dis.c (fmtconst): Cast address to 32bits.
170
35fc57f3
MF		 1712010-09-22 Mike Frysinger <vapier@gentoo.org>
172
173 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
174
219b747a
MF		 1752010-09-22 Robin Getz <robin.getz@analog.com>
176
177 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
178 Reject P6/P7 to TESTSET.
179 (decode_PushPopReg_0): Check for parallel insns. Reject pushing
180 SP onto the stack.
181 (decode_PushPopMultiple_0): Check for parallel insns. Make sure
182 P/D fields match all the time.
183 (decode_CCflag_0): Check for parallel insns. Verify x/y fields
184 are 0 for accumulator compares.
185 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
186 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
187 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
188 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
189 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
190 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
191 insns.
192 (decode_dagMODim_0): Verify br field for IREG ops.
193 (decode_LDST_0): Reject preg load into same preg.
194 (_print_insn_bfin): Handle returns for ILLEGAL decodes.
195 (print_insn_bfin): Likewise.
196
775f1cf0
MF		 1972010-09-22 Mike Frysinger <vapier@gentoo.org>
198
199 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
200
0b7691fd
MF		 2012010-09-22 Robin Getz <robin.getz@analog.com>
202
203 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
204
b2459327
MF		 2052010-09-22 Mike Frysinger <vapier@gentoo.org>
206
207 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
208
50e2162a
MF		 2092010-09-22 Robin Getz <robin.getz@analog.com>
210
211 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
212 register values greater than 8.
213 (IS_RESERVEDREG, allreg, mostreg): New helpers.
214 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
215 (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
216 (decode_CC2dreg_0): Check valid CC register number.
217
a01eda85
MF		 2182010-09-22 Robin Getz <robin.getz@analog.com>
219
220 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
221
22215ae0
MF		 2222010-09-22 Robin Getz <robin.getz@analog.com>
223
224 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
225 (reg_names): Likewise.
226 (decode_statbits): Likewise; while reformatting to make manageable.
227
73a63ccf
MF		 2282010-09-22 Mike Frysinger <vapier@gentoo.org>
229
230 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
231 (decode_pseudoOChar_0): New function.
232 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
233
59a82d23
MF		 2342010-09-22 Robin Getz <robin.getz@analog.com>
235
236 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
237 LSHIFT instead of SHIFT.
238
528c6277
MF		 2392010-09-22 Mike Frysinger <vapier@gentoo.org>
240
241 * bfin-dis.c (constant_formats): Constify the whole structure.
242 (fmtconst): Add const to return value.
243 (reg_names): Mark const.
244 (decode_multfunc): Mark s0/s1 as const.
245 (decode_macfunc): Mark a/sop as const.
246
db472d6f
MGD		 2472010-09-17 Tejas Belagod <tejas.belagod@arm.com>
248
249 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
250
f6690563
MR		 2512010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
252
253 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
254 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
255
8901a3cd
PM		 2562010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
257
258 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
259 dlx_insn_type array.
260
d9e3625e
L		 2612010-08-31 H.J. Lu <hongjiu.lu@intel.com>
262
263 PR binutils/11960
264 * i386-dis.c (sIv): New.
265 (dis386): Replace Iq with sIv on "pushT".
266 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
4469d2be 267 (x86_64_table): Replace {T|}/{P|} with P.
d9e3625e
L		 268 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
269 (OP_sI): Update v_mode. Remove w_mode.
270
f383de66
NF		 2712010-08-27 Nathan Froyd <froydnj@codesourcery.com>
272
273 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
274 on E500 and E500MC.
275
1ab03f4b
L		 2762010-08-17 H.J. Lu <hongjiu.lu@intel.com>
277
278 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
279 prefetchw.
280
22109423
L		 2812010-08-06 Quentin Neill <quentin.neill@amd.com>
282
283 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
284 to processor flags for PENTIUMPRO processors and later.
285 * i386-opc.h (enum): Add CpuNop.
286 (i386_cpu_flags): Add cpunop bit.
287 * i386-opc.tbl: Change nop cpu_flags.
288 * i386-init.h: Regenerated.
289 * i386-tbl.h: Likewise.
290
b49dfb4a
L		 2912010-08-06 Quentin Neill <quentin.neill@amd.com>
292
293 * i386-opc.h (enum): Fix typos in comments.
294
6ca4eb77
AM		 2952010-08-06 Alan Modra <amodra@gmail.com>
296
297 * disassemble.c: Formatting.
298 (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
299
92d4d42e
L		 3002010-08-05 H.J. Lu <hongjiu.lu@intel.com>
301
302 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
303 * i386-tbl.h: Regenerated.
304
b414985b
L		 3052010-08-05 H.J. Lu <hongjiu.lu@intel.com>
306
307 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
308
309 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
310 * i386-tbl.h: Regenerated.
311
f9c7014e
DD		 3122010-07-29 DJ Delorie <dj@redhat.com>
313
314 * rx-decode.opc (SRR): New.
315 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
316 r0,r0) and NOP3 (max r0,r0) special cases.
317 * rx-decode.c: Regenerate.
6ca4eb77 318
592a252b
L		 3192010-07-28 H.J. Lu <hongjiu.lu@intel.com>
320
321 * i386-dis.c: Add 0F to VEX opcode enums.
322
3cf79a01
DD		 3232010-07-27 DJ Delorie <dj@redhat.com>
324
325 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
326 (rx_decode_opcode): Likewise.
327 * rx-decode.c: Regenerate.
328
1cd986c5
NC		 3292010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
330 Ina Pandit <ina.pandit@kpitcummins.com>
331
332 * v850-dis.c (v850_sreg_names): Updated structure for system
333 registers.
334 (float_cc_names): new structure for condition codes.
335 (print_value): Update the function that prints value.
336 (get_operand_value): New function to get the operand value.
337 (disassemble): Updated to handle the disassembly of instructions.
338 (print_insn_v850): Updated function to print instruction for different
339 families.
340 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
341 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
342 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
343 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
344 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
345 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
346 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
347 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
348 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
349 (v850_operands): Update with the relocation name. Also update
350 the instructions with specific set of processors.
351
52e7f43d
RE		 3522010-07-08 Tejas Belagod <tejas.belagod@arm.com>
353
354 * arm-dis.c (print_insn_arm): Add cases for printing more
355 symbolic operands.
356 (print_insn_thumb32): Likewise.
357
c680e7f6
MR		 3582010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
359
360 * mips-dis.c (print_insn_mips): Correct branch instruction type
361 determination.
362
9a2c7088
MR		 3632010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
364
365 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
366 type and delay slot determination.
367 (print_insn_mips16): Extend branch instruction type and delay
368 slot determination to cover all instructions.
369 * mips16-opc.c (BR): Remove macro.
370 (UBR, CBR): New macros.
371 (mips16_opcodes): Update branch annotation for "b", "beqz",
372 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
373 and "jrc".
374
d7d9a9f8
L		 3752010-07-05 H.J. Lu <hongjiu.lu@intel.com>
376
377 AVX Programming Reference (June, 2010)
378 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
379 * i386-opc.tbl: Likewise.
380 * i386-tbl.h: Regenerated.
381
77321f53
L		 3822010-07-05 H.J. Lu <hongjiu.lu@intel.com>
383
384 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
385
7102e95e
AS		 3862010-07-03 Andreas Schwab <schwab@linux-m68k.org>
387
388 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
389 ppc_cpu_t before inverting.
3a5530ea
AS		 390 (ppc_parse_cpu): Likewise.
391 (print_insn_powerpc): Likewise.
7102e95e 392
bdc70b4a
AM		 3932010-07-03 Alan Modra <amodra@gmail.com>
394
395 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
396 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
397 (PPC64, MFDEC2): Update.
398 (NON32, NO371): Define.
399 (powerpc_opcode): Update to not use old opcode flags, and avoid
400 -m601 duplicates.
401
21375995
DD		 4022010-07-03 DJ Delorie <dj@delorie.com>
403
404 * m32c-ibld.c: Regenerate.
405
81a0b7e2
AM		 4062010-07-03 Alan Modra <amodra@gmail.com>
407
408 * ppc-opc.c (PWR2COM): Define.
409 (PPCPWR2): Add PPC_OPCODE_COMMON.
410 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
411 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
412 "rac" from -mcom.
413
c7b8aa3a
L		 4142010-07-01 H.J. Lu <hongjiu.lu@intel.com>
415
416 AVX Programming Reference (June, 2010)
417 * i386-dis.c (PREFIX_0FAE_REG_0): New.
418 (PREFIX_0FAE_REG_1): Likewise.
419 (PREFIX_0FAE_REG_2): Likewise.
420 (PREFIX_0FAE_REG_3): Likewise.
421 (PREFIX_VEX_3813): Likewise.
422 (PREFIX_VEX_3A1D): Likewise.
423 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
424 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
425 PREFIX_VEX_3A1D.
426 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
427 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
428 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
429
430 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
431 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
432 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
433
434 * i386-opc.h (CpuXsaveopt): New.
77321f53 435 (CpuFSGSBase): Likewise.
c7b8aa3a
L		 436 (CpuRdRnd): Likewise.
437 (CpuF16C): Likewise.
438 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
439 cpuf16c.
440
441 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
442 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
a00eb5e8
L		 443 * i386-init.h: Regenerated.
444 * i386-tbl.h: Likewise.
c7b8aa3a 445
09a8ad8d
AM		 4462010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
447
448 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
449 and mtocrf on EFS.
450
360cfc9c
AM		 4512010-06-29 Alan Modra <amodra@gmail.com>
452
453 * maxq-dis.c: Delete file.
454 * Makefile.am: Remove references to maxq.
455 * configure.in: Likewise.
456 * disassemble.c: Likewise.
457 * Makefile.in: Regenerate.
458 * configure: Regenerate.
459 * po/POTFILES.in: Regenerate.
460
dc898d5e
AM		 4612010-06-29 Alan Modra <amodra@gmail.com>
462
463 * mep-dis.c: Regenerate.
464
8e560766
MGD		 4652010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
466
467 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
468
c7e2358a
AM		 4692010-06-27 Alan Modra <amodra@gmail.com>
470
471 * arc-dis.c (arc_sprintf): Delete set but unused variables.
472 (decodeInstr): Likewise.
473 * dlx-dis.c (print_insn_dlx): Likewise.
474 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
475 * maxq-dis.c (check_move, print_insn): Likewise.
476 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
477 * msp430-dis.c (msp430_branchinstr): Likewise.
478 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
479 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
480 * sparc-dis.c (print_insn_sparc): Likewise.
481 * fr30-asm.c: Regenerate.
482 * frv-asm.c: Regenerate.
483 * ip2k-asm.c: Regenerate.
484 * iq2000-asm.c: Regenerate.
485 * lm32-asm.c: Regenerate.
486 * m32c-asm.c: Regenerate.
487 * m32r-asm.c: Regenerate.
488 * mep-asm.c: Regenerate.
489 * mt-asm.c: Regenerate.
490 * openrisc-asm.c: Regenerate.
491 * xc16x-asm.c: Regenerate.
492 * xstormy16-asm.c: Regenerate.
493
6ffe3d99
NC		 4942010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
495
496 PR gas/11673
497 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
498
09ec0d17
NC		 4992010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
500
501 PR binutils/11676
502 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
503
e01d869a
AM		 5042010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
505
506 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
507 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
508 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
509 touch floating point regs and are enabled by COM, PPC or PPCCOM.
510 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
511 Treat lwsync as msync on e500.
512
1f4e4950
MGD		 5132010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
514
515 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
516
9d82ec38
MGD		 5172010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
518
e01d869a 519 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
9d82ec38
MGD		 520 constants is the same on 32-bit and 64-bit hosts.
521
c3a6ea62 5222010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
d8b24b95
NC		 523
524 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
525 .short directives so that they can be reassembled.
526
9db8dccb
CM		 5272010-05-26 Catherine Moore <clm@codesourcery.com>
528 David Ung <davidu@mips.com>
529
530 * mips-opc.c: Change membership to I1 for instructions ssnop and
531 ehb.
532
dfc8cf43
L		 5332010-05-26 H.J. Lu <hongjiu.lu@intel.com>
534
535 * i386-dis.c (sib): New.
536 (get_sib): Likewise.
537 (print_insn): Call get_sib.
538 OP_E_memory): Use sib.
539
f79e2745
CM		 5402010-05-26 Catherine Moore <clm@codesoourcery.com>
541
542 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
543 * mips-opc.c (I16): Remove.
544 (mips_builtin_op): Reclassify jalx.
545
51b5d4a8
AM		 5462010-05-19 Alan Modra <amodra@gmail.com>
547
548 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
549 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
550
85d4ac0b
AM		 5512010-05-13 Alan Modra <amodra@gmail.com>
552
553 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
554
4547cb56
NC		 5552010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
556
557 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
558 format.
559 (print_insn_thumb16): Add support for new %W format.
560
6540b386
TG		 5612010-05-07 Tristan Gingold <gingold@adacore.com>
562
563 * Makefile.in: Regenerate with automake 1.11.1.
564 * aclocal.m4: Ditto.
565
3e01a7fd
NC		 5662010-05-05 Nick Clifton <nickc@redhat.com>
567
568 * po/es.po: Updated Spanish translation.
569
9c9c98a5
NC		 5702010-04-22 Nick Clifton <nickc@redhat.com>
571
572 * po/opcodes.pot: Updated by the Translation project.
573 * po/vi.po: Updated Vietnamese translation.
574
f07af43e
L		 5752010-04-16 H.J. Lu <hongjiu.lu@intel.com>
576
577 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
578 bits in opcode.
579
3d540e93
NC		 5802010-04-09 Nick Clifton <nickc@redhat.com>
581
582 * i386-dis.c (print_insn): Remove unused variable op.
583 (OP_sI): Remove unused variable mask.
584
397841b5
AM		 5852010-04-07 Alan Modra <amodra@gmail.com>
586
587 * configure: Regenerate.
588
cee62821
PB		 5892010-04-06 Peter Bergner <bergner@vnet.ibm.com>
590
591 * ppc-opc.c (RBOPT): New define.
592 ("dccci"): Enable for PPCA2. Make operands optional.
593 ("iccci"): Likewise. Do not deprecate for PPC476.
594
accf4463
NC		 5952010-04-02 Masaki Muranaka <monaka@monami-software.com>
596
597 * cr16-opc.c (cr16_instruction): Fix typo in comment.
598
40b36596
JM		 5992010-03-25 Joseph Myers <joseph@codesourcery.com>
600
601 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
602 * Makefile.in: Regenerate.
603 * configure.in (bfd_tic6x_arch): New.
604 * configure: Regenerate.
605 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
606 (disassembler): Handle TI C6X.
607 * tic6x-dis.c: New.
608
1985c81c
MF		 6092010-03-24 Mike Frysinger <vapier@gentoo.org>
610
611 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
612
f66187fd
JM		 6132010-03-23 Joseph Myers <joseph@codesourcery.com>
614
615 * dis-buf.c (buffer_read_memory): Give error for reading just
616 before the start of memory.
617
ce7d077e
SP		 6182010-03-22 Sebastian Pop <sebastian.pop@amd.com>
619 Quentin Neill <quentin.neill@amd.com>
620
621 * i386-dis.c (OP_LWP_I): Removed.
622 (reg_table): Do not use OP_LWP_I, use Iq.
623 (OP_LWPCB_E): Remove use of names16.
624 (OP_LWP_E): Same.
625 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
626 should not set the Vex.length bit.
627 * i386-tbl.h: Regenerated.
628
63d0fa4e
AM		 6292010-02-25 Edmar Wienskoski <edmar@freescale.com>
630
631 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
632
c060226a
NC		 6332010-02-24 Nick Clifton <nickc@redhat.com>
634
635 PR binutils/6773
636 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
637 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
638 (thumb32_opcodes): Likewise.
639
ab7875de
NC		 6402010-02-15 Nick Clifton <nickc@redhat.com>
641
642 * po/vi.po: Updated Vietnamese translation.
643
fee1d3e8
DE		 6442010-02-12 Doug Evans <dje@sebabeach.org>
645
646 * lm32-opinst.c: Regenerate.
647
37ec9240
DE		 6482010-02-11 Doug Evans <dje@sebabeach.org>
649
9468ae89
DE		 650 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
651 (print_address): Delete CGEN_PRINT_ADDRESS.
652 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
653 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
654 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
655 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
656
37ec9240
DE		 657 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
658 * frv-desc.c, * frv-desc.h, * frv-opc.c,
659 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
660 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
661 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
662 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
663 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
664 * mep-desc.c, * mep-desc.h, * mep-opc.c,
665 * mt-desc.c, * mt-desc.h, * mt-opc.c,
666 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
667 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
668 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
669
c75ef631
L		 6702010-02-11 H.J. Lu <hongjiu.lu@intel.com>
671
672 * i386-dis.c: Update copyright.
673 * i386-gen.c: Likewise.
674 * i386-opc.h: Likewise.
675 * i386-opc.tbl: Likewise.
676
a683cc34
SP		 6772010-02-10 Quentin Neill <quentin.neill@amd.com>
678 Sebastian Pop <sebastian.pop@amd.com>
679
680 * i386-dis.c (OP_EX_VexImmW): Reintroduced
681 function to handle 5th imm8 operand.
682 (PREFIX_VEX_3A48): Added.
683 (PREFIX_VEX_3A49): Added.
684 (VEX_W_3A48_P_2): Added.
685 (VEX_W_3A49_P_2): Added.
686 (prefix table): Added entries for PREFIX_VEX_3A48
687 and PREFIX_VEX_3A49.
688 (vex table): Added entries for VEX_W_3A48_P_2 and
689 and VEX_W_3A49_P_2.
690 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
691 for Vec_Imm4 operands.
692 * i386-opc.h (enum): Added Vec_Imm4.
693 (i386_operand_type): Added vec_imm4.
694 * i386-opc.tbl: Add entries for vpermilp[ds].
695 * i386-init.h: Regenerated.
696 * i386-tbl.h: Regenerated.
697
cdc51b07
RS		 6982010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
699
700 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
701 and "pwr7". Move "a2" into alphabetical order.
702
ce3d2015
AM		 7032010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
704
705 * ppc-dis.c (ppc_opts): Add titan entry.
706 * ppc-opc.c (TITAN, MULHW): Define.
707 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
708
68339fdf
SP		 7092010-02-03 Quentin Neill <quentin.neill@amd.com>
710
711 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
712 to CPU_BDVER1_FLAGS
713 * i386-init.h: Regenerated.
714
f3d55a94
AG		 7152010-02-03 Anthony Green <green@moxielogic.com>
716
717 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
718 0x0f, and make 0x00 an illegal instruction.
719
b0e28b39
DJ		 7202010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
721
722 * opcodes/arm-dis.c (struct arm_private_data): New.
723 (print_insn_coprocessor, print_insn_arm): Update to use struct
724 arm_private_data.
725 (is_mapping_symbol, get_map_sym_type): New functions.
726 (get_sym_code_type): Check the symbol's section. Do not check
727 mapping symbols.
728 (print_insn): Default to disassembling ARM mode code. Check
729 for mapping symbols separately from other symbols. Use
730 struct arm_private_data.
731
1c480963
L		 7322010-01-28 H.J. Lu <hongjiu.lu@intel.com>
733
734 * i386-dis.c (EXVexWdqScalar): New.
735 (vex_scalar_w_dq_mode): Likewise.
736 (prefix_table): Update entries for PREFIX_VEX_3899,
737 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
738 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
739 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
740 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
741 (intel_operand_size): Handle vex_scalar_w_dq_mode.
742 (OP_EX): Likewise.
743
539f890d
L		 7442010-01-27 H.J. Lu <hongjiu.lu@intel.com>
745
746 * i386-dis.c (XMScalar): New.
747 (EXdScalar): Likewise.
748 (EXqScalar): Likewise.
749 (EXqScalarS): Likewise.
750 (VexScalar): Likewise.
751 (EXdVexScalarS): Likewise.
752 (EXqVexScalarS): Likewise.
753 (XMVexScalar): Likewise.
754 (scalar_mode): Likewise.
755 (d_scalar_mode): Likewise.
756 (d_scalar_swap_mode): Likewise.
757 (q_scalar_mode): Likewise.
758 (q_scalar_swap_mode): Likewise.
759 (vex_scalar_mode): Likewise.
760 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
761 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
762 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
763 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
764 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
765 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
766 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
767 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
768 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
769 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
770 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
771 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
772 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
773 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
774 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
775 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
776 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
777 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
778 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
779 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
780 q_scalar_mode, q_scalar_swap_mode.
781 (OP_XMM): Handle scalar_mode.
782 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
783 and q_scalar_swap_mode.
784 (OP_VEX): Handle vex_scalar_mode.
785
208b4d78
L		 7862010-01-24 H.J. Lu <hongjiu.lu@intel.com>
787
788 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
789
448b213a
L		 7902010-01-24 H.J. Lu <hongjiu.lu@intel.com>
791
792 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
793
47cf8fa0
L		 7942010-01-24 H.J. Lu <hongjiu.lu@intel.com>
795
796 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
797
592d1631
L		 7982010-01-24 H.J. Lu <hongjiu.lu@intel.com>
799
800 * i386-dis.c (Bad_Opcode): New.
801 (bad_opcode): Likewise.
802 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
803 (dis386_twobyte): Likewise.
804 (reg_table): Likewise.
805 (prefix_table): Likewise.
806 (x86_64_table): Likewise.
807 (vex_len_table): Likewise.
808 (vex_w_table): Likewise.
809 (mod_table): Likewise.
810 (rm_table): Likewise.
811 (float_reg): Likewise.
812 (reg_table): Remove trailing "(bad)" entries.
813 (prefix_table): Likewise.
814 (x86_64_table): Likewise.
815 (vex_len_table): Likewise.
816 (vex_w_table): Likewise.
817 (mod_table): Likewise.
818 (rm_table): Likewise.
819 (get_valid_dis386): Handle bytemode 0.
820
712366da
L		 8212010-01-23 H.J. Lu <hongjiu.lu@intel.com>
822
823 * i386-opc.h (VEXScalar): New.
824
825 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
826 instructions.
827 * i386-tbl.h: Regenerated.
828
706e8205 8292010-01-21 H.J. Lu <hongjiu.lu@intel.com>
73bb6729
L		 830
831 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
832
833 * i386-opc.tbl: Add xsave64 and xrstor64.
834 * i386-tbl.h: Regenerated.
835
99ea83aa
NC		 8362010-01-20 Nick Clifton <nickc@redhat.com>
837
838 PR 11170
839 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
840 based post-indexed addressing.
841
a6461c02
SP		 8422010-01-15 Sebastian Pop <sebastian.pop@amd.com>
843
844 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
845 * i386-tbl.h: Regenerated.
846
a2a7d12c
L		 8472010-01-14 H.J. Lu <hongjiu.lu@intel.com>
848
849 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
850 comments.
851
b9733481
L		 8522010-01-14 H.J. Lu <hongjiu.lu@intel.com>
853
854 * i386-dis.c (names_mm): New.
855 (intel_names_mm): Likewise.
856 (att_names_mm): Likewise.
857 (names_xmm): Likewise.
858 (intel_names_xmm): Likewise.
859 (att_names_xmm): Likewise.
860 (names_ymm): Likewise.
861 (intel_names_ymm): Likewise.
862 (att_names_ymm): Likewise.
863 (print_insn): Set names_mm, names_xmm and names_ymm.
864 (OP_MMX): Use names_mm, names_xmm and names_ymm.
865 (OP_XMM): Likewise.
866 (OP_EM): Likewise.
867 (OP_EMC): Likewise.
868 (OP_MXC): Likewise.
869 (OP_EX): Likewise.
870 (XMM_Fixup): Likewise.
871 (OP_VEX): Likewise.
872 (OP_EX_VexReg): Likewise.
873 (OP_Vex_2src): Likewise.
874 (OP_Vex_2src_1): Likewise.
875 (OP_Vex_2src_2): Likewise.
876 (OP_REG_VexI4): Likewise.
877
5e6718e4
L		 8782010-01-13 H.J. Lu <hongjiu.lu@intel.com>
879
880 * i386-dis.c (print_insn): Update comments.
881
d869730d
L		 8822010-01-12 H.J. Lu <hongjiu.lu@intel.com>
883
884 * i386-dis.c (rex_original): Removed.
885 (ckprefix): Remove rex_original.
886 (print_insn): Update comments.
887
3725885a
RW		 8882010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
889
890 * Makefile.in: Regenerate.
891 * configure: Regenerate.
892
b7cd1872
DE		 8932010-01-07 Doug Evans <dje@sebabeach.org>
894
895 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
896 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
897 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
898 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
899 * xstormy16-ibld.c: Regenerate.
900
69dd9865
SP		 9012010-01-06 Quentin Neill <quentin.neill@amd.com>
902
903 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
904 * i386-init.h: Regenerated.
905
e3e535bc
NC		 9062010-01-06 Daniel Gutson <dgutson@codesourcery.com>
907
908 * arm-dis.c (print_insn): Fixed search for next symbol and data
909 dumping condition, and the initial mapping symbol state.
910
fe8afbc4
DE		 9112010-01-05 Doug Evans <dje@sebabeach.org>
912
913 * cgen-ibld.in: #include "cgen/basic-modes.h".
914 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
915 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
916 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
917 * xstormy16-ibld.c: Regenerate.
918
2edcd244
NC		 9192010-01-04 Nick Clifton <nickc@redhat.com>
920
921 PR 11123
922 * arm-dis.c (print_insn_coprocessor): Initialise value.
923
0dc93057
AM		 9242010-01-04 Edmar Wienskoski <edmar@freescale.com>
925
926 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
927
05994f45
DE		 9282010-01-02 Doug Evans <dje@sebabeach.org>
929
930 * cgen-asm.in: Update copyright year.
931 * cgen-dis.in: Update copyright year.
932 * cgen-ibld.in: Update copyright year.
933 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
934 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
935 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
936 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
937 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
938 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
939 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
940 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
941 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
942 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
943 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
944 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
945 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
946 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
947 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
948 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
949 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
950 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
951 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
952 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
953 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2426c15f 954
43ecc30f 955For older changes see ChangeLog-2009
252b5132
RH		 956\f
957Local Variables:
2f6d2f85
NC		 958mode: change-log
959left-margin: 8
960fill-column: 74
252b5132
RH		 961version-control: never
962End:
GDB Binutils - Deliverables
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