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ChangeLog formatting fixes
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
b2c6190b 12016-12-21 Andrew Waterman <andrew@sifive.com>
58a6d3c9
AW		 2
3 * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
4
11dd08e9
MR		 52016-12-20 Maciej W. Rozycki <macro@imgtec.com>
6
7 * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
8 ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
9 (print_insn_mips16): Check opcode entries for validity against
10 the ISA level and ASE set selected.
11
7fd53920
MR		 122016-12-20 Maciej W. Rozycki <macro@imgtec.com>
13
14 * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
15 `insn' together, with `extend' as the high-order 16 bits.
16 (match_kind): New enum.
17 (print_insn_mips16): Rework for 32-bit instruction matching.
18 Do not dump EXTEND prefixes here.
19 * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
20 Recode `match' and `mask' fields as 32-bit in absolute "jal" and
21 "jalx" entries.
22
4ebce1a0
MR		 232016-12-20 Maciej W. Rozycki <macro@imgtec.com>
24
25 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
26 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
27 INSN_MACRO entries.
28
c97dda72
MR		 292016-12-20 Maciej W. Rozycki <macro@imgtec.com>
30
31 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
32 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
33 opcode).
34
3e67a378
AW		 352016-12-20 Andrew Waterman <andrew@sifive.com>
36
37 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
38 "*.aqrl".
39
04386d9e
AW		 402016-12-20 Andrew Waterman <andrew@sifive.com>
41
42 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
43 INSN_ALIAS.
44
755c5297
AW		 452016-12-20 Andrew Waterman <andrew@sifive.com>
46
47 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
48 format.
49
2922d21d
AW		 502016-12-20 Andrew Waterman <andrew@sifive.com>
51
52 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
53 XLEN when none is provided.
54
1d65abb5
AW		 552016-12-20 Andrew Waterman <andrew@sifive.com>
56
57 * riscv-opc.c: Formatting fixes.
58
dd1d944e
AM		 592016-12-20 Alan Modra <amodra@gmail.com>
60
61 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
62 * Makefile.in: Regenerate.
63 * po/POTFILES.in: Regenerate.
64
91068ec6
MR		 652016-12-19 Maciej W. Rozycki <macro@imgtec.com>
66
67 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
68 Only examine ELF file structures here.
69
4df995c7
MR		 702016-12-19 Maciej W. Rozycki <macro@imgtec.com>
71
72 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
73 `bfd_mips_elf_get_abiflags' here.
74
db7b55fa
NC		 752016-12-16 Nick Clifton <nickc@redhat.com>
76
77 * arm-dis.c (print_insn_thumb32): Fix compile time warning
78 computing value_in_comment.
79
5e7fc731
MR		 802016-12-14 Maciej W. Rozycki <macro@imgtec.com>
81
82 * mips-dis.c (mips_convert_abiflags_ases): New function.
83 (set_default_mips_dis_options): Also infer ASE flags from ELF
84 file structures.
85
8184783a
MR		 862016-12-14 Maciej W. Rozycki <macro@imgtec.com>
87
88 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
89 header flag interpretation code.
90
353abf7c
MR		 912016-12-14 Maciej W. Rozycki <macro@imgtec.com>
92
93 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
94 `pinfo2' with SP-relative "sd" entries.
95
63e014fc
MR		 962016-12-14 Maciej W. Rozycki <macro@imgtec.com>
97
98 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
99 compact jumps.
100
a6a51754
RL		 1012016-12-13 Renlin Li <renlin.li@arm.com>
102
103 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
104 qualifier.
105 (operand_general_constraint_met_p): Remove case for CP_REG.
106 (aarch64_print_operand): Print CRn, CRm operand using imm field.
107 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
108 (QL_SYSL): Likewise.
109 (aarch64_opcode_table): Change CRn, CRm operand class and type.
110 * aarch64-opc-2.c : Regenerate.
111 * aarch64-asm-2.c : Likewise.
112 * aarch64-dis-2.c : Likewise.
113
029e9d52
YQ		 1142016-12-12 Yao Qi <yao.qi@linaro.org>
115
116 * rx-dis.c: Include <setjmp.h>
117 (struct private): New.
118 (rx_get_byte): Check return value of read_memory_func, and
119 call memory_error_func and OPCODES_SIGLONGJMP on error.
120 (print_insn_rx): Call OPCODES_SIGSETJMP.
121
3a0b8f7d
YQ		 1222016-12-12 Yao Qi <yao.qi@linaro.org>
123
124 * rl78-dis.c: Include <setjmp.h>.
125 (struct private): New.
126 (rl78_get_byte): Check return value of read_memory_func, and
127 call memory_error_func and OPCODES_SIGLONGJMP on error.
128 (print_insn_rl78_common): Call OPCODES_SIGJMP.
129
64c11183
MR		 1302016-12-09 Maciej W. Rozycki <macro@imgtec.com>
131
132 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
133
f17ecb4b
MR		 1342016-12-09 Maciej W. Rozycki <macro@imgtec.com>
135
136 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
137 than UINT.
138
55af4784
MR		 1392016-12-09 Maciej W. Rozycki <macro@imgtec.com>
140
141 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
142 to separate `extend' and its uninterpreted argument output.
143 Separate hexadecimal halves of undecoded extended instructions
144 output.
145
39f66f3a
MR		 1462016-12-08 Maciej W. Rozycki <macro@imgtec.com>
147
148 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
149 indentation space across.
150
860b03a8
MR		 1512016-12-08 Maciej W. Rozycki <macro@imgtec.com>
152
153 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
154 adjustment for PC-relative operations following MIPS16e compact
155 jumps or undefined RR/J(AL)R(C) encodings.
156
329d01f7
MR		 1572016-12-08 Maciej W. Rozycki <macro@imgtec.com>
158
159 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
160 variable to `reglane_index'.
161
3a2488dd
LM		 1622016-12-08 Luis Machado <lgustavo@codesourcery.com>
163
164 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
165
5f5c6e03
MR		 1662016-12-07 Maciej W. Rozycki <macro@imgtec.com>
167
168 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
169
343fa690
MR		 1702016-12-07 Maciej W. Rozycki <macro@imgtec.com>
171
172 * mips16-opc.c (mips16_opcodes): Update comment naming structure
173 members.
174
6725647c
MR		 1752016-12-07 Maciej W. Rozycki <macro@imgtec.com>
176
177 * mips-dis.c (print_mips_disassembler_options): Reformat output.
178
c28eeff2
SN		 1792016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
180
181 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
182 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
183
49e8a725
SN		 1842016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
185
186 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
187
a37a2806
NC		 1882016-12-01 Nick Clifton <nickc@redhat.com>
189
190 PR binutils/20893
191 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
192 opcode designator.
193
abe7c33b
CZ		 1942016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
195
196 * arc-opc.c (insert_ra_chk): New function.
197 (insert_rb_chk): Likewise.
198 (insert_rad): Update text error message.
199 (insert_rcd): Likewise.
200 (insert_rhv2): Likewise.
201 (insert_r0): Likewise.
202 (insert_r1): Likewise.
203 (insert_r2): Likewise.
204 (insert_r3): Likewise.
205 (insert_sp): Likewise.
206 (insert_gp): Likewise.
207 (insert_pcl): Likewise.
208 (insert_blink): Likewise.
209 (insert_ilink1): Likewise.
210 (insert_ilink2): Likewise.
211 (insert_ras): Likewise.
212 (insert_rbs): Likewise.
213 (insert_rcs): Likewise.
214 (insert_simm3s): Likewise.
215 (insert_rrange): Likewise.
216 (insert_fpel): Likewise.
217 (insert_blinkel): Likewise.
218 (insert_pcel): Likewise.
219 (insert_nps_3bit_dst): Likewise.
220 (insert_nps_3bit_dst_short): Likewise.
221 (insert_nps_3bit_src2_short): Likewise.
222 (insert_nps_bitop_size_2b): Likewise.
223 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
224 (RA_CHK): Define.
225 (RB): Adjust.
226 (RB_CHK): Define.
227 (RC): Adjust.
228 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
229 * arc-tbl.h (div, divu): All instructions are DIVREM class.
230 Change first insn argument to check for LP_COUNT usage.
231 (rem): Likewise.
232 (ld, ldd): All instructions are LOAD class. Change first insn
233 argument to check for LP_COUNT usage.
234 (st, std): All instructions are STORE class.
235 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
236 Change first insn argument to check for LP_COUNT usage.
237 (mov): All instructions are MOVE class. Change first insn
238 argument to check for LP_COUNT usage.
239
ee881e5d
CZ		 2402016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
241
242 * arc-dis.c (is_compatible_p): Remove function.
243 (skip_this_opcode): Don't add any decoding class to decode list.
244 Remove warning.
245 (find_format_from_table): Go through all opcodes, and warn if we
246 use a guessed mnemonic.
247
abfcb414
AP		 2482016-11-28 Ramiro Polla <ramiro@hex-rays.com>
249 Amit Pawar <amit.pawar@amd.com>
250
251 PR binutils/20637
252 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
253 instructions.
254
96fe4562
AM		 2552016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
256
257 * configure: Regenerate.
258
6884417a
JM		 2592016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
260
261 * sparc-opc.c (HWS_V8): Definition moved from
262 gas/config/tc-sparc.c.
263 (HWS_V9): Likewise.
264 (HWS_VA): Likewise.
265 (HWS_VB): Likewise.
266 (HWS_VC): Likewise.
267 (HWS_VD): Likewise.
268 (HWS_VE): Likewise.
269 (HWS_VV): Likewise.
270 (HWS_VM): Likewise.
271 (HWS2_VM): Likewise.
272 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
273 existing entries.
274
c4b943d7
CZ		 2752016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
276
277 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
278 instructions.
279
c2c4ff8d
SN		 2802016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
281
282 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
283 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
284 (aarch64_opcode_table): Add fcmla and fcadd.
285 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
286 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
287 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
288 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
289 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
290 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
291 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
292 (operand_general_constraint_met_p): Rotate and index range check.
293 (aarch64_print_operand): Handle rotate operand.
294 * aarch64-asm-2.c: Regenerate.
295 * aarch64-dis-2.c: Likewise.
296 * aarch64-opc-2.c: Likewise.
297
28617675
SN		 2982016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
299
300 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
301 * aarch64-asm-2.c: Regenerate.
302 * aarch64-dis-2.c: Regenerate.
303 * aarch64-opc-2.c: Regenerate.
304
ccfc90a3
SN		 3052016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
306
307 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
308 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
309 * aarch64-asm-2.c: Regenerate.
310 * aarch64-dis-2.c: Regenerate.
311 * aarch64-opc-2.c: Regenerate.
312
3f06e550
SN		 3132016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
314
315 * aarch64-tbl.h (QL_X1NIL): New.
316 (arch64_opcode_table): Add ldraa, ldrab.
317 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
318 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
319 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
320 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
321 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
322 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
323 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
324 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
325 (aarch64_print_operand): Likewise.
326 * aarch64-asm-2.c: Regenerate.
327 * aarch64-dis-2.c: Regenerate.
328 * aarch64-opc-2.c: Regenerate.
329
74f5402d
SN		 3302016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
331
332 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
333 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
334 * aarch64-asm-2.c: Regenerate.
335 * aarch64-dis-2.c: Regenerate.
336 * aarch64-opc-2.c: Regenerate.
337
c84364ec
SN		 3382016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
339
340 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
341 (AARCH64_OPERANDS): Add Rm_SP.
342 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
343 * aarch64-asm-2.c: Regenerate.
344 * aarch64-dis-2.c: Regenerate.
345 * aarch64-opc-2.c: Regenerate.
346
a2cfc830
SN		 3472016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
348
349 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
350 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
351 autdzb, xpaci, xpacd.
352 * aarch64-asm-2.c: Regenerate.
353 * aarch64-dis-2.c: Regenerate.
354 * aarch64-opc-2.c: Regenerate.
355
b0bfa7b5
SN		 3562016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
357
358 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
359 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
360 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
361 (aarch64_sys_reg_supported_p): Add feature test for new registers.
362
8787d804
SN		 3632016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
364
365 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
366 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
367 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
368 autibsp.
369 * aarch64-asm-2.c: Regenerate.
370 * aarch64-dis-2.c: Regenerate.
371
3d731f69
SN		 3722016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
373
374 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
375
60227d64
L		 3762016-11-09 H.J. Lu <hongjiu.lu@intel.com>
377
378 PR binutils/20799
379 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
380 * i386-dis.c (EdqwS): Removed.
381 (dqw_swap_mode): Likewise.
382 (intel_operand_size): Don't check dqw_swap_mode.
383 (OP_E_register): Likewise.
384 (OP_E_memory): Likewise.
385 (OP_G): Likewise.
386 (OP_EX): Likewise.
387 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
388 * i386-tbl.h: Regerated.
389
7efeed17
L		 3902016-11-09 H.J. Lu <hongjiu.lu@intel.com>
391
392 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 393 * i386-tbl.h: Regerated.
7efeed17 394
1f334aeb
L		 3952016-11-08 H.J. Lu <hongjiu.lu@intel.com>
396
397 PR binutils/20701
398 * i386-dis.c (THREE_BYTE_0F7A): Removed.
399 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
400 (three_byte_table): Remove THREE_BYTE_0F7A.
401
48c97fa1
L		 4022016-11-07 H.J. Lu <hongjiu.lu@intel.com>
403
404 PR binutils/20775
405 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
406 (FGRPd9_4): Replace 1 with 2.
407 (FGRPd9_5): Replace 2 with 3.
408 (FGRPd9_6): Replace 3 with 4.
409 (FGRPd9_7): Replace 4 with 5.
410 (FGRPda_5): Replace 5 with 6.
411 (FGRPdb_4): Replace 6 with 7.
412 (FGRPde_3): Replace 7 with 8.
413 (FGRPdf_4): Replace 8 with 9.
414 (fgrps): Add an entry for Bad_Opcode.
415
b437d035
AB		 4162016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
417
418 * arc-opc.c (arc_flag_operands): Add F_DI14.
419 (arc_flag_classes): Add C_DI14.
420 * arc-nps400-tbl.h: Add new exc instructions.
421
5a736821
GM		 4222016-11-03 Graham Markall <graham.markall@embecosm.com>
423
424 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
425 major opcode 0xa.
426 * arc-nps-400-tbl.h: Add dcmac instruction.
427 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
428 (insert_nps_rbdouble_64): Added.
429 (extract_nps_rbdouble_64): Added.
430 (insert_nps_proto_size): Added.
431 (extract_nps_proto_size): Added.
432
bdfe53e3
AB		 4332016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
434
435 * arc-dis.c (struct arc_operand_iterator): Remove all fields
436 relating to long instruction processing, add new limm field.
437 (OPCODE): Rename to...
438 (OPCODE_32BIT_INSN): ...this.
439 (OPCODE_AC): Delete.
440 (skip_this_opcode): Handle different instruction lengths, update
441 macro name.
442 (special_flag_p): Update parameter type.
443 (find_format_from_table): Update for more instruction lengths.
444 (find_format_long_instructions): Delete.
445 (find_format): Update for more instruction lengths.
446 (arc_insn_length): Likewise.
447 (extract_operand_value): Update for more instruction lengths.
448 (operand_iterator_next): Remove code relating to long
449 instructions.
450 (arc_opcode_to_insn_type): New function.
451 (print_insn_arc):Update for more instructions lengths.
452 * arc-ext.c (extInstruction_t): Change argument type.
453 * arc-ext.h (extInstruction_t): Change argument type.
454 * arc-fxi.h: Change type unsigned to unsigned long long
455 extensively throughout.
456 * arc-nps400-tbl.h: Add long instructions taken from
457 arc_long_opcodes table in arc-opc.c.
458 * arc-opc.c: Update parameter types on insert/extract handlers.
459 (arc_long_opcodes): Delete.
460 (arc_num_long_opcodes): Delete.
461 (arc_opcode_len): Update for more instruction lengths.
462
90f61cce
GM		 4632016-11-03 Graham Markall <graham.markall@embecosm.com>
464
465 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
466
06fe285f
GM		 4672016-11-03 Graham Markall <graham.markall@embecosm.com>
468
469 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
470 with arc_opcode_len.
471 (find_format_long_instructions): Likewise.
472 * arc-opc.c (arc_opcode_len): New function.
473
ecf64ec6
AB		 4742016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
475
476 * arc-nps400-tbl.h: Fix some instruction masks.
477
d039fef3
L		 4782016-11-03 H.J. Lu <hongjiu.lu@intel.com>
479
480 * i386-dis.c (REG_82): Removed.
481 (X86_64_82_REG_0): Likewise.
482 (X86_64_82_REG_1): Likewise.
483 (X86_64_82_REG_2): Likewise.
484 (X86_64_82_REG_3): Likewise.
485 (X86_64_82_REG_4): Likewise.
486 (X86_64_82_REG_5): Likewise.
487 (X86_64_82_REG_6): Likewise.
488 (X86_64_82_REG_7): Likewise.
489 (X86_64_82): New.
490 (dis386): Use X86_64_82 instead of REG_82.
491 (reg_table): Remove REG_82.
492 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
493 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
494 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
495 X86_64_82_REG_7.
496
8b89fe14
L		 4972016-11-03 H.J. Lu <hongjiu.lu@intel.com>
498
499 PR binutils/20754
500 * i386-dis.c (REG_82): New.
501 (X86_64_82_REG_0): Likewise.
502 (X86_64_82_REG_1): Likewise.
503 (X86_64_82_REG_2): Likewise.
504 (X86_64_82_REG_3): Likewise.
505 (X86_64_82_REG_4): Likewise.
506 (X86_64_82_REG_5): Likewise.
507 (X86_64_82_REG_6): Likewise.
508 (X86_64_82_REG_7): Likewise.
509 (dis386): Use REG_82.
510 (reg_table): Add REG_82.
511 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
512 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
513 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
514
7148c369
L		 5152016-11-03 H.J. Lu <hongjiu.lu@intel.com>
516
517 * i386-dis.c (REG_82): Renamed to ...
518 (REG_83): This.
519 (dis386): Updated.
520 (reg_table): Likewise.
521
47acf0bd
IT		 5222016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
523
524 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
525 * i386-dis-evex.h (evex_table): Updated.
526 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
527 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
528 (cpu_flags): Add CpuAVX512_4VNNIW.
529 * i386-opc.h (enum): (AVX512_4VNNIW): New.
530 (i386_cpu_flags): Add cpuavx512_4vnniw.
531 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
532 * i386-init.h: Regenerate.
533 * i386-tbl.h: Ditto.
534
920d2ddc
IT		 5352016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
536
537 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
538 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
539 * i386-dis-evex.h (evex_table): Updated.
540 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
541 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
542 (cpu_flags): Add CpuAVX512_4FMAPS.
543 (opcode_modifiers): Add ImplicitQuadGroup modifier.
544 * i386-opc.h (AVX512_4FMAP): New.
545 (i386_cpu_flags): Add cpuavx512_4fmaps.
546 (ImplicitQuadGroup): New.
547 (i386_opcode_modifier): Add implicitquadgroup.
548 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
549 * i386-init.h: Regenerate.
550 * i386-tbl.h: Ditto.
551
e23eba97
NC		 5522016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
553 Andrew Waterman <andrew@sifive.com>
554
555 Add support for RISC-V architecture.
556 * configure.ac: Add entry for bfd_riscv_arch.
557 * configure: Regenerate.
558 * disassemble.c (disassembler): Add support for riscv.
559 (disassembler_usage): Likewise.
560 * riscv-dis.c: New file.
561 * riscv-opc.c: New file.
562
b5cefcca
L		 5632016-10-21 H.J. Lu <hongjiu.lu@intel.com>
564
565 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
566 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
567 (rm_table): Update the RM_0FAE_REG_7 entry.
568 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
569 (cpu_flags): Remove CpuPCOMMIT.
570 * i386-opc.h (CpuPCOMMIT): Removed.
571 (i386_cpu_flags): Remove cpupcommit.
572 * i386-opc.tbl: Remove pcommit.
573 * i386-init.h: Regenerated.
574 * i386-tbl.h: Likewise.
575
9889cbb1
L		 5762016-10-20 H.J. Lu <hongjiu.lu@intel.com>
577
578 PR binutis/20705
579 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
580 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
581 32-bit mode. Don't check vex.register_specifier in 32-bit
582 mode.
583 (OP_VEX): Check for invalid mask registers.
584
28596323
L		 5852016-10-18 H.J. Lu <hongjiu.lu@intel.com>
586
587 PR binutis/20699
588 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
589 sizeflag.
590
da8d7d66
L		 5912016-10-18 H.J. Lu <hongjiu.lu@intel.com>
592
593 PR binutis/20704
594 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
595
eaf02703
MR		 5962016-10-18 Maciej W. Rozycki <macro@imgtec.com>
597
598 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
599 local variable to `index_regno'.
600
decf5bd1
CM		 6012016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
602
603 * arc-tbl.h: Removed any "inv.+" instructions from the table.
604
e5b06ef0
CZ		 6052016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
606
607 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
608 usage on ISA basis.
609
93562a34
JW		 6102016-10-11 Jiong Wang <jiong.wang@arm.com>
611
612 PR target/20666
613 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
614
362c0c4d
JW		 6152016-10-07 Jiong Wang <jiong.wang@arm.com>
616
617 PR target/20667
618 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
619 available.
620
1047201f
AM		 6212016-10-07 Alan Modra <amodra@gmail.com>
622
623 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
624
1a0670f3
AM		 6252016-10-06 Alan Modra <amodra@gmail.com>
626
627 * aarch64-opc.c: Spell fall through comments consistently.
628 * i386-dis.c: Likewise.
629 * aarch64-dis.c: Add missing fall through comments.
630 * aarch64-opc.c: Likewise.
631 * arc-dis.c: Likewise.
632 * arm-dis.c: Likewise.
633 * i386-dis.c: Likewise.
634 * m68k-dis.c: Likewise.
635 * mep-asm.c: Likewise.
636 * ns32k-dis.c: Likewise.
637 * sh-dis.c: Likewise.
638 * tic4x-dis.c: Likewise.
639 * tic6x-dis.c: Likewise.
640 * vax-dis.c: Likewise.
641
2b804145
AM		 6422016-10-06 Alan Modra <amodra@gmail.com>
643
644 * arc-ext.c (create_map): Add missing break.
645 * msp430-decode.opc (encode_as): Likewise.
646 * msp430-decode.c: Regenerate.
647
616ec358
AM		 6482016-10-06 Alan Modra <amodra@gmail.com>
649
650 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
651 * crx-dis.c (print_insn_crx): Likewise.
652
72da393d
L		 6532016-09-30 H.J. Lu <hongjiu.lu@intel.com>
654
655 PR binutils/20657
656 * i386-dis.c (putop): Don't assign alt twice.
657
744ce302
JW		 6582016-09-29 Jiong Wang <jiong.wang@arm.com>
659
660 PR target/20553
661 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
662
a5721ba2
AM		 6632016-09-29 Alan Modra <amodra@gmail.com>
664
665 * ppc-opc.c (L): Make compulsory.
666 (LOPT): New, optional form of L.
667 (HTM_R): Define as LOPT.
668 (L0, L1): Delete.
669 (L32OPT): New, optional for 32-bit L.
670 (L2OPT): New, 2-bit L for dcbf.
671 (SVC_LEC): Update.
672 (L2): Define.
673 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
674 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
675 <dcbf>: Use L2OPT.
676 <tlbiel, tlbie>: Use LOPT.
677 <wclr, wclrall>: Use L2.
678
c5da1932
VZ		 6792016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
680
681 * Makefile.in: Regenerate.
682 * configure: Likewise.
683
2b848ebd
CZ		 6842016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
685
686 * arc-ext-tbl.h (EXTINSN2OPF): Define.
687 (EXTINSN2OP): Use EXTINSN2OPF.
688 (bspeekm, bspop, modapp): New extension instructions.
689 * arc-opc.c (F_DNZ_ND): Define.
690 (F_DNZ_D): Likewise.
691 (F_SIZEB1): Changed.
692 (C_DNZ_D): Define.
693 (C_HARD): Changed.
694 * arc-tbl.h (dbnz): New instruction.
695 (prealloc): Allow it for ARC EM.
696 (xbfu): Likewise.
697
ad43e107
RS		 6982016-09-21 Richard Sandiford <richard.sandiford@arm.com>
699
700 * aarch64-opc.c (print_immediate_offset_address): Print spaces
701 after commas in addresses.
702 (aarch64_print_operand): Likewise.
703
ab3b8fcf
RS		 7042016-09-21 Richard Sandiford <richard.sandiford@arm.com>
705
706 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
707 rather than "should be" or "expected to be" in error messages.
708
bb7eff52
RS		 7092016-09-21 Richard Sandiford <richard.sandiford@arm.com>
710
711 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
712 (print_mnemonic_name): ...here.
713 (print_comment): New function.
714 (print_aarch64_insn): Call it.
715 * aarch64-opc.c (aarch64_conds): Add SVE names.
716 (aarch64_print_operand): Print alternative condition names in
717 a comment.
718
c0890d26
RS		 7192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
720
721 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
722 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
723 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
724 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
725 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
726 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
727 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
728 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
729 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
730 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
731 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
732 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
733 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
734 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
735 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
736 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
737 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
738 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
739 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
740 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
741 (OP_SVE_XWU, OP_SVE_XXU): New macros.
742 (aarch64_feature_sve): New variable.
743 (SVE): New macro.
744 (_SVE_INSN): Likewise.
745 (aarch64_opcode_table): Add SVE instructions.
746 * aarch64-opc.h (extract_fields): Declare.
747 * aarch64-opc-2.c: Regenerate.
748 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
749 * aarch64-asm-2.c: Regenerate.
750 * aarch64-dis.c (extract_fields): Make global.
751 (do_misc_decoding): Handle the new SVE aarch64_ops.
752 * aarch64-dis-2.c: Regenerate.
753
116b6019
RS		 7542016-09-21 Richard Sandiford <richard.sandiford@arm.com>
755
756 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
757 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
758 aarch64_field_kinds.
759 * aarch64-opc.c (fields): Add corresponding entries.
760 * aarch64-asm.c (aarch64_get_variant): New function.
761 (aarch64_encode_variant_using_iclass): Likewise.
762 (aarch64_opcode_encode): Call it.
763 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
764 (aarch64_opcode_decode): Call it.
765
047cd301
RS		 7662016-09-21 Richard Sandiford <richard.sandiford@arm.com>
767
768 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
769 and FP register operands.
770 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
771 (FLD_SVE_Vn): New aarch64_field_kinds.
772 * aarch64-opc.c (fields): Add corresponding entries.
773 (aarch64_print_operand): Handle the new SVE core and FP register
774 operands.
775 * aarch64-opc-2.c: Regenerate.
776 * aarch64-asm-2.c: Likewise.
777 * aarch64-dis-2.c: Likewise.
778
165d4950
RS		 7792016-09-21 Richard Sandiford <richard.sandiford@arm.com>
780
781 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
782 immediate operands.
783 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
784 * aarch64-opc.c (fields): Add corresponding entry.
785 (operand_general_constraint_met_p): Handle the new SVE FP immediate
786 operands.
787 (aarch64_print_operand): Likewise.
788 * aarch64-opc-2.c: Regenerate.
789 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
790 (ins_sve_float_zero_one): New inserters.
791 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
792 (aarch64_ins_sve_float_half_two): Likewise.
793 (aarch64_ins_sve_float_zero_one): Likewise.
794 * aarch64-asm-2.c: Regenerate.
795 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
796 (ext_sve_float_zero_one): New extractors.
797 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
798 (aarch64_ext_sve_float_half_two): Likewise.
799 (aarch64_ext_sve_float_zero_one): Likewise.
800 * aarch64-dis-2.c: Regenerate.
801
e950b345
RS		 8022016-09-21 Richard Sandiford <richard.sandiford@arm.com>
803
804 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
805 integer immediate operands.
806 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
807 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
808 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
809 * aarch64-opc.c (fields): Add corresponding entries.
810 (operand_general_constraint_met_p): Handle the new SVE integer
811 immediate operands.
812 (aarch64_print_operand): Likewise.
813 (aarch64_sve_dupm_mov_immediate_p): New function.
814 * aarch64-opc-2.c: Regenerate.
815 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
816 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
817 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
818 (aarch64_ins_limm): ...here.
819 (aarch64_ins_inv_limm): New function.
820 (aarch64_ins_sve_aimm): Likewise.
821 (aarch64_ins_sve_asimm): Likewise.
822 (aarch64_ins_sve_limm_mov): Likewise.
823 (aarch64_ins_sve_shlimm): Likewise.
824 (aarch64_ins_sve_shrimm): Likewise.
825 * aarch64-asm-2.c: Regenerate.
826 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
827 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
828 * aarch64-dis.c (decode_limm): New function, split out from...
829 (aarch64_ext_limm): ...here.
830 (aarch64_ext_inv_limm): New function.
831 (decode_sve_aimm): Likewise.
832 (aarch64_ext_sve_aimm): Likewise.
833 (aarch64_ext_sve_asimm): Likewise.
834 (aarch64_ext_sve_limm_mov): Likewise.
835 (aarch64_top_bit): Likewise.
836 (aarch64_ext_sve_shlimm): Likewise.
837 (aarch64_ext_sve_shrimm): Likewise.
838 * aarch64-dis-2.c: Regenerate.
839
98907a70
RS		 8402016-09-21 Richard Sandiford <richard.sandiford@arm.com>
841
842 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
843 operands.
844 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
845 the AARCH64_MOD_MUL_VL entry.
846 (value_aligned_p): Cope with non-power-of-two alignments.
847 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
848 (print_immediate_offset_address): Likewise.
849 (aarch64_print_operand): Likewise.
850 * aarch64-opc-2.c: Regenerate.
851 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
852 (ins_sve_addr_ri_s9xvl): New inserters.
853 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
854 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
855 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
856 * aarch64-asm-2.c: Regenerate.
857 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
858 (ext_sve_addr_ri_s9xvl): New extractors.
859 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
860 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
861 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
862 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
863 * aarch64-dis-2.c: Regenerate.
864
4df068de
RS		 8652016-09-21 Richard Sandiford <richard.sandiford@arm.com>
866
867 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
868 address operands.
869 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
870 (FLD_SVE_xs_22): New aarch64_field_kinds.
871 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
872 (get_operand_specific_data): New function.
873 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
874 FLD_SVE_xs_14 and FLD_SVE_xs_22.
875 (operand_general_constraint_met_p): Handle the new SVE address
876 operands.
877 (sve_reg): New array.
878 (get_addr_sve_reg_name): New function.
879 (aarch64_print_operand): Handle the new SVE address operands.
880 * aarch64-opc-2.c: Regenerate.
881 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
882 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
883 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
884 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
885 (aarch64_ins_sve_addr_rr_lsl): Likewise.
886 (aarch64_ins_sve_addr_rz_xtw): Likewise.
887 (aarch64_ins_sve_addr_zi_u5): Likewise.
888 (aarch64_ins_sve_addr_zz): Likewise.
889 (aarch64_ins_sve_addr_zz_lsl): Likewise.
890 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
891 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
892 * aarch64-asm-2.c: Regenerate.
893 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
894 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
895 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
896 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
897 (aarch64_ext_sve_addr_ri_u6): Likewise.
898 (aarch64_ext_sve_addr_rr_lsl): Likewise.
899 (aarch64_ext_sve_addr_rz_xtw): Likewise.
900 (aarch64_ext_sve_addr_zi_u5): Likewise.
901 (aarch64_ext_sve_addr_zz): Likewise.
902 (aarch64_ext_sve_addr_zz_lsl): Likewise.
903 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
904 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
905 * aarch64-dis-2.c: Regenerate.
906
2442d846
RS		 9072016-09-21 Richard Sandiford <richard.sandiford@arm.com>
908
909 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
910 AARCH64_OPND_SVE_PATTERN_SCALED.
911 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
912 * aarch64-opc.c (fields): Add a corresponding entry.
913 (set_multiplier_out_of_range_error): New function.
914 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
915 (operand_general_constraint_met_p): Handle
916 AARCH64_OPND_SVE_PATTERN_SCALED.
917 (print_register_offset_address): Use PRIi64 to print the
918 shift amount.
919 (aarch64_print_operand): Likewise. Handle
920 AARCH64_OPND_SVE_PATTERN_SCALED.
921 * aarch64-opc-2.c: Regenerate.
922 * aarch64-asm.h (ins_sve_scale): New inserter.
923 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
924 * aarch64-asm-2.c: Regenerate.
925 * aarch64-dis.h (ext_sve_scale): New inserter.
926 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
927 * aarch64-dis-2.c: Regenerate.
928
245d2e3f
RS		 9292016-09-21 Richard Sandiford <richard.sandiford@arm.com>
930
931 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
932 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
933 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
934 (FLD_SVE_prfop): Likewise.
935 * aarch64-opc.c: Include libiberty.h.
936 (aarch64_sve_pattern_array): New variable.
937 (aarch64_sve_prfop_array): Likewise.
938 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
939 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
940 AARCH64_OPND_SVE_PRFOP.
941 * aarch64-asm-2.c: Regenerate.
942 * aarch64-dis-2.c: Likewise.
943 * aarch64-opc-2.c: Likewise.
944
d50c751e
RS		 9452016-09-21 Richard Sandiford <richard.sandiford@arm.com>
946
947 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
948 AARCH64_OPND_QLF_P_[ZM].
949 (aarch64_print_operand): Print /z and /m where appropriate.
950
f11ad6bc
RS		 9512016-09-21 Richard Sandiford <richard.sandiford@arm.com>
952
953 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
954 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
955 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
956 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
957 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
958 * aarch64-opc.c (fields): Add corresponding entries here.
959 (operand_general_constraint_met_p): Check that SVE register lists
960 have the correct length. Check the ranges of SVE index registers.
961 Check for cases where p8-p15 are used in 3-bit predicate fields.
962 (aarch64_print_operand): Handle the new SVE operands.
963 * aarch64-opc-2.c: Regenerate.
964 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
965 * aarch64-asm.c (aarch64_ins_sve_index): New function.
966 (aarch64_ins_sve_reglist): Likewise.
967 * aarch64-asm-2.c: Regenerate.
968 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
969 * aarch64-dis.c (aarch64_ext_sve_index): New function.
970 (aarch64_ext_sve_reglist): Likewise.
971 * aarch64-dis-2.c: Regenerate.
972
0c608d6b
RS		 9732016-09-21 Richard Sandiford <richard.sandiford@arm.com>
974
975 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
976 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
977 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
978 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
979 tied operands.
980
01dbfe4c
RS		 9812016-09-21 Richard Sandiford <richard.sandiford@arm.com>
982
983 * aarch64-opc.c (get_offset_int_reg_name): New function.
984 (print_immediate_offset_address): Likewise.
985 (print_register_offset_address): Take the base and offset
986 registers as parameters.
987 (aarch64_print_operand): Update caller accordingly. Use
988 print_immediate_offset_address.
989
72e9f319
RS		 9902016-09-21 Richard Sandiford <richard.sandiford@arm.com>
991
992 * aarch64-opc.c (BANK): New macro.
993 (R32, R64): Take a register number as argument
994 (int_reg): Use BANK.
995
8a7f0c1b
RS		 9962016-09-21 Richard Sandiford <richard.sandiford@arm.com>
997
998 * aarch64-opc.c (print_register_list): Add a prefix parameter.
999 (aarch64_print_operand): Update accordingly.
1000
aa2aa4c6
RS		 10012016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1002
1003 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1004 for FPIMM.
1005 * aarch64-asm.h (ins_fpimm): New inserter.
1006 * aarch64-asm.c (aarch64_ins_fpimm): New function.
1007 * aarch64-asm-2.c: Regenerate.
1008 * aarch64-dis.h (ext_fpimm): New extractor.
1009 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1010 (aarch64_ext_fpimm): New function.
1011 * aarch64-dis-2.c: Regenerate.
1012
b5464a68
RS		 10132016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1014
1015 * aarch64-asm.c: Include libiberty.h.
1016 (insert_fields): New function.
1017 (aarch64_ins_imm): Use it.
1018 * aarch64-dis.c (extract_fields): New function.
1019 (aarch64_ext_imm): Use it.
1020
42408347
RS		 10212016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1022
1023 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1024 with an esize parameter.
1025 (operand_general_constraint_met_p): Update accordingly.
1026 Fix misindented code.
1027 * aarch64-asm.c (aarch64_ins_limm): Update call to
1028 aarch64_logical_immediate_p.
1029
4989adac
RS		 10302016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1031
1032 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1033
bd11d5d8
RS		 10342016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1035
1036 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1037
f807f43d
CZ		 10382016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
1039
1040 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1041
fd486b63
PB		 10422016-09-14 Peter Bergner <bergner@vnet.ibm.com>
1043
1044 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1045 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1046 xor3>: Delete mnemonics.
1047 <cp_abort>: Rename mnemonic from ...
1048 <cpabort>: ...to this.
1049 <setb>: Change to a X form instruction.
1050 <sync>: Change to 1 operand form.
1051 <copy>: Delete mnemonic.
1052 <copy_first>: Rename mnemonic from ...
1053 <copy>: ...to this.
1054 <paste, paste.>: Delete mnemonics.
1055 <paste_last>: Rename mnemonic from ...
1056 <paste.>: ...to this.
1057
dce08442
AK		 10582016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1059
1060 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1061
952c3f51
AK		 10622016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1063
1064 * s390-mkopc.c (main): Support alternate arch strings.
1065
8b71537b
PS		 10662016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1067
1068 * s390-opc.txt: Fix kmctr instruction type.
1069
5b64d091
L		 10702016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1071
1072 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1073 * i386-init.h: Regenerated.
1074
7763838e
CM		 10752016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1076
1077 * opcodes/arc-dis.c (print_insn_arc): Changed.
1078
1b8b6532
JM		 10792016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1080
1081 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1082 camellia_fl.
1083
1a336194
TP		 10842016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1085
1086 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1087 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1088 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1089
6b40c462
L		 10902016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1091
1092 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1093 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1094 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1095 PREFIX_MOD_3_0FAE_REG_4.
1096 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1097 PREFIX_MOD_3_0FAE_REG_4.
1098 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1099 (cpu_flags): Add CpuPTWRITE.
1100 * i386-opc.h (CpuPTWRITE): New.
1101 (i386_cpu_flags): Add cpuptwrite.
1102 * i386-opc.tbl: Add ptwrite instruction.
1103 * i386-init.h: Regenerated.
1104 * i386-tbl.h: Likewise.
1105
ab548d2d
AK		 11062016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1107
1108 * arc-dis.h: Wrap around in extern "C".
1109
344bde0a
RS		 11102016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1111
1112 * aarch64-tbl.h (V8_2_INSN): New macro.
1113 (aarch64_opcode_table): Use it.
1114
5ce912d8
RS		 11152016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1116
1117 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1118 CORE_INSN, __FP_INSN and SIMD_INSN.
1119
9d30b0bd
RS		 11202016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1121
1122 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1123 (aarch64_opcode_table): Update uses accordingly.
1124
dfdaec14
AJ		 11252016-07-25 Andrew Jenner <andrew@codesourcery.com>
1126 Kwok Cheung Yeung <kcy@codesourcery.com>
1127
1128 opcodes/
1129 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1130 'e_cmplwi' to 'e_cmpli' instead.
1131 (OPVUPRT, OPVUPRT_MASK): Define.
1132 (powerpc_opcodes): Add E200Z4 insns.
1133 (vle_opcodes): Add context save/restore insns.
1134
7bd374a4
MR		 11352016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1136
1137 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1138 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1139 "j".
1140
db18dbab
GM		 11412016-07-27 Graham Markall <graham.markall@embecosm.com>
1142
1143 * arc-nps400-tbl.h: Change block comments to GNU format.
1144 * arc-dis.c: Add new globals addrtypenames,
1145 addrtypenames_max, and addtypeunknown.
1146 (get_addrtype): New function.
1147 (print_insn_arc): Print colons and address types when
1148 required.
1149 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1150 define insert and extract functions for all address types.
1151 (arc_operands): Add operands for colon and all address
1152 types.
1153 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1154 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1155 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1156 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1157 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1158 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1159
fecd57f9
L		 11602016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1161
1162 * configure: Regenerated.
1163
37fd5ef3
CZ		 11642016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1165
1166 * arc-dis.c (skipclass): New structure.
1167 (decodelist): New variable.
1168 (is_compatible_p): New function.
1169 (new_element): Likewise.
1170 (skip_class_p): Likewise.
1171 (find_format_from_table): Use skip_class_p function.
1172 (find_format): Decode first the extension instructions.
1173 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1174 e_flags.
1175 (parse_option): New function.
1176 (parse_disassembler_options): Likewise.
1177 (print_arc_disassembler_options): Likewise.
1178 (print_insn_arc): Use parse_disassembler_options function. Proper
1179 select ARCv2 cpu variant.
1180 * disassemble.c (disassembler_usage): Add ARC disassembler
1181 options.
1182
92281a5b
MR		 11832016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1184
1185 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1186 annotation from the "nal" entry and reorder it beyond "bltzal".
1187
6e7ced37
JM		 11882016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1189
1190 * sparc-opc.c (ldtxa): New macro.
1191 (sparc_opcodes): Use the macro defined above to add entries for
1192 the LDTXA instructions.
1193 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1194 instruction.
1195
2f831b9a 11962016-07-07 James Bowman <james.bowman@ftdichip.com>
1197
1198 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1199 and "jmpc".
1200
c07315e0
JB		 12012016-07-01 Jan Beulich <jbeulich@suse.com>
1202
1203 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1204 (movzb): Adjust to cover all permitted suffixes.
1205 (movzw): New.
1206 * i386-tbl.h: Re-generate.
1207
9243100a
JB		 12082016-07-01 Jan Beulich <jbeulich@suse.com>
1209
1210 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1211 (lgdt): Remove Tbyte from non-64-bit variant.
1212 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1213 xsaves64, xsavec64): Remove Disp16.
1214 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1215 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1216 64-bit variants.
1217 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1218 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1219 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1220 64-bit variants.
1221 * i386-tbl.h: Re-generate.
1222
8325cc63
JB		 12232016-07-01 Jan Beulich <jbeulich@suse.com>
1224
1225 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1226 * i386-tbl.h: Re-generate.
1227
838441e4
YQ		 12282016-06-30 Yao Qi <yao.qi@linaro.org>
1229
1230 * arm-dis.c (print_insn): Fix typo in comment.
1231
dab26bf4
RS		 12322016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1233
1234 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1235 range of ldst_elemlist operands.
1236 (print_register_list): Use PRIi64 to print the index.
1237 (aarch64_print_operand): Likewise.
1238
5703197e
TS		 12392016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1240
1241 * mcore-opc.h: Remove sentinal.
1242 * mcore-dis.c (print_insn_mcore): Adjust.
1243
ce440d63
GM		 12442016-06-23 Graham Markall <graham.markall@embecosm.com>
1245
1246 * arc-opc.c: Correct description of availability of NPS400
1247 features.
1248
6fd3a02d
PB		 12492016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1250
1251 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1252 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1253 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1254 xor3>: New mnemonics.
1255 <setb>: Change to a VX form instruction.
1256 (insert_sh6): Add support for rldixor.
1257 (extract_sh6): Likewise.
1258
6b477896
TS		 12592016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1260
1261 * arc-ext.h: Wrap in extern C.
1262
bdd582db
GM		 12632016-06-21 Graham Markall <graham.markall@embecosm.com>
1264
1265 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1266 Use same method for determining instruction length on ARC700 and
1267 NPS-400.
1268 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1269 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1270 with the NPS400 subclass.
1271 * arc-opc.c: Likewise.
1272
96074adc
JM		 12732016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1274
1275 * sparc-opc.c (rdasr): New macro.
1276 (wrasr): Likewise.
1277 (rdpr): Likewise.
1278 (wrpr): Likewise.
1279 (rdhpr): Likewise.
1280 (wrhpr): Likewise.
1281 (sparc_opcodes): Use the macros above to fix and expand the
1282 definition of read/write instructions from/to
1283 asr/privileged/hyperprivileged instructions.
1284 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1285 %hva_mask_nz. Prefer softint_set and softint_clear over
1286 set_softint and clear_softint.
1287 (print_insn_sparc): Support %ver in Rd.
1288
7a10c22f
JM		 12892016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1290
1291 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1292 architecture according to the hardware capabilities they require.
1293
4f26fb3a
JM		 12942016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1295
1296 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1297 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1298 bfd_mach_sparc_v9{c,d,e,v,m}.
1299 * sparc-opc.c (MASK_V9C): Define.
1300 (MASK_V9D): Likewise.
1301 (MASK_V9E): Likewise.
1302 (MASK_V9V): Likewise.
1303 (MASK_V9M): Likewise.
1304 (v6): Add MASK_V9{C,D,E,V,M}.
1305 (v6notlet): Likewise.
1306 (v7): Likewise.
1307 (v8): Likewise.
1308 (v9): Likewise.
1309 (v9andleon): Likewise.
1310 (v9a): Likewise.
1311 (v9b): Likewise.
1312 (v9c): Define.
1313 (v9d): Likewise.
1314 (v9e): Likewise.
1315 (v9v): Likewise.
1316 (v9m): Likewise.
1317 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1318
3ee6e4fb
NC		 13192016-06-15 Nick Clifton <nickc@redhat.com>
1320
1321 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1322 constants to match expected behaviour.
1323 (nds32_parse_opcode): Likewise. Also for whitespace.
1324
02f3be19
AB		 13252016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1326
1327 * arc-opc.c (extract_rhv1): Extract value from insn.
1328
6f9f37ed 13292016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1330
1331 * arc-nps400-tbl.h: Add ldbit instruction.
1332 * arc-opc.c: Add flag classes required for ldbit.
1333
6f9f37ed 13342016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1335
1336 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1337 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1338 support the above instructions.
1339
6f9f37ed 13402016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1341
1342 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1343 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1344 csma, cbba, zncv, and hofs.
1345 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1346 support the above instructions.
1347
13482016-06-06 Graham Markall <graham.markall@embecosm.com>
1349
1350 * arc-nps400-tbl.h: Add andab and orab instructions.
1351
13522016-06-06 Graham Markall <graham.markall@embecosm.com>
1353
1354 * arc-nps400-tbl.h: Add addl-like instructions.
1355
13562016-06-06 Graham Markall <graham.markall@embecosm.com>
1357
1358 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1359
13602016-06-06 Graham Markall <graham.markall@embecosm.com>
1361
1362 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1363 instructions.
1364
b2cc3f6f
AK		 13652016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1366
1367 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1368 variable.
1369 (init_disasm): Handle new command line option "insnlength".
1370 (print_s390_disassembler_options): Mention new option in help
1371 output.
1372 (print_insn_s390): Use the encoded insn length when dumping
1373 unknown instructions.
1374
1857fe72
DC		 13752016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1376
1377 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1378 to the address and set as symbol address for LDS/ STS immediate operands.
1379
14b57c7c
AM		 13802016-06-07 Alan Modra <amodra@gmail.com>
1381
1382 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1383 cpu for "vle" to e500.
1384 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1385 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1386 (PPCNONE): Delete, substitute throughout.
1387 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1388 except for major opcode 4 and 31.
1389 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1390
4d1464f2
MW		 13912016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1392
1393 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1394 ARM_EXT_RAS in relevant entries.
1395
026122a6
PB		 13962016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1397
1398 PR binutils/20196
1399 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1400 opcodes for E6500.
1401
07f5af7d
L		 14022016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1403
1404 PR binutis/18386
1405 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1406 (indir_v_mode): New.
1407 Add comments for '&'.
1408 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1409 (putop): Handle '&'.
1410 (intel_operand_size): Handle indir_v_mode.
1411 (OP_E_register): Likewise.
1412 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1413 64-bit indirect call/jmp for AMD64.
1414 * i386-tbl.h: Regenerated
1415
4eb6f892
AB		 14162016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1417
1418 * arc-dis.c (struct arc_operand_iterator): New structure.
1419 (find_format_from_table): All the old content from find_format,
1420 with some minor adjustments, and parameter renaming.
1421 (find_format_long_instructions): New function.
1422 (find_format): Rewritten.
1423 (arc_insn_length): Add LSB parameter.
1424 (extract_operand_value): New function.
1425 (operand_iterator_next): New function.
1426 (print_insn_arc): Use new functions to find opcode, and iterator
1427 over operands.
1428 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1429 (extract_nps_3bit_dst_short): New function.
1430 (insert_nps_3bit_src2_short): New function.
1431 (extract_nps_3bit_src2_short): New function.
1432 (insert_nps_bitop1_size): New function.
1433 (extract_nps_bitop1_size): New function.
1434 (insert_nps_bitop2_size): New function.
1435 (extract_nps_bitop2_size): New function.
1436 (insert_nps_bitop_mod4_msb): New function.
1437 (extract_nps_bitop_mod4_msb): New function.
1438 (insert_nps_bitop_mod4_lsb): New function.
1439 (extract_nps_bitop_mod4_lsb): New function.
1440 (insert_nps_bitop_dst_pos3_pos4): New function.
1441 (extract_nps_bitop_dst_pos3_pos4): New function.
1442 (insert_nps_bitop_ins_ext): New function.
1443 (extract_nps_bitop_ins_ext): New function.
1444 (arc_operands): Add new operands.
1445 (arc_long_opcodes): New global array.
1446 (arc_num_long_opcodes): New global.
1447 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1448
1fe0971e
TS		 14492016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1450
1451 * nds32-asm.h: Add extern "C".
1452 * sh-opc.h: Likewise.
1453
315f180f
GM		 14542016-06-01 Graham Markall <graham.markall@embecosm.com>
1455
1456 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1457 0,b,limm to the rflt instruction.
1458
a2b5fccc
TS		 14592016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1460
1461 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1462 constant.
1463
0cbd0046
L		 14642016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1465
1466 PR gas/20145
1467 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1468 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1469 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1470 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1471 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1472 * i386-init.h: Regenerated.
1473
1848e567
L		 14742016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1475
1476 PR gas/20145
1477 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1478 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1479 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1480 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1481 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1482 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1483 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1484 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1485 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1486 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1487 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1488 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1489 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1490 CpuRegMask for AVX512.
1491 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1492 and CpuRegMask.
1493 (set_bitfield_from_cpu_flag_init): New function.
1494 (set_bitfield): Remove const on f. Call
1495 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1496 * i386-opc.h (CpuRegMMX): New.
1497 (CpuRegXMM): Likewise.
1498 (CpuRegYMM): Likewise.
1499 (CpuRegZMM): Likewise.
1500 (CpuRegMask): Likewise.
1501 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1502 and cpuregmask.
1503 * i386-init.h: Regenerated.
1504 * i386-tbl.h: Likewise.
1505
e92bae62
L		 15062016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1507
1508 PR gas/20154
1509 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1510 (opcode_modifiers): Add AMD64 and Intel64.
1511 (main): Properly verify CpuMax.
1512 * i386-opc.h (CpuAMD64): Removed.
1513 (CpuIntel64): Likewise.
1514 (CpuMax): Set to CpuNo64.
1515 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1516 (AMD64): New.
1517 (Intel64): Likewise.
1518 (i386_opcode_modifier): Add amd64 and intel64.
1519 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1520 on call and jmp.
1521 * i386-init.h: Regenerated.
1522 * i386-tbl.h: Likewise.
1523
e89c5eaa
L		 15242016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1525
1526 PR gas/20154
1527 * i386-gen.c (main): Fail if CpuMax is incorrect.
1528 * i386-opc.h (CpuMax): Set to CpuIntel64.
1529 * i386-tbl.h: Regenerated.
1530
77d66e7b
NC		 15312016-05-27 Nick Clifton <nickc@redhat.com>
1532
1533 PR target/20150
1534 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1535 (msp430dis_opcode_unsigned): New function.
1536 (msp430dis_opcode_signed): New function.
1537 (msp430_singleoperand): Use the new opcode reading functions.
1538 Only disassenmble bytes if they were successfully read.
1539 (msp430_doubleoperand): Likewise.
1540 (msp430_branchinstr): Likewise.
1541 (msp430x_callx_instr): Likewise.
1542 (print_insn_msp430): Check that it is safe to read bytes before
1543 attempting disassembly. Use the new opcode reading functions.
1544
19dfcc89
PB		 15452016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1546
1547 * ppc-opc.c (CY): New define. Document it.
1548 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1549
f3ad7637
L		 15502016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1551
1552 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1553 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1554 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1555 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1556 CPU_ANY_AVX_FLAGS.
1557 * i386-init.h: Regenerated.
1558
f1360d58
L		 15592016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1560
1561 PR gas/20141
1562 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1563 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1564 * i386-init.h: Regenerated.
1565
293f5f65
L		 15662016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1567
1568 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1569 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1570 * i386-init.h: Regenerated.
1571
d9eca1df
CZ		 15722016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1573
1574 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1575 information.
1576 (print_insn_arc): Set insn_type information.
1577 * arc-opc.c (C_CC): Add F_CLASS_COND.
1578 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1579 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1580 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1581 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1582 (brne, brne_s, jeq_s, jne_s): Likewise.
1583
87789e08
CZ		 15842016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1585
1586 * arc-tbl.h (neg): New instruction variant.
1587
c810e0b8
CZ		 15882016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1589
1590 * arc-dis.c (find_format, find_format, get_auxreg)
1591 (print_insn_arc): Changed.
1592 * arc-ext.h (INSERT_XOP): Likewise.
1593
3d207518
TS		 15942016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1595
1596 * tic54x-dis.c (sprint_mmr): Adjust.
1597 * tic54x-opc.c: Likewise.
1598
514e58b7
AM		 15992016-05-19 Alan Modra <amodra@gmail.com>
1600
1601 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1602
e43de63c
AM		 16032016-05-19 Alan Modra <amodra@gmail.com>
1604
1605 * ppc-opc.c: Formatting.
1606 (NSISIGNOPT): Define.
1607 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1608
1401d2fe
MR		 16092016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1610
1611 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1612 replacing references to `micromips_ase' throughout.
1613 (_print_insn_mips): Don't use file-level microMIPS annotation to
1614 determine the disassembly mode with the symbol table.
1615
1178da44
PB		 16162016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1617
1618 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1619
8f4f9071
MF		 16202016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1621
1622 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1623 mips64r6.
1624 * mips-opc.c (D34): New macro.
1625 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1626
8bc52696
AF		 16272016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1628
1629 * i386-dis.c (prefix_table): Add RDPID instruction.
1630 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1631 (cpu_flags): Add RDPID bitfield.
1632 * i386-opc.h (enum): Add RDPID element.
1633 (i386_cpu_flags): Add RDPID field.
1634 * i386-opc.tbl: Add RDPID instruction.
1635 * i386-init.h: Regenerate.
1636 * i386-tbl.h: Regenerate.
1637
39d911fc
TP		 16382016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1639
1640 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1641 branch type of a symbol.
1642 (print_insn): Likewise.
1643
16a1fa25
TP		 16442016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1645
1646 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1647 Mainline Security Extensions instructions.
1648 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1649 Extensions instructions.
1650 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1651 instructions.
1652 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1653 special registers.
1654
d751b79e
JM		 16552016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1656
1657 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1658
945e0f82
CZ		 16592016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1660
1661 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1662 (arcExtMap_genOpcode): Likewise.
1663 * arc-opc.c (arg_32bit_rc): Define new variable.
1664 (arg_32bit_u6): Likewise.
1665 (arg_32bit_limm): Likewise.
1666
20f55f38
SN		 16672016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1668
1669 * aarch64-gen.c (VERIFIER): Define.
1670 * aarch64-opc.c (VERIFIER): Define.
1671 (verify_ldpsw): Use static linkage.
1672 * aarch64-opc.h (verify_ldpsw): Remove.
1673 * aarch64-tbl.h: Use VERIFIER for verifiers.
1674
4bd13cde
NC		 16752016-04-28 Nick Clifton <nickc@redhat.com>
1676
1677 PR target/19722
1678 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1679 * aarch64-opc.c (verify_ldpsw): New function.
1680 * aarch64-opc.h (verify_ldpsw): New prototype.
1681 * aarch64-tbl.h: Add initialiser for verifier field.
1682 (LDPSW): Set verifier to verify_ldpsw.
1683
c0f92bf9
L		 16842016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1685
1686 PR binutils/19983
1687 PR binutils/19984
1688 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1689 smaller than address size.
1690
e6c7cdec
TS		 16912016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1692
1693 * alpha-dis.c: Regenerate.
1694 * crx-dis.c: Likewise.
1695 * disassemble.c: Likewise.
1696 * epiphany-opc.c: Likewise.
1697 * fr30-opc.c: Likewise.
1698 * frv-opc.c: Likewise.
1699 * ip2k-opc.c: Likewise.
1700 * iq2000-opc.c: Likewise.
1701 * lm32-opc.c: Likewise.
1702 * lm32-opinst.c: Likewise.
1703 * m32c-opc.c: Likewise.
1704 * m32r-opc.c: Likewise.
1705 * m32r-opinst.c: Likewise.
1706 * mep-opc.c: Likewise.
1707 * mt-opc.c: Likewise.
1708 * or1k-opc.c: Likewise.
1709 * or1k-opinst.c: Likewise.
1710 * tic80-opc.c: Likewise.
1711 * xc16x-opc.c: Likewise.
1712 * xstormy16-opc.c: Likewise.
1713
537aefaf
AB		 17142016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1715
1716 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1717 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1718 calcsd, and calcxd instructions.
1719 * arc-opc.c (insert_nps_bitop_size): Delete.
1720 (extract_nps_bitop_size): Delete.
1721 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1722 (extract_nps_qcmp_m3): Define.
1723 (extract_nps_qcmp_m2): Define.
1724 (extract_nps_qcmp_m1): Define.
1725 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1726 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1727 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1728 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1729 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1730 NPS_QCMP_M3.
1731
c8f785f2
AB		 17322016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1733
1734 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1735
6fd8e7c2
L		 17362016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1737
1738 * Makefile.in: Regenerated with automake 1.11.6.
1739 * aclocal.m4: Likewise.
1740
4b0c052e
AB		 17412016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1742
1743 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1744 instructions.
1745 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1746 (extract_nps_cmem_uimm16): New function.
1747 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1748
cb040366
AB		 17492016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1750
1751 * arc-dis.c (arc_insn_length): New function.
1752 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1753 (find_format): Change insnLen parameter to unsigned.
1754
accc0180
NC		 17552016-04-13 Nick Clifton <nickc@redhat.com>
1756
1757 PR target/19937
1758 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1759 the LD.B and LD.BU instructions.
1760
f36e33da
CZ		 17612016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1762
1763 * arc-dis.c (find_format): Check for extension flags.
1764 (print_flags): New function.
1765 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1766 .extAuxRegister.
1767 * arc-ext.c (arcExtMap_coreRegName): Use
1768 LAST_EXTENSION_CORE_REGISTER.
1769 (arcExtMap_coreReadWrite): Likewise.
1770 (dump_ARC_extmap): Update printing.
1771 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1772 (arc_aux_regs): Add cpu field.
1773 * arc-regs.h: Add cpu field, lower case name aux registers.
1774
1c2e355e
CZ		 17752016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1776
1777 * arc-tbl.h: Add rtsc, sleep with no arguments.
1778
b99747ae
CZ		 17792016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1780
1781 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1782 Initialize.
1783 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1784 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1785 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1786 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1787 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1788 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1789 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1790 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1791 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1792 (arc_opcode arc_opcodes): Null terminate the array.
1793 (arc_num_opcodes): Remove.
1794 * arc-ext.h (INSERT_XOP): Define.
1795 (extInstruction_t): Likewise.
1796 (arcExtMap_instName): Delete.
1797 (arcExtMap_insn): New function.
1798 (arcExtMap_genOpcode): Likewise.
1799 * arc-ext.c (ExtInstruction): Remove.
1800 (create_map): Zero initialize instruction fields.
1801 (arcExtMap_instName): Remove.
1802 (arcExtMap_insn): New function.
1803 (dump_ARC_extmap): More info while debuging.
1804 (arcExtMap_genOpcode): New function.
1805 * arc-dis.c (find_format): New function.
1806 (print_insn_arc): Use find_format.
1807 (arc_get_disassembler): Enable dump_ARC_extmap only when
1808 debugging.
1809
92708cec
MR		 18102016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1811
1812 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1813 instruction bits out.
1814
a42a4f84
AB		 18152016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1816
1817 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1818 * arc-opc.c (arc_flag_operands): Add new flags.
1819 (arc_flag_classes): Add new classes.
1820
1328504b
AB		 18212016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1822
1823 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1824
820f03ff
AB		 18252016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1826
1827 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1828 encode1, rflt, crc16, and crc32 instructions.
1829 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1830 (arc_flag_classes): Add C_NPS_R.
1831 (insert_nps_bitop_size_2b): New function.
1832 (extract_nps_bitop_size_2b): Likewise.
1833 (insert_nps_bitop_uimm8): Likewise.
1834 (extract_nps_bitop_uimm8): Likewise.
1835 (arc_operands): Add new operand entries.
1836
8ddf6b2a
CZ		 18372016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1838
b99747ae
CZ		 1839 * arc-regs.h: Add a new subclass field. Add double assist
1840 accumulator register values.
1841 * arc-tbl.h: Use DPA subclass to mark the double assist
1842 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1843 * arc-opc.c (RSP): Define instead of SP.
1844 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1845
589a7d88
JW		 18462016-04-05 Jiong Wang <jiong.wang@arm.com>
1847
1848 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1849
0a191de9 18502016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1851
1852 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1853 NPS_R_SRC1.
1854
0a106562
AB		 18552016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1856
1857 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1858 issues. No functional changes.
1859
bd05ac5f
CZ		 18602016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1861
b99747ae
CZ		 1862 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1863 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1864 (RTT): Remove duplicate.
1865 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1866 (PCT_CONFIG*): Remove.
1867 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1868
9885948f
CZ		 18692016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1870
b99747ae 1871 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1872
f2dd8838
CZ		 18732016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1874
b99747ae
CZ		 1875 * arc-tbl.h (invld07): Remove.
1876 * arc-ext-tbl.h: New file.
1877 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1878 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1879
0d2f91fe
JK		 18802016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1881
1882 Fix -Wstack-usage warnings.
1883 * aarch64-dis.c (print_operands): Substitute size.
1884 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1885
a6b71f42
JM		 18862016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1887
1888 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1889 to get a proper diagnostic when an invalid ASR register is used.
1890
9780e045
NC		 18912016-03-22 Nick Clifton <nickc@redhat.com>
1892
1893 * configure: Regenerate.
1894
e23e8ebe
AB		 18952016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1896
1897 * arc-nps400-tbl.h: New file.
1898 * arc-opc.c: Add top level comment.
1899 (insert_nps_3bit_dst): New function.
1900 (extract_nps_3bit_dst): New function.
1901 (insert_nps_3bit_src2): New function.
1902 (extract_nps_3bit_src2): New function.
1903 (insert_nps_bitop_size): New function.
1904 (extract_nps_bitop_size): New function.
1905 (arc_flag_operands): Add nps400 entries.
1906 (arc_flag_classes): Add nps400 entries.
1907 (arc_operands): Add nps400 entries.
1908 (arc_opcodes): Add nps400 include.
1909
1ae8ab47
AB		 19102016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1911
1912 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1913 the new class enum values.
1914
8699fc3e
AB		 19152016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1916
1917 * arc-dis.c (print_insn_arc): Handle nps400.
1918
24740d83
AB		 19192016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1920
1921 * arc-opc.c (BASE): Delete.
1922
8678914f
NC		 19232016-03-18 Nick Clifton <nickc@redhat.com>
1924
1925 PR target/19721
1926 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1927 of MOV insn that aliases an ORR insn.
1928
cc933301
JW		 19292016-03-16 Jiong Wang <jiong.wang@arm.com>
1930
1931 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1932
f86f5863
TS		 19332016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1934
1935 * mcore-opc.h: Add const qualifiers.
1936 * microblaze-opc.h (struct op_code_struct): Likewise.
1937 * sh-opc.h: Likewise.
1938 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1939 (tic4x_print_op): Likewise.
1940
62de1c63
AM		 19412016-03-02 Alan Modra <amodra@gmail.com>
1942
d11698cd 1943 * or1k-desc.h: Regenerate.
62de1c63 1944 * fr30-ibld.c: Regenerate.
c697cf0b 1945 * rl78-decode.c: Regenerate.
62de1c63 1946
020efce5
NC		 19472016-03-01 Nick Clifton <nickc@redhat.com>
1948
1949 PR target/19747
1950 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1951
b0c11777
RL		 19522016-02-24 Renlin Li <renlin.li@arm.com>
1953
1954 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1955 (print_insn_coprocessor): Support fp16 instructions.
1956
3e309328
RL		 19572016-02-24 Renlin Li <renlin.li@arm.com>
1958
1959 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1960 vminnm, vrint(mpna).
1961
8afc7bea
RL		 19622016-02-24 Renlin Li <renlin.li@arm.com>
1963
1964 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1965 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1966
4fd7268a
L		 19672016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1968
1969 * i386-dis.c (print_insn): Parenthesize expression to prevent
1970 truncated addresses.
1971 (OP_J): Likewise.
1972
4670103e
CZ		 19732016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1974 Janek van Oirschot <jvanoirs@synopsys.com>
1975
b99747ae
CZ		 1976 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1977 variable.
4670103e 1978
c1d9289f
NC		 19792016-02-04 Nick Clifton <nickc@redhat.com>
1980
1981 PR target/19561
1982 * msp430-dis.c (print_insn_msp430): Add a special case for
1983 decoding an RRC instruction with the ZC bit set in the extension
1984 word.
1985
a143b004
AB		 19862016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1987
1988 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1989 * epiphany-ibld.c: Regenerate.
1990 * fr30-ibld.c: Regenerate.
1991 * frv-ibld.c: Regenerate.
1992 * ip2k-ibld.c: Regenerate.
1993 * iq2000-ibld.c: Regenerate.
1994 * lm32-ibld.c: Regenerate.
1995 * m32c-ibld.c: Regenerate.
1996 * m32r-ibld.c: Regenerate.
1997 * mep-ibld.c: Regenerate.
1998 * mt-ibld.c: Regenerate.
1999 * or1k-ibld.c: Regenerate.
2000 * xc16x-ibld.c: Regenerate.
2001 * xstormy16-ibld.c: Regenerate.
2002
b89807c6
AB		 20032016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2004
2005 * epiphany-dis.c: Regenerated from latest cpu files.
2006
d8c823c8
MM		 20072016-02-01 Michael McConville <mmcco@mykolab.com>
2008
2009 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2010 test bit.
2011
5bc5ae88
RL		 20122016-01-25 Renlin Li <renlin.li@arm.com>
2013
2014 * arm-dis.c (mapping_symbol_for_insn): New function.
2015 (find_ifthen_state): Call mapping_symbol_for_insn().
2016
0bff6e2d
MW		 20172016-01-20 Matthew Wahab <matthew.wahab@arm.com>
2018
2019 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2020 of MSR UAO immediate operand.
2021
100b4f2e
MR		 20222016-01-18 Maciej W. Rozycki <macro@imgtec.com>
2023
2024 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2025 instruction support.
2026
5c14705f
AM		 20272016-01-17 Alan Modra <amodra@gmail.com>
2028
2029 * configure: Regenerate.
2030
4d82fe66
NC		 20312016-01-14 Nick Clifton <nickc@redhat.com>
2032
2033 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2034 instructions that can support stack pointer operations.
2035 * rl78-decode.c: Regenerate.
2036 * rl78-dis.c: Fix display of stack pointer in MOVW based
2037 instructions.
2038
651657fa
MW		 20392016-01-14 Matthew Wahab <matthew.wahab@arm.com>
2040
2041 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2042 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
2043 erxtatus_el1 and erxaddr_el1.
2044
105bde57
MW		 20452016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2046
2047 * arm-dis.c (arm_opcodes): Add "esb".
2048 (thumb_opcodes): Likewise.
2049
afa8d405
PB		 20502016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2051
2052 * ppc-opc.c <xscmpnedp>: Delete.
2053 <xvcmpnedp>: Likewise.
2054 <xvcmpnedp.>: Likewise.
2055 <xvcmpnesp>: Likewise.
2056 <xvcmpnesp.>: Likewise.
2057
83c3256e
AS		 20582016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2059
2060 PR gas/13050
2061 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2062 addition to ISA_A.
2063
6f2750fe
AM		 20642016-01-01 Alan Modra <amodra@gmail.com>
2065
2066 Update year range in copyright notice of all files.
2067
3499769a
AM		 2068For older changes see ChangeLog-2015
2069\f
2070Copyright (C) 2016 Free Software Foundation, Inc.
2071
2072Copying and distribution of this file, with or without modification,
2073are permitted in any medium without royalty provided the copyright
2074notice and this notice are preserved.
2075
2076Local Variables:
2077mode: change-log
2078left-margin: 8
2079fill-column: 74
2080version-control: never
2081End:
GDB Binutils - Deliverables
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