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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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87b8eed7
YZ		 12013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
2
3 * aarch64-opc.c (aarch64_pstatefields): Update.
4
8f8c3854
CM		 52013-11-19 Catherine Moore <clm@codesourcery.com>
6
7 * micromips-opc.c (LM): Define.
8 (micromips_opcodes): Add LM to load instructions.
9 * mips-opc.c (prefe): Add LM attribute.
10
a203d9b7
YZ		 112013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
12
13 Revert
14
15 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
16
17 * aarch64-opc.c (CPENT): New define.
18 (F_READONLY, F_WRITEONLY): Likewise.
19 (aarch64_sys_regs): Add trace unit registers.
20 (aarch64_sys_reg_readonly_p): New function.
21 (aarch64_sys_reg_writeonly_p): Ditto.
22
75468c93
YZ		 232013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
24
25 * aarch64-opc.c (CPENT): New define.
26 (F_READONLY, F_WRITEONLY): Likewise.
27 (aarch64_sys_regs): Add trace unit registers.
28 (aarch64_sys_reg_readonly_p): New function.
29 (aarch64_sys_reg_writeonly_p): Ditto.
30
caeba11c
MR		 312013-11-15 Maciej W. Rozycki <macro@codesourcery.com>
32
33 * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
34 "mtcr".
35
b83a9376
CM		 362013-11-11 Catherine Moore <clm@codesourcery.com>
37
38 * mips-dis.c (print_insn_mips): Use
39 INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
40 (print_insn_micromips): Likewise.
41 * mips-opc.c (LDD): Remove.
42 (CLD): Include INSN_LOAD_MEMORY.
43 (LM): New.
44 (mips_builtin_opcodes): Use LM instead of LDD.
45 Add LM to load instructions.
46
d56da83e
L		 472013-11-08 H.J. Lu <hongjiu.lu@intel.com>
48
49 PR gas/16140
50 * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
51 * i386-init.h: Regenerated.
52
49eec193
YZ		 532013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
54
55 * aarch64-opc.c (F_DEPRECATED): New macro.
56 (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
57 F_DEPRECATED.
58 (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
59 AARCH64_OPND_SYSREG.
60
68a64283
YZ		 612013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
62
63 * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
64 (convert_from_csel): Likewise.
65 * aarch64-opc.c (operand_general_constraint_met_p): Handle
66 AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
67 (aarch64_print_operand): Handle AARCH64_OPND_COND1.
68 * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
69 COND for cinc, cset, cinv, csetm and cneg.
70 (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
71 * aarch64-asm-2.c: Re-generated.
72 * aarch64-dis-2.c: Ditto.
73 * aarch64-opc-2.c: Ditto.
74
4e50d5f8
YZ		 752013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
76
77 * aarch64-opc.c (set_syntax_error): New function.
78 (operand_general_constraint_met_p): Replace set_other_error
79 with set_syntax_error.
80
7d4a7d10
AA		 812013-10-30 Andreas Arnez <arnez@linux.vnet.ibm.com>
82
83 * s390-dis.c (init_disasm): Default to full 'zarch' opcode
84 availability even for 31-bit programs.
85
85181173
RR		 862013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
87
88 * arm-dis.c (neon_opcodes): Adjust print string for vshll.
89
4edbb8e3
CF		 902013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
91
92 * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
93 +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
94 +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
95 (MSA): New define.
96 (MSA64): New define.
97 (micromips_opcodes): Add MSA instructions.
98 * mips-dis.c (msa_control_names): New array.
99 (mips_abi_choice): Add ASE_MSA to mips32r2.
100 Remove ASE_MDMX from mips64r2.
101 Add ASE_MSA and ASE_MSA64 to mips64r2.
102 (parse_mips_dis_option): Handle -Mmsa.
103 (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
104 (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
105 (print_mips_disassembler_options): Print -Mmsa.
106 * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
107 +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
108 (MSA): New define.
109 (MSA64): New define.
110 (mips_builtin_op): Add MSA instructions.
111
ae335a4e
SL		 1122013-10-13 Sandra Loosemore <sandra@codesourcery.com>
113
114 * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
115 as the primary name of r30.
116
6c75cc62
L		 1172013-10-12 Jan Beulich <jbeulich@suse.com>
118
119 * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
120 default case.
121 (OP_E_register): Move v_bnd_mode alongside m_mode.
122 * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
123 Drop Reg16 and Disp16. Add NoRex64.
124 (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
125 * i386-tbl.h: Re-generate.
126
0e1c2434
SK		 1272013-10-10 Sean Keys <skeys@ipdatasys.com>
128
129 * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
130 table.
131 * xgate-dis.c (print_insn): Refactor to work with table change.
132
7903e530
RM		 1332013-10-10 Roland McGrath <mcgrathr@google.com>
134
9ce09ba2
RM		 135 * i386-dis.c (oappend_maybe_intel): New function.
136 (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
137 (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
138 (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
139
2b4e983c
RM		 140 * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
141 possible compiler warnings when the union's initializer is
142 actually meant for the 'preg' enum typed member.
143 * crx-opc.c (REG): Likewise.
144
7903e530
RM		 145 * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
146 Remove duplicate const qualifier.
147
79e0e31d
JB		 1482013-10-08 Jan Beulich <jbeulich@suse.com>
149
150 * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
151 (clflush): Use Anysize instead of Byte|Unspecified.
152 (prefetch*): Likewise.
153 * i386-tbl.h: Re-generate.
154
45099dfa
CF		 1552013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
156
157 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
158
916fae91
L		 1592013-09-30 H.J. Lu <hongjiu.lu@intel.com>
160
161 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
162 * i386-init.h: Regenerated.
163
c7b0bd56
SE		 1642013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
165
166 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
167 * i386-init.h: Regenerated.
168
cc9afea3
AM		 1692013-09-20 Alan Modra <amodra@gmail.com>
170
171 * configure: Regenerate.
172
e3f9e852
RS		 1732013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
174
175 * s390-opc.txt (clih): Make the immediate unsigned.
176
74db7efb
NC		 1772013-09-04 Roland McGrath <mcgrathr@google.com>
178
179 PR gas/15914
180 * arm-dis.c (arm_opcodes): Add udf.
181 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
182 (thumb32_opcodes): Add udf.w.
183 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
184
c8094e01
AK		 1852013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
186
187 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
188 For the load fp integer instructions only the suppression flag was
189 new with z196 version.
190
7e105031
NC		 1912013-08-28 Nick Clifton <nickc@redhat.com>
192
193 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
194 immediate is not suitable for the 32-bit ABI.
195
fb6f3895
MR		 1962013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
197
198 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
199 replacing NODS.
200
9aff4b7a
NC		 2012013-08-23 Yuri Chornoivan <yurchor@ukr.net>
202
203 PR binutils/15834
204 * aarch64-asm.c: Fix typos.
205 * aarch64-dis.c: Likewise.
206 * msp430-dis.c: Likewise.
207
5e0dc5ba
RS		 2082013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
209
210 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
211 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
212 Use +H rather than +C for the real "dext".
213 * mips-opc.c (mips_builtin_opcodes): Likewise.
214
0f35dbc4
RS		 2152013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
216
217 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
218 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
219 and OPTIONAL_MAPPED_REG.
220 * mips-opc.c (decode_mips_operand): Likewise.
221 * mips16-opc.c (decode_mips16_operand): Likewise.
222 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
223
79ceb7cb
L		 2242013-08-19 H.J. Lu <hongjiu.lu@intel.com>
225
226 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
227 (PREFIX_EVEX_0F3A3F): Likewise.
228 * i386-dis-evex.h (evex_table): Updated.
229
ee5734f0
RS		 2302013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
231
232 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
233 VCLIPW.
234
d6787ef9
EB		 2352013-08-05 Eric Botcazou <ebotcazou@adacore.com>
236 Konrad Eisele <konrad@gaisler.com>
237
238 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
239 bfd_mach_sparc.
240 * sparc-opc.c (MASK_LEON): Define.
241 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
242 (letandleon): New macro.
243 (v9andleon): Likewise.
244 (sparc_opc): Add leon.
245 (umac): Enable for letandleon.
246 (smac): Likewise.
247 (casa): Enable for v9andleon.
248 (cas): Likewise.
249 (casl): Likewise.
250
14daeee3
RS		 2512013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
252 Richard Sandiford <rdsandiford@googlemail.com>
253
254 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
255 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
256 (print_vu0_channel): New function.
257 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
258 (print_insn_args): Handle '#'.
259 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
260 * mips-opc.c (mips_vu0_channel_mask): New constant.
261 (decode_mips_operand): Handle new VU0 operand types.
262 (VU0, VU0CH): New macros.
263 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
264 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
265 Use "+6" rather than "G" for QMFC2 and QMTC2.
266
3ccad066
RS		 2672013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
268
269 * mips-formats.h (PCREL): Reorder parameters and update the definition
270 to match new mips_pcrel_operand layout.
271 (JUMP, JALX, BRANCH): Update accordingly.
272 * mips16-opc.c (decode_mips16_operand): Likewise.
273
df34fbcc
RS		 2742013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
275
276 * micromips-opc.c (WR_s): Delete.
277
fc76e730
RS		 2782013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
279
280 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
281 New macros.
282 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
283 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
284 (mips_builtin_opcodes): Use the new position-based read-write flags
285 instead of field-based ones. Use UDI for "udi..." instructions.
286 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
287 New macros.
288 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
289 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
290 (WR_SP, RD_16): New macros.
291 (RD_SP): Redefine as an INSN2_* flag.
292 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
293 (mips16_opcodes): Use the new position-based read-write flags
294 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
295 pinfo2 field.
296 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
297 New macros.
298 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
299 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
300 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
301 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
302 (micromips_opcodes): Use the new position-based read-write flags
303 instead of field-based ones.
304 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
305 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
306 of field-based flags.
307
26545944
RS		 3082013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
309
310 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
311 (WR_SP): Replace with...
312 (MOD_SP): ...this.
313 (mips16_opcodes): Update accordingly.
314 * mips-dis.c (print_insn_mips16): Likewise.
315
a8d92fc6
RS		 3162013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
317
318 * mips16-opc.c (mips16_opcodes): Reformat.
319
6a819047
RS		 3202013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
321
322 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
323 for operands that are hard-coded to $0.
324 * micromips-opc.c (micromips_opcodes): Likewise.
325
344c74a6
RS		 3262013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
327
328 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
329 for the single-operand forms of JALR and JALR.HB.
330 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
331 and JALRS.HB.
332
41989114
RS		 3332013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
334
335 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
336 instructions. Fix them to use WR_MACC instead of WR_CC and
337 add missing RD_MACCs.
338
6d075bce
RS		 3392013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
340
341 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
342
4f6ffcd3
PB		 3432013-07-29 Peter Bergner <bergner@vnet.ibm.com>
344
345 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
346
43234a1e
L		 3472013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
348 Alexander Ivchenko <alexander.ivchenko@intel.com>
349 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
350 Sergey Lega <sergey.s.lega@intel.com>
351 Anna Tikhonova <anna.tikhonova@intel.com>
352 Ilya Tocar <ilya.tocar@intel.com>
353 Andrey Turetskiy <andrey.turetskiy@intel.com>
354 Ilya Verbin <ilya.verbin@intel.com>
355 Kirill Yukhin <kirill.yukhin@intel.com>
356 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
357
358 * i386-dis-evex.h: New.
359 * i386-dis.c (OP_Rounding): New.
360 (VPCMP_Fixup): New.
361 (OP_Mask): New.
362 (Rdq): New.
363 (XMxmmq): New.
364 (EXdScalarS): New.
365 (EXymm): New.
366 (EXEvexHalfBcstXmmq): New.
367 (EXxmm_mdq): New.
368 (EXEvexXGscat): New.
369 (EXEvexXNoBcst): New.
370 (VPCMP): New.
371 (EXxEVexR): New.
372 (EXxEVexS): New.
373 (XMask): New.
374 (MaskG): New.
375 (MaskE): New.
376 (MaskR): New.
377 (MaskVex): New.
378 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
379 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
380 evex_rounding_mode, evex_sae_mode, mask_mode.
381 (USE_EVEX_TABLE): New.
382 (EVEX_TABLE): New.
383 (EVEX enum): New.
384 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
385 REG_EVEX_0F38C7.
386 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
387 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
388 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
389 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
390 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
391 MOD_EVEX_0F38C7_REG_6.
392 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
393 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
394 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
395 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
396 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
397 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
398 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
399 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
400 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
401 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
402 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
403 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
404 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
405 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
406 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
407 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
408 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
409 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
410 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
411 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
412 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
413 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
414 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
415 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
416 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
417 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
418 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
419 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
420 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
421 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
422 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
423 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
424 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
425 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
426 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
427 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
428 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
429 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
430 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
431 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
432 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
433 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
434 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
435 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
436 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
437 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
438 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
439 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
440 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
441 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
442 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
443 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
444 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
445 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
446 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
447 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
448 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
449 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
450 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
451 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
452 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
453 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
454 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
455 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
456 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
457 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
458 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
459 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
460 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
461 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
462 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
463 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
464 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
465 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
466 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
467 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
468 PREFIX_EVEX_0F3A55.
469 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
470 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
471 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
472 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
473 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
474 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
475 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
476 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
477 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
478 VEX_W_0F3A32_P_2_LEN_0.
479 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
480 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
481 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
482 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
483 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
484 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
485 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
486 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
487 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
488 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
489 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
490 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
491 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
492 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
493 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
494 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
495 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
496 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
497 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
498 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
499 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
500 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
501 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
502 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
503 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
504 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
505 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
506 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
507 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
508 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
509 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
510 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
511 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
512 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
513 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
514 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
515 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
516 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
517 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
518 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
519 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
520 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
521 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
522 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
523 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
524 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
525 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
526 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
527 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
528 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
529 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
530 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
531 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
532 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
533 (struct vex): Add fields evex, r, v, mask_register_specifier,
534 zeroing, ll, b.
535 (intel_names_xmm): Add upper 16 registers.
536 (att_names_xmm): Ditto.
537 (intel_names_ymm): Ditto.
538 (att_names_ymm): Ditto.
539 (names_zmm): New.
540 (intel_names_zmm): Ditto.
541 (att_names_zmm): Ditto.
542 (names_mask): Ditto.
543 (intel_names_mask): Ditto.
544 (att_names_mask): Ditto.
545 (names_rounding): Ditto.
546 (names_broadcast): Ditto.
547 (x86_64_table): Add escape to evex-table.
548 (reg_table): Include reg_table evex-entries from
549 i386-dis-evex.h. Fix prefetchwt1 instruction.
550 (prefix_table): Add entries for new instructions.
551 (vex_table): Ditto.
552 (vex_len_table): Ditto.
553 (vex_w_table): Ditto.
554 (mod_table): Ditto.
555 (get_valid_dis386): Properly handle new instructions.
556 (print_insn): Handle zmm and mask registers, print mask operand.
557 (intel_operand_size): Support EVEX, new modes and sizes.
558 (OP_E_register): Handle new modes.
559 (OP_E_memory): Ditto.
560 (OP_G): Ditto.
561 (OP_XMM): Ditto.
562 (OP_EX): Ditto.
563 (OP_VEX): Ditto.
564 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
565 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
566 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
567 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
568 CpuAVX512PF and CpuVREX.
569 (operand_type_init): Add OPERAND_TYPE_REGZMM,
570 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
571 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
572 StaticRounding, SAE, Disp8MemShift, NoDefMask.
573 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
574 * i386-init.h: Regenerate.
575 * i386-opc.h (CpuAVX512F): New.
576 (CpuAVX512CD): New.
577 (CpuAVX512ER): New.
578 (CpuAVX512PF): New.
579 (CpuVREX): New.
580 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
581 cpuavx512pf and cpuvrex fields.
582 (VecSIB): Add VecSIB512.
583 (EVex): New.
584 (Masking): New.
585 (VecESize): New.
586 (Broadcast): New.
587 (StaticRounding): New.
588 (SAE): New.
589 (Disp8MemShift): New.
590 (NoDefMask): New.
591 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
592 staticrounding, sae, disp8memshift and nodefmask.
593 (RegZMM): New.
594 (Zmmword): Ditto.
595 (Vec_Disp8): Ditto.
596 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
597 fields.
598 (RegVRex): New.
599 * i386-opc.tbl: Add AVX512 instructions.
600 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
601 registers, mask registers.
602 * i386-tbl.h: Regenerate.
603
1d2db237
RS		 6042013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
605
606 PR gas/15220
607 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
608 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
609
a0046408
L		 6102013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
611
612 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
613 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
614 PREFIX_0F3ACC.
615 (prefix_table): Updated.
616 (three_byte_table): Likewise.
617 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
618 (cpu_flags): Add CpuSHA.
619 (i386_cpu_flags): Add cpusha.
620 * i386-init.h: Regenerate.
621 * i386-opc.h (CpuSHA): New.
622 (CpuUnused): Restored.
623 (i386_cpu_flags): Add cpusha.
624 * i386-opc.tbl: Add SHA instructions.
625 * i386-tbl.h: Regenerate.
626
7e8b059b
L		 6272013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
628 Kirill Yukhin <kirill.yukhin@intel.com>
629 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
630
631 * i386-dis.c (BND_Fixup): New.
632 (Ebnd): New.
633 (Ev_bnd): New.
634 (Gbnd): New.
635 (BND): New.
636 (v_bnd_mode): New.
637 (bnd_mode): New.
c623f86c
L		 638 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
639 MOD_0F1B_PREFIX_1.
640 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 641 (dis tables): Replace XX with BND for near branch and call
642 instructions.
643 (prefix_table): Add new entries.
644 (mod_table): Likewise.
645 (names_bnd): New.
646 (intel_names_bnd): New.
647 (att_names_bnd): New.
648 (BND_PREFIX): New.
649 (prefix_name): Handle BND_PREFIX.
650 (print_insn): Initialize names_bnd.
651 (intel_operand_size): Handle new modes.
652 (OP_E_register): Likewise.
653 (OP_E_memory): Likewise.
654 (OP_G): Likewise.
655 * i386-gen.c (cpu_flag_init): Add CpuMPX.
656 (cpu_flags): Add CpuMPX.
657 (operand_type_init): Add RegBND.
658 (opcode_modifiers): Add BNDPrefixOk.
659 (operand_types): Add RegBND.
660 * i386-init.h: Regenerate.
661 * i386-opc.h (CpuMPX): New.
662 (CpuUnused): Comment out.
663 (i386_cpu_flags): Add cpumpx.
664 (BNDPrefixOk): New.
665 (i386_opcode_modifier): Add bndprefixok.
666 (RegBND): New.
667 (i386_operand_type): Add regbnd.
668 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
669 Add MPX instructions and bnd prefix.
670 * i386-reg.tbl: Add bnd0-bnd3 registers.
671 * i386-tbl.h: Regenerate.
672
b56e23fb
RS		 6732013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
674
675 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
676 ATTRIBUTE_UNUSED.
677
e7ae278d
RS		 6782013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
679
680 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
681 special rules.
682 * Makefile.in: Regenerate.
683 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
684 all fields. Reformat.
685
c3c07478
RS		 6862013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
687
688 * mips16-opc.c: Include mips-formats.h.
689 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
690 static arrays.
691 (decode_mips16_operand): New function.
692 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
693 (print_insn_arg): Handle OP_ENTRY_EXIT list.
694 Abort for OP_SAVE_RESTORE_LIST.
695 (print_mips16_insn_arg): Change interface. Use mips_operand
696 structures. Delete GET_OP_S. Move GET_OP definition to...
697 (print_insn_mips16): ...here. Call init_print_arg_state.
698 Update the call to print_mips16_insn_arg.
699
ab902481
RS		 7002013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
701
702 * mips-formats.h: New file.
703 * mips-opc.c: Include mips-formats.h.
704 (reg_0_map): New static array.
705 (decode_mips_operand): New function.
706 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
707 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
708 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
709 (int_c_map): New static arrays.
710 (decode_micromips_operand): New function.
711 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
712 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
713 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
714 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
715 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
716 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
717 (micromips_imm_b_map, micromips_imm_c_map): Delete.
718 (print_reg): New function.
719 (mips_print_arg_state): New structure.
720 (init_print_arg_state, print_insn_arg): New functions.
721 (print_insn_args): Change interface and use mips_operand structures.
722 Delete GET_OP_S. Move GET_OP definition to...
723 (print_insn_mips): ...here. Update the call to print_insn_args.
724 (print_insn_micromips): Use print_insn_args.
725
cc537e56
RS		 7262013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
727
728 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
729 in macros.
730
7a5f87ce
RS		 7312013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
732
733 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
734 ADDA.S, MULA.S and SUBA.S.
735
41741fa4
L		 7362013-07-08 H.J. Lu <hongjiu.lu@intel.com>
737
738 PR gas/13572
739 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
740 * i386-tbl.h: Regenerated.
741
f2ae14a1
RS		 7422013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
743
744 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
745 and SD A(B) macros up.
746 * micromips-opc.c (micromips_opcodes): Likewise.
747
04c9d415
RS		 7482013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
749
750 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
751 instructions.
752
5c324c16
RS		 7532013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
754
755 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
756 MDMX-like instructions.
757 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
758 printing "Q" operands for INSN_5400 instructions.
759
23e69e47
RS		 7602013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
761
762 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
763 "+S" for "cins".
764 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
765 Combine cases.
766
27c5c572
RS		 7672013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
768
769 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
770 "jalx".
771 * mips16-opc.c (mips16_opcodes): Likewise.
772 * micromips-opc.c (micromips_opcodes): Likewise.
773 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
774 (print_insn_mips16): Handle "+i".
775 (print_insn_micromips): Likewise. Conditionally preserve the
776 ISA bit for "a" but not for "+i".
777
e76ff5ab
RS		 7782013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
779
780 * micromips-opc.c (WR_mhi): Rename to..
781 (WR_mh): ...this.
782 (micromips_opcodes): Update "movep" entry accordingly. Replace
783 "mh,mi" with "mh".
784 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
785 (micromips_to_32_reg_h_map1): ...this.
786 (micromips_to_32_reg_i_map): Rename to...
787 (micromips_to_32_reg_h_map2): ...this.
788 (print_micromips_insn): Remove "mi" case. Print both registers
789 in the pair for "mh".
790
fa7616a4
RS		 7912013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
792
793 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
794 * micromips-opc.c (micromips_opcodes): Likewise.
795 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
796 and "+T" handling. Check for a "0" suffix when deciding whether to
797 use coprocessor 0 names. In that case, also check for ",H" selectors.
798
fb798c50
AK		 7992013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
800
801 * s390-opc.c (J12_12, J24_24): New macros.
802 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
803 (MASK_MII_UPI): Rename to MASK_MII_UPP.
804 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
805
58ae08f2
AM		 8062013-07-04 Alan Modra <amodra@gmail.com>
807
808 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
809
b5e04c2b
NC		 8102013-06-26 Nick Clifton <nickc@redhat.com>
811
812 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
813 field when checking for type 2 nop.
814 * rx-decode.c: Regenerate.
815
833794fc
MR		 8162013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
817
818 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
819 and "movep" macros.
820
1bbce132
MR		 8212013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
822
823 * mips-dis.c (is_mips16_plt_tail): New function.
824 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
825 word.
826 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
827
34c911a4
NC		 8282013-06-21 DJ Delorie <dj@redhat.com>
829
830 * msp430-decode.opc: New.
831 * msp430-decode.c: New/generated.
832 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
833 (MAINTAINER_CLEANFILES): Likewise.
834 Add rule to build msp430-decode.c frommsp430decode.opc
835 using the opc2c program.
836 * Makefile.in: Regenerate.
837 * configure.in: Add msp430-decode.lo to msp430 architecture files.
838 * configure: Regenerate.
839
b9eead84
YZ		 8402013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
841
842 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
843 (SYMTAB_AVAILABLE): Removed.
844 (#include "elf/aarch64.h): Ditto.
845
7f3c4072
CM		 8462013-06-17 Catherine Moore <clm@codesourcery.com>
847 Maciej W. Rozycki <macro@codesourcery.com>
848 Chao-Ying Fu <fu@mips.com>
849
850 * micromips-opc.c (EVA): Define.
851 (TLBINV): Define.
852 (micromips_opcodes): Add EVA opcodes.
853 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
854 (print_insn_args): Handle EVA offsets.
855 (print_insn_micromips): Likewise.
856 * mips-opc.c (EVA): Define.
857 (TLBINV): Define.
858 (mips_builtin_opcodes): Add EVA opcodes.
859
de40ceb6
AM		 8602013-06-17 Alan Modra <amodra@gmail.com>
861
862 * Makefile.am (mips-opc.lo): Add rules to create automatic
863 dependency files. Pass archdefs.
864 (micromips-opc.lo, mips16-opc.lo): Likewise.
865 * Makefile.in: Regenerate.
866
3531d549
DD		 8672013-06-14 DJ Delorie <dj@redhat.com>
868
869 * rx-decode.opc (rx_decode_opcode): Bit operations on
870 registers are 32-bit operations, not 8-bit operations.
871 * rx-decode.c: Regenerate.
872
ba92f7fb
CF		 8732013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
874
875 * micromips-opc.c (IVIRT): New define.
876 (IVIRT64): New define.
877 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
878 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
879
880 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
881 dmtgc0 to print cp0 names.
882
9daf7bab
SL		 8832013-06-09 Sandra Loosemore <sandra@codesourcery.com>
884
885 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
886 argument.
887
d301a56b
RS		 8882013-06-08 Catherine Moore <clm@codesourcery.com>
889 Richard Sandiford <rdsandiford@googlemail.com>
890
891 * micromips-opc.c (D32, D33, MC): Update definitions.
892 (micromips_opcodes): Initialize ase field.
893 * mips-dis.c (mips_arch_choice): Add ase field.
894 (mips_arch_choices): Initialize ase field.
895 (set_default_mips_dis_options): Declare and setup mips_ase.
896 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
897 MT32, MC): Update definitions.
898 (mips_builtin_opcodes): Initialize ase field.
899
a3dcb6c5
RS		 9002013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
901
902 * s390-opc.txt (flogr): Require a register pair destination.
903
6cf1d90c
AK		 9042013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
905
906 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
907 instruction format.
908
c77c0862
RS		 9092013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
910
911 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
912
c0637f3a
PB		 9132013-05-20 Peter Bergner <bergner@vnet.ibm.com>
914
915 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
916 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
917 XLS_MASK, PPCVSX2): New defines.
918 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
919 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
920 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
921 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
922 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
923 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
924 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
925 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
926 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
927 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
928 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
929 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
930 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
931 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
932 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
933 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
934 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
935 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
936 <lxvx, stxvx>: New extended mnemonics.
937
4934fdaf
AM		 9382013-05-17 Alan Modra <amodra@gmail.com>
939
940 * ia64-raw.tbl: Replace non-ASCII char.
941 * ia64-waw.tbl: Likewise.
942 * ia64-asmtab.c: Regenerate.
943
6091d651
SE		 9442013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
945
946 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
947 * i386-init.h: Regenerated.
948
d2865ed3
YZ		 9492013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
950
951 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
952 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
953 check from [0, 255] to [-128, 255].
954
b015e599
AP		 9552013-05-09 Andrew Pinski <apinski@cavium.com>
956
957 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
958 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
959 (parse_mips_dis_option): Handle the virt option.
960 (print_insn_args): Handle "+J".
961 (print_mips_disassembler_options): Print out message about virt64.
962 * mips-opc.c (IVIRT): New define.
963 (IVIRT64): New define.
964 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
965 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
966 Move rfe to the bottom as it conflicts with tlbgp.
967
9f0682fe
AM		 9682013-05-09 Alan Modra <amodra@gmail.com>
969
970 * ppc-opc.c (extract_vlesi): Properly sign extend.
971 (extract_vlensi): Likewise. Comment reason for setting invalid.
972
13761a11
NC		 9732013-05-02 Nick Clifton <nickc@redhat.com>
974
975 * msp430-dis.c: Add support for MSP430X instructions.
976
e3031850
SL		 9772013-04-24 Sandra Loosemore <sandra@codesourcery.com>
978
979 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
980 to "eccinj".
981
17310e56
NC		 9822013-04-17 Wei-chen Wang <cole945@gmail.com>
983
984 PR binutils/15369
985 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
986 of CGEN_CPU_ENDIAN.
987 (hash_insns_list): Likewise.
988
731df338
JK		 9892013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
990
991 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
992 warning workaround.
993
5f77db52
JB		 9942013-04-08 Jan Beulich <jbeulich@suse.com>
995
996 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
997 * i386-tbl.h: Re-generate.
998
0afd1215
DM		 9992013-04-06 David S. Miller <davem@davemloft.net>
1000
1001 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
1002 of an opcode, prefer the one with F_PREFERRED set.
1003 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
1004 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
1005 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
1006 mark existing mnenomics as aliases. Add "cc" suffix to edge
1007 instructions generating condition codes, mark existing mnenomics
1008 as aliases. Add "fp" prefix to VIS compare instructions, mark
1009 existing mnenomics as aliases.
1010
41702d50
NC		 10112013-04-03 Nick Clifton <nickc@redhat.com>
1012
1013 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
1014 destination address by subtracting the operand from the current
1015 address.
1016 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
1017 a positive value in the insn.
1018 (extract_u16_loop): Do not negate the returned value.
1019 (D16_LOOP): Add V850_INVERSE_PCREL flag.
1020
1021 (ceilf.sw): Remove duplicate entry.
1022 (cvtf.hs): New entry.
1023 (cvtf.sh): Likewise.
1024 (fmaf.s): Likewise.
1025 (fmsf.s): Likewise.
1026 (fnmaf.s): Likewise.
1027 (fnmsf.s): Likewise.
1028 (maddf.s): Restrict to E3V5 architectures.
1029 (msubf.s): Likewise.
1030 (nmaddf.s): Likewise.
1031 (nmsubf.s): Likewise.
1032
55cf16e1
L		 10332013-03-27 H.J. Lu <hongjiu.lu@intel.com>
1034
1035 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
1036 check address mode.
1037 (print_insn): Pass sizeflag to get_sib.
1038
51dcdd4d
NC		 10392013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
1040
1041 PR binutils/15068
1042 * tic6x-dis.c: Add support for displaying 16-bit insns.
1043
795b8e6b
NC		 10442013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
1045
1046 PR gas/15095
1047 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1048 individual msb and lsb halves in src1 & src2 fields. Discard the
1049 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1050 follow what Ti SDK does in that case as any value in the src1
1051 field yields the same output with SDK disassembler.
1052
314d60dd
ME		 10532013-03-12 Michael Eager <eager@eagercon.com>
1054
795b8e6b 1055 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 1056
dad60f8e
SL		 10572013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1058
1059 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1060
f5cb796a
SL		 10612013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1062
1063 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1064
21fde85c
SL		 10652013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1066
1067 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1068
dd5181d5
KT		 10692013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1070
1071 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1072 (thumb32_opcodes): Likewise.
1073 (print_insn_thumb32): Handle 'S' control char.
1074
87a8d6cb
NC		 10752013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
1076
1077 * lm32-desc.c: Regenerate.
1078
99dce992
L		 10792013-03-01 H.J. Lu <hongjiu.lu@intel.com>
1080
1081 * i386-reg.tbl (riz): Add RegRex64.
1082 * i386-tbl.h: Regenerated.
1083
e60bb1dd
YZ		 10842013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1085
1086 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1087 (aarch64_feature_crc): New static.
1088 (CRC): New macro.
1089 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1090 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1091 * aarch64-asm-2.c: Re-generate.
1092 * aarch64-dis-2.c: Ditto.
1093 * aarch64-opc-2.c: Ditto.
1094
c7570fcd
AM		 10952013-02-27 Alan Modra <amodra@gmail.com>
1096
1097 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1098 * rl78-decode.c: Regenerate.
1099
151fa98f
NC		 11002013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1101
1102 * rl78-decode.opc: Fix encoding of DIVWU insn.
1103 * rl78-decode.c: Regenerate.
1104
5c111e37
L		 11052013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1106
1107 PR gas/15159
1108 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1109
1110 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1111 (cpu_flags): Add CpuSMAP.
1112
1113 * i386-opc.h (CpuSMAP): New.
1114 (i386_cpu_flags): Add cpusmap.
1115
1116 * i386-opc.tbl: Add clac and stac.
1117
1118 * i386-init.h: Regenerated.
1119 * i386-tbl.h: Likewise.
1120
9d1df426
NC		 11212013-02-15 Markos Chandras <markos.chandras@imgtec.com>
1122
1123 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1124 which also makes the disassembler output be in little
1125 endian like it should be.
1126
a1ccaec9
YZ		 11272013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1128
1129 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1130 fields to NULL.
1131 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1132
ef068ef4 11332013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 1134
1135 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1136 section disassembled.
1137
6fe6ded9
RE		 11382013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1139
1140 * arm-dis.c: Update strht pattern.
1141
0aa27725
RS		 11422013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1143
1144 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1145 single-float. Disable ll, lld, sc and scd for EE. Disable the
1146 trunc.w.s macro for EE.
1147
36591ba1
SL		 11482013-02-06 Sandra Loosemore <sandra@codesourcery.com>
1149 Andrew Jenner <andrew@codesourcery.com>
1150
1151 Based on patches from Altera Corporation.
1152
1153 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1154 nios2-opc.c.
1155 * Makefile.in: Regenerated.
1156 * configure.in: Add case for bfd_nios2_arch.
1157 * configure: Regenerated.
1158 * disassemble.c (ARCH_nios2): Define.
1159 (disassembler): Add case for bfd_arch_nios2.
1160 * nios2-dis.c: New file.
1161 * nios2-opc.c: New file.
1162
545093a4
AM		 11632013-02-04 Alan Modra <amodra@gmail.com>
1164
1165 * po/POTFILES.in: Regenerate.
1166 * rl78-decode.c: Regenerate.
1167 * rx-decode.c: Regenerate.
1168
e30181a5
YZ		 11692013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1170
1171 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1172 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1173 * aarch64-asm.c (convert_xtl_to_shll): New function.
1174 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1175 calling convert_xtl_to_shll.
1176 * aarch64-dis.c (convert_shll_to_xtl): New function.
1177 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1178 calling convert_shll_to_xtl.
1179 * aarch64-gen.c: Update copyright year.
1180 * aarch64-asm-2.c: Re-generate.
1181 * aarch64-dis-2.c: Re-generate.
1182 * aarch64-opc-2.c: Re-generate.
1183
78c8d46c
NC		 11842013-01-24 Nick Clifton <nickc@redhat.com>
1185
1186 * v850-dis.c: Add support for e3v5 architecture.
1187 * v850-opc.c: Likewise.
1188
f5555712
YZ		 11892013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1190
1191 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1192 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1193 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 1194 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 1195 alignment check; change to call set_sft_amount_out_of_range_error
1196 instead of set_imm_out_of_range_error.
1197 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1198 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1199 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1200 SIMD_IMM_SFT.
1201
2f81ff92
L		 12022013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1203
1204 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1205
1206 * i386-init.h: Regenerated.
1207 * i386-tbl.h: Likewise.
1208
dd42f060
NC		 12092013-01-15 Nick Clifton <nickc@redhat.com>
1210
1211 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1212 values.
1213 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1214
a4533ed8
NC		 12152013-01-14 Will Newton <will.newton@imgtec.com>
1216
1217 * metag-dis.c (REG_WIDTH): Increase to 64.
1218
5817ffd1
PB		 12192013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1220
1221 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1222 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1223 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1224 (SH6): Update.
1225 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1226 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1227 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1228 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1229
a3c62988
NC		 12302013-01-10 Will Newton <will.newton@imgtec.com>
1231
1232 * Makefile.am: Add Meta.
1233 * configure.in: Add Meta.
1234 * disassemble.c: Add Meta support.
1235 * metag-dis.c: New file.
1236 * Makefile.in: Regenerate.
1237 * configure: Regenerate.
1238
73335eae
NC		 12392013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1240
1241 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1242 (match_opcode): Rename to cr16_match_opcode.
1243
e407c74b
NC		 12442013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1245
1246 * mips-dis.c: Add names for CP0 registers of r5900.
1247 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1248 instructions sq and lq.
1249 Add support for MIPS r5900 CPU.
1250 Add support for 128 bit MMI (Multimedia Instructions).
1251 Add support for EE instructions (Emotion Engine).
1252 Disable unsupported floating point instructions (64 bit and
1253 undefined compare operations).
1254 Enable instructions of MIPS ISA IV which are supported by r5900.
1255 Disable 64 bit co processor instructions.
1256 Disable 64 bit multiplication and division instructions.
1257 Disable instructions for co-processor 2 and 3, because these are
1258 not supported (preparation for later VU0 support (Vector Unit)).
1259 Disable cvt.w.s because this behaves like trunc.w.s and the
1260 correct execution can't be ensured on r5900.
1261 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1262 will confuse less developers and compilers.
1263
a32c3ff8
NC		 12642013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1265
fb098a1e
YZ		 1266 * aarch64-opc.c (aarch64_print_operand): Change to print
1267 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1268 in comment.
1269 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1270 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1271 OP_MOV_IMM_WIDE.
1272
12732013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1274
1275 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1276 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1277
62658407
L		 12782013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1279
1280 * i386-gen.c (process_copyright): Update copyright year to 2013.
1281
bab4becb 12822013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1283
bab4becb
NC		 1284 * cr16-dis.c (match_opcode,make_instruction): Remove static
1285 declaration.
1286 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1287 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1288
bab4becb 1289For older changes see ChangeLog-2012
252b5132 1290\f
bab4becb 1291Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1292
1293Copying and distribution of this file, with or without modification,
1294are permitted in any medium without royalty provided the copyright
1295notice and this notice are preserved.
1296
252b5132 1297Local Variables:
2f6d2f85
NC		 1298mode: change-log
1299left-margin: 8
1300fill-column: 74
252b5132
RH		 1301version-control: never
1302End:
GDB Binutils - Deliverables
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