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PowerPC64 ELFv2 support for gold.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
85181173
RR		 12013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2
3 * arm-dis.c (neon_opcodes): Adjust print string for vshll.
4
4edbb8e3
CF		 52013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
6
7 * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
8 +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
9 +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
10 (MSA): New define.
11 (MSA64): New define.
12 (micromips_opcodes): Add MSA instructions.
13 * mips-dis.c (msa_control_names): New array.
14 (mips_abi_choice): Add ASE_MSA to mips32r2.
15 Remove ASE_MDMX from mips64r2.
16 Add ASE_MSA and ASE_MSA64 to mips64r2.
17 (parse_mips_dis_option): Handle -Mmsa.
18 (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
19 (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
20 (print_mips_disassembler_options): Print -Mmsa.
21 * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
22 +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
23 (MSA): New define.
24 (MSA64): New define.
25 (mips_builtin_op): Add MSA instructions.
26
ae335a4e
SL		 272013-10-13 Sandra Loosemore <sandra@codesourcery.com>
28
29 * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
30 as the primary name of r30.
31
6c75cc62
L		 322013-10-12 Jan Beulich <jbeulich@suse.com>
33
34 * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
35 default case.
36 (OP_E_register): Move v_bnd_mode alongside m_mode.
37 * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
38 Drop Reg16 and Disp16. Add NoRex64.
39 (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
40 * i386-tbl.h: Re-generate.
41
0e1c2434
SK		 422013-10-10 Sean Keys <skeys@ipdatasys.com>
43
44 * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
45 table.
46 * xgate-dis.c (print_insn): Refactor to work with table change.
47
7903e530
RM		 482013-10-10 Roland McGrath <mcgrathr@google.com>
49
9ce09ba2
RM		 50 * i386-dis.c (oappend_maybe_intel): New function.
51 (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
52 (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
53 (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
54
2b4e983c
RM		 55 * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
56 possible compiler warnings when the union's initializer is
57 actually meant for the 'preg' enum typed member.
58 * crx-opc.c (REG): Likewise.
59
7903e530
RM		 60 * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
61 Remove duplicate const qualifier.
62
79e0e31d
JB		 632013-10-08 Jan Beulich <jbeulich@suse.com>
64
65 * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
66 (clflush): Use Anysize instead of Byte|Unspecified.
67 (prefetch*): Likewise.
68 * i386-tbl.h: Re-generate.
69
45099dfa
CF		 702013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
71
72 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
73
916fae91
L		 742013-09-30 H.J. Lu <hongjiu.lu@intel.com>
75
76 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
77 * i386-init.h: Regenerated.
78
c7b0bd56
SE		 792013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
80
81 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
82 * i386-init.h: Regenerated.
83
cc9afea3
AM		 842013-09-20 Alan Modra <amodra@gmail.com>
85
86 * configure: Regenerate.
87
e3f9e852
RS		 882013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
89
90 * s390-opc.txt (clih): Make the immediate unsigned.
91
74db7efb
NC		 922013-09-04 Roland McGrath <mcgrathr@google.com>
93
94 PR gas/15914
95 * arm-dis.c (arm_opcodes): Add udf.
96 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
97 (thumb32_opcodes): Add udf.w.
98 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
99
c8094e01
AK		 1002013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
101
102 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
103 For the load fp integer instructions only the suppression flag was
104 new with z196 version.
105
7e105031
NC		 1062013-08-28 Nick Clifton <nickc@redhat.com>
107
108 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
109 immediate is not suitable for the 32-bit ABI.
110
fb6f3895
MR		 1112013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
112
113 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
114 replacing NODS.
115
9aff4b7a
NC		 1162013-08-23 Yuri Chornoivan <yurchor@ukr.net>
117
118 PR binutils/15834
119 * aarch64-asm.c: Fix typos.
120 * aarch64-dis.c: Likewise.
121 * msp430-dis.c: Likewise.
122
5e0dc5ba
RS		 1232013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
124
125 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
126 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
127 Use +H rather than +C for the real "dext".
128 * mips-opc.c (mips_builtin_opcodes): Likewise.
129
0f35dbc4
RS		 1302013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
131
132 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
133 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
134 and OPTIONAL_MAPPED_REG.
135 * mips-opc.c (decode_mips_operand): Likewise.
136 * mips16-opc.c (decode_mips16_operand): Likewise.
137 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
138
79ceb7cb
L		 1392013-08-19 H.J. Lu <hongjiu.lu@intel.com>
140
141 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
142 (PREFIX_EVEX_0F3A3F): Likewise.
143 * i386-dis-evex.h (evex_table): Updated.
144
ee5734f0
RS		 1452013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
146
147 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
148 VCLIPW.
149
d6787ef9
EB		 1502013-08-05 Eric Botcazou <ebotcazou@adacore.com>
151 Konrad Eisele <konrad@gaisler.com>
152
153 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
154 bfd_mach_sparc.
155 * sparc-opc.c (MASK_LEON): Define.
156 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
157 (letandleon): New macro.
158 (v9andleon): Likewise.
159 (sparc_opc): Add leon.
160 (umac): Enable for letandleon.
161 (smac): Likewise.
162 (casa): Enable for v9andleon.
163 (cas): Likewise.
164 (casl): Likewise.
165
14daeee3
RS		 1662013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
167 Richard Sandiford <rdsandiford@googlemail.com>
168
169 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
170 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
171 (print_vu0_channel): New function.
172 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
173 (print_insn_args): Handle '#'.
174 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
175 * mips-opc.c (mips_vu0_channel_mask): New constant.
176 (decode_mips_operand): Handle new VU0 operand types.
177 (VU0, VU0CH): New macros.
178 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
179 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
180 Use "+6" rather than "G" for QMFC2 and QMTC2.
181
3ccad066
RS		 1822013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
183
184 * mips-formats.h (PCREL): Reorder parameters and update the definition
185 to match new mips_pcrel_operand layout.
186 (JUMP, JALX, BRANCH): Update accordingly.
187 * mips16-opc.c (decode_mips16_operand): Likewise.
188
df34fbcc
RS		 1892013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
190
191 * micromips-opc.c (WR_s): Delete.
192
fc76e730
RS		 1932013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
194
195 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
196 New macros.
197 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
198 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
199 (mips_builtin_opcodes): Use the new position-based read-write flags
200 instead of field-based ones. Use UDI for "udi..." instructions.
201 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
202 New macros.
203 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
204 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
205 (WR_SP, RD_16): New macros.
206 (RD_SP): Redefine as an INSN2_* flag.
207 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
208 (mips16_opcodes): Use the new position-based read-write flags
209 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
210 pinfo2 field.
211 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
212 New macros.
213 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
214 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
215 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
216 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
217 (micromips_opcodes): Use the new position-based read-write flags
218 instead of field-based ones.
219 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
220 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
221 of field-based flags.
222
26545944
RS		 2232013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
224
225 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
226 (WR_SP): Replace with...
227 (MOD_SP): ...this.
228 (mips16_opcodes): Update accordingly.
229 * mips-dis.c (print_insn_mips16): Likewise.
230
a8d92fc6
RS		 2312013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
232
233 * mips16-opc.c (mips16_opcodes): Reformat.
234
6a819047
RS		 2352013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
236
237 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
238 for operands that are hard-coded to $0.
239 * micromips-opc.c (micromips_opcodes): Likewise.
240
344c74a6
RS		 2412013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
242
243 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
244 for the single-operand forms of JALR and JALR.HB.
245 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
246 and JALRS.HB.
247
41989114
RS		 2482013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
249
250 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
251 instructions. Fix them to use WR_MACC instead of WR_CC and
252 add missing RD_MACCs.
253
6d075bce
RS		 2542013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
255
256 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
257
4f6ffcd3
PB		 2582013-07-29 Peter Bergner <bergner@vnet.ibm.com>
259
260 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
261
43234a1e
L		 2622013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
263 Alexander Ivchenko <alexander.ivchenko@intel.com>
264 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
265 Sergey Lega <sergey.s.lega@intel.com>
266 Anna Tikhonova <anna.tikhonova@intel.com>
267 Ilya Tocar <ilya.tocar@intel.com>
268 Andrey Turetskiy <andrey.turetskiy@intel.com>
269 Ilya Verbin <ilya.verbin@intel.com>
270 Kirill Yukhin <kirill.yukhin@intel.com>
271 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
272
273 * i386-dis-evex.h: New.
274 * i386-dis.c (OP_Rounding): New.
275 (VPCMP_Fixup): New.
276 (OP_Mask): New.
277 (Rdq): New.
278 (XMxmmq): New.
279 (EXdScalarS): New.
280 (EXymm): New.
281 (EXEvexHalfBcstXmmq): New.
282 (EXxmm_mdq): New.
283 (EXEvexXGscat): New.
284 (EXEvexXNoBcst): New.
285 (VPCMP): New.
286 (EXxEVexR): New.
287 (EXxEVexS): New.
288 (XMask): New.
289 (MaskG): New.
290 (MaskE): New.
291 (MaskR): New.
292 (MaskVex): New.
293 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
294 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
295 evex_rounding_mode, evex_sae_mode, mask_mode.
296 (USE_EVEX_TABLE): New.
297 (EVEX_TABLE): New.
298 (EVEX enum): New.
299 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
300 REG_EVEX_0F38C7.
301 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
302 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
303 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
304 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
305 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
306 MOD_EVEX_0F38C7_REG_6.
307 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
308 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
309 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
310 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
311 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
312 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
313 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
314 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
315 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
316 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
317 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
318 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
319 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
320 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
321 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
322 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
323 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
324 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
325 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
326 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
327 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
328 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
329 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
330 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
331 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
332 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
333 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
334 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
335 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
336 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
337 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
338 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
339 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
340 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
341 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
342 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
343 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
344 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
345 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
346 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
347 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
348 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
349 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
350 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
351 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
352 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
353 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
354 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
355 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
356 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
357 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
358 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
359 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
360 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
361 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
362 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
363 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
364 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
365 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
366 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
367 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
368 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
369 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
370 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
371 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
372 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
373 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
374 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
375 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
376 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
377 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
378 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
379 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
380 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
381 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
382 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
383 PREFIX_EVEX_0F3A55.
384 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
385 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
386 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
387 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
388 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
389 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
390 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
391 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
392 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
393 VEX_W_0F3A32_P_2_LEN_0.
394 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
395 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
396 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
397 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
398 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
399 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
400 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
401 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
402 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
403 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
404 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
405 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
406 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
407 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
408 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
409 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
410 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
411 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
412 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
413 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
414 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
415 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
416 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
417 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
418 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
419 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
420 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
421 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
422 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
423 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
424 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
425 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
426 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
427 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
428 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
429 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
430 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
431 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
432 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
433 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
434 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
435 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
436 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
437 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
438 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
439 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
440 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
441 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
442 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
443 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
444 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
445 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
446 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
447 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
448 (struct vex): Add fields evex, r, v, mask_register_specifier,
449 zeroing, ll, b.
450 (intel_names_xmm): Add upper 16 registers.
451 (att_names_xmm): Ditto.
452 (intel_names_ymm): Ditto.
453 (att_names_ymm): Ditto.
454 (names_zmm): New.
455 (intel_names_zmm): Ditto.
456 (att_names_zmm): Ditto.
457 (names_mask): Ditto.
458 (intel_names_mask): Ditto.
459 (att_names_mask): Ditto.
460 (names_rounding): Ditto.
461 (names_broadcast): Ditto.
462 (x86_64_table): Add escape to evex-table.
463 (reg_table): Include reg_table evex-entries from
464 i386-dis-evex.h. Fix prefetchwt1 instruction.
465 (prefix_table): Add entries for new instructions.
466 (vex_table): Ditto.
467 (vex_len_table): Ditto.
468 (vex_w_table): Ditto.
469 (mod_table): Ditto.
470 (get_valid_dis386): Properly handle new instructions.
471 (print_insn): Handle zmm and mask registers, print mask operand.
472 (intel_operand_size): Support EVEX, new modes and sizes.
473 (OP_E_register): Handle new modes.
474 (OP_E_memory): Ditto.
475 (OP_G): Ditto.
476 (OP_XMM): Ditto.
477 (OP_EX): Ditto.
478 (OP_VEX): Ditto.
479 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
480 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
481 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
482 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
483 CpuAVX512PF and CpuVREX.
484 (operand_type_init): Add OPERAND_TYPE_REGZMM,
485 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
486 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
487 StaticRounding, SAE, Disp8MemShift, NoDefMask.
488 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
489 * i386-init.h: Regenerate.
490 * i386-opc.h (CpuAVX512F): New.
491 (CpuAVX512CD): New.
492 (CpuAVX512ER): New.
493 (CpuAVX512PF): New.
494 (CpuVREX): New.
495 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
496 cpuavx512pf and cpuvrex fields.
497 (VecSIB): Add VecSIB512.
498 (EVex): New.
499 (Masking): New.
500 (VecESize): New.
501 (Broadcast): New.
502 (StaticRounding): New.
503 (SAE): New.
504 (Disp8MemShift): New.
505 (NoDefMask): New.
506 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
507 staticrounding, sae, disp8memshift and nodefmask.
508 (RegZMM): New.
509 (Zmmword): Ditto.
510 (Vec_Disp8): Ditto.
511 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
512 fields.
513 (RegVRex): New.
514 * i386-opc.tbl: Add AVX512 instructions.
515 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
516 registers, mask registers.
517 * i386-tbl.h: Regenerate.
518
1d2db237
RS		 5192013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
520
521 PR gas/15220
522 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
523 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
524
a0046408
L		 5252013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
526
527 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
528 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
529 PREFIX_0F3ACC.
530 (prefix_table): Updated.
531 (three_byte_table): Likewise.
532 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
533 (cpu_flags): Add CpuSHA.
534 (i386_cpu_flags): Add cpusha.
535 * i386-init.h: Regenerate.
536 * i386-opc.h (CpuSHA): New.
537 (CpuUnused): Restored.
538 (i386_cpu_flags): Add cpusha.
539 * i386-opc.tbl: Add SHA instructions.
540 * i386-tbl.h: Regenerate.
541
7e8b059b
L		 5422013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
543 Kirill Yukhin <kirill.yukhin@intel.com>
544 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
545
546 * i386-dis.c (BND_Fixup): New.
547 (Ebnd): New.
548 (Ev_bnd): New.
549 (Gbnd): New.
550 (BND): New.
551 (v_bnd_mode): New.
552 (bnd_mode): New.
c623f86c
L		 553 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
554 MOD_0F1B_PREFIX_1.
555 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 556 (dis tables): Replace XX with BND for near branch and call
557 instructions.
558 (prefix_table): Add new entries.
559 (mod_table): Likewise.
560 (names_bnd): New.
561 (intel_names_bnd): New.
562 (att_names_bnd): New.
563 (BND_PREFIX): New.
564 (prefix_name): Handle BND_PREFIX.
565 (print_insn): Initialize names_bnd.
566 (intel_operand_size): Handle new modes.
567 (OP_E_register): Likewise.
568 (OP_E_memory): Likewise.
569 (OP_G): Likewise.
570 * i386-gen.c (cpu_flag_init): Add CpuMPX.
571 (cpu_flags): Add CpuMPX.
572 (operand_type_init): Add RegBND.
573 (opcode_modifiers): Add BNDPrefixOk.
574 (operand_types): Add RegBND.
575 * i386-init.h: Regenerate.
576 * i386-opc.h (CpuMPX): New.
577 (CpuUnused): Comment out.
578 (i386_cpu_flags): Add cpumpx.
579 (BNDPrefixOk): New.
580 (i386_opcode_modifier): Add bndprefixok.
581 (RegBND): New.
582 (i386_operand_type): Add regbnd.
583 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
584 Add MPX instructions and bnd prefix.
585 * i386-reg.tbl: Add bnd0-bnd3 registers.
586 * i386-tbl.h: Regenerate.
587
b56e23fb
RS		 5882013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
589
590 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
591 ATTRIBUTE_UNUSED.
592
e7ae278d
RS		 5932013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
594
595 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
596 special rules.
597 * Makefile.in: Regenerate.
598 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
599 all fields. Reformat.
600
c3c07478
RS		 6012013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
602
603 * mips16-opc.c: Include mips-formats.h.
604 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
605 static arrays.
606 (decode_mips16_operand): New function.
607 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
608 (print_insn_arg): Handle OP_ENTRY_EXIT list.
609 Abort for OP_SAVE_RESTORE_LIST.
610 (print_mips16_insn_arg): Change interface. Use mips_operand
611 structures. Delete GET_OP_S. Move GET_OP definition to...
612 (print_insn_mips16): ...here. Call init_print_arg_state.
613 Update the call to print_mips16_insn_arg.
614
ab902481
RS		 6152013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
616
617 * mips-formats.h: New file.
618 * mips-opc.c: Include mips-formats.h.
619 (reg_0_map): New static array.
620 (decode_mips_operand): New function.
621 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
622 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
623 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
624 (int_c_map): New static arrays.
625 (decode_micromips_operand): New function.
626 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
627 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
628 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
629 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
630 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
631 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
632 (micromips_imm_b_map, micromips_imm_c_map): Delete.
633 (print_reg): New function.
634 (mips_print_arg_state): New structure.
635 (init_print_arg_state, print_insn_arg): New functions.
636 (print_insn_args): Change interface and use mips_operand structures.
637 Delete GET_OP_S. Move GET_OP definition to...
638 (print_insn_mips): ...here. Update the call to print_insn_args.
639 (print_insn_micromips): Use print_insn_args.
640
cc537e56
RS		 6412013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
642
643 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
644 in macros.
645
7a5f87ce
RS		 6462013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
647
648 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
649 ADDA.S, MULA.S and SUBA.S.
650
41741fa4
L		 6512013-07-08 H.J. Lu <hongjiu.lu@intel.com>
652
653 PR gas/13572
654 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
655 * i386-tbl.h: Regenerated.
656
f2ae14a1
RS		 6572013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
658
659 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
660 and SD A(B) macros up.
661 * micromips-opc.c (micromips_opcodes): Likewise.
662
04c9d415
RS		 6632013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
664
665 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
666 instructions.
667
5c324c16
RS		 6682013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
669
670 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
671 MDMX-like instructions.
672 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
673 printing "Q" operands for INSN_5400 instructions.
674
23e69e47
RS		 6752013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
676
677 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
678 "+S" for "cins".
679 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
680 Combine cases.
681
27c5c572
RS		 6822013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
683
684 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
685 "jalx".
686 * mips16-opc.c (mips16_opcodes): Likewise.
687 * micromips-opc.c (micromips_opcodes): Likewise.
688 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
689 (print_insn_mips16): Handle "+i".
690 (print_insn_micromips): Likewise. Conditionally preserve the
691 ISA bit for "a" but not for "+i".
692
e76ff5ab
RS		 6932013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
694
695 * micromips-opc.c (WR_mhi): Rename to..
696 (WR_mh): ...this.
697 (micromips_opcodes): Update "movep" entry accordingly. Replace
698 "mh,mi" with "mh".
699 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
700 (micromips_to_32_reg_h_map1): ...this.
701 (micromips_to_32_reg_i_map): Rename to...
702 (micromips_to_32_reg_h_map2): ...this.
703 (print_micromips_insn): Remove "mi" case. Print both registers
704 in the pair for "mh".
705
fa7616a4
RS		 7062013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
707
708 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
709 * micromips-opc.c (micromips_opcodes): Likewise.
710 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
711 and "+T" handling. Check for a "0" suffix when deciding whether to
712 use coprocessor 0 names. In that case, also check for ",H" selectors.
713
fb798c50
AK		 7142013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
715
716 * s390-opc.c (J12_12, J24_24): New macros.
717 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
718 (MASK_MII_UPI): Rename to MASK_MII_UPP.
719 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
720
58ae08f2
AM		 7212013-07-04 Alan Modra <amodra@gmail.com>
722
723 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
724
b5e04c2b
NC		 7252013-06-26 Nick Clifton <nickc@redhat.com>
726
727 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
728 field when checking for type 2 nop.
729 * rx-decode.c: Regenerate.
730
833794fc
MR		 7312013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
732
733 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
734 and "movep" macros.
735
1bbce132
MR		 7362013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
737
738 * mips-dis.c (is_mips16_plt_tail): New function.
739 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
740 word.
741 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
742
34c911a4
NC		 7432013-06-21 DJ Delorie <dj@redhat.com>
744
745 * msp430-decode.opc: New.
746 * msp430-decode.c: New/generated.
747 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
748 (MAINTAINER_CLEANFILES): Likewise.
749 Add rule to build msp430-decode.c frommsp430decode.opc
750 using the opc2c program.
751 * Makefile.in: Regenerate.
752 * configure.in: Add msp430-decode.lo to msp430 architecture files.
753 * configure: Regenerate.
754
b9eead84
YZ		 7552013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
756
757 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
758 (SYMTAB_AVAILABLE): Removed.
759 (#include "elf/aarch64.h): Ditto.
760
7f3c4072
CM		 7612013-06-17 Catherine Moore <clm@codesourcery.com>
762 Maciej W. Rozycki <macro@codesourcery.com>
763 Chao-Ying Fu <fu@mips.com>
764
765 * micromips-opc.c (EVA): Define.
766 (TLBINV): Define.
767 (micromips_opcodes): Add EVA opcodes.
768 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
769 (print_insn_args): Handle EVA offsets.
770 (print_insn_micromips): Likewise.
771 * mips-opc.c (EVA): Define.
772 (TLBINV): Define.
773 (mips_builtin_opcodes): Add EVA opcodes.
774
de40ceb6
AM		 7752013-06-17 Alan Modra <amodra@gmail.com>
776
777 * Makefile.am (mips-opc.lo): Add rules to create automatic
778 dependency files. Pass archdefs.
779 (micromips-opc.lo, mips16-opc.lo): Likewise.
780 * Makefile.in: Regenerate.
781
3531d549
DD		 7822013-06-14 DJ Delorie <dj@redhat.com>
783
784 * rx-decode.opc (rx_decode_opcode): Bit operations on
785 registers are 32-bit operations, not 8-bit operations.
786 * rx-decode.c: Regenerate.
787
ba92f7fb
CF		 7882013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
789
790 * micromips-opc.c (IVIRT): New define.
791 (IVIRT64): New define.
792 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
793 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
794
795 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
796 dmtgc0 to print cp0 names.
797
9daf7bab
SL		 7982013-06-09 Sandra Loosemore <sandra@codesourcery.com>
799
800 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
801 argument.
802
d301a56b
RS		 8032013-06-08 Catherine Moore <clm@codesourcery.com>
804 Richard Sandiford <rdsandiford@googlemail.com>
805
806 * micromips-opc.c (D32, D33, MC): Update definitions.
807 (micromips_opcodes): Initialize ase field.
808 * mips-dis.c (mips_arch_choice): Add ase field.
809 (mips_arch_choices): Initialize ase field.
810 (set_default_mips_dis_options): Declare and setup mips_ase.
811 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
812 MT32, MC): Update definitions.
813 (mips_builtin_opcodes): Initialize ase field.
814
a3dcb6c5
RS		 8152013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
816
817 * s390-opc.txt (flogr): Require a register pair destination.
818
6cf1d90c
AK		 8192013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
820
821 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
822 instruction format.
823
c77c0862
RS		 8242013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
825
826 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
827
c0637f3a
PB		 8282013-05-20 Peter Bergner <bergner@vnet.ibm.com>
829
830 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
831 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
832 XLS_MASK, PPCVSX2): New defines.
833 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
834 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
835 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
836 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
837 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
838 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
839 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
840 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
841 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
842 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
843 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
844 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
845 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
846 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
847 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
848 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
849 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
850 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
851 <lxvx, stxvx>: New extended mnemonics.
852
4934fdaf
AM		 8532013-05-17 Alan Modra <amodra@gmail.com>
854
855 * ia64-raw.tbl: Replace non-ASCII char.
856 * ia64-waw.tbl: Likewise.
857 * ia64-asmtab.c: Regenerate.
858
6091d651
SE		 8592013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
860
861 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
862 * i386-init.h: Regenerated.
863
d2865ed3
YZ		 8642013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
865
866 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
867 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
868 check from [0, 255] to [-128, 255].
869
b015e599
AP		 8702013-05-09 Andrew Pinski <apinski@cavium.com>
871
872 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
873 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
874 (parse_mips_dis_option): Handle the virt option.
875 (print_insn_args): Handle "+J".
876 (print_mips_disassembler_options): Print out message about virt64.
877 * mips-opc.c (IVIRT): New define.
878 (IVIRT64): New define.
879 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
880 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
881 Move rfe to the bottom as it conflicts with tlbgp.
882
9f0682fe
AM		 8832013-05-09 Alan Modra <amodra@gmail.com>
884
885 * ppc-opc.c (extract_vlesi): Properly sign extend.
886 (extract_vlensi): Likewise. Comment reason for setting invalid.
887
13761a11
NC		 8882013-05-02 Nick Clifton <nickc@redhat.com>
889
890 * msp430-dis.c: Add support for MSP430X instructions.
891
e3031850
SL		 8922013-04-24 Sandra Loosemore <sandra@codesourcery.com>
893
894 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
895 to "eccinj".
896
17310e56
NC		 8972013-04-17 Wei-chen Wang <cole945@gmail.com>
898
899 PR binutils/15369
900 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
901 of CGEN_CPU_ENDIAN.
902 (hash_insns_list): Likewise.
903
731df338
JK		 9042013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
905
906 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
907 warning workaround.
908
5f77db52
JB		 9092013-04-08 Jan Beulich <jbeulich@suse.com>
910
911 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
912 * i386-tbl.h: Re-generate.
913
0afd1215
DM		 9142013-04-06 David S. Miller <davem@davemloft.net>
915
916 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
917 of an opcode, prefer the one with F_PREFERRED set.
918 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
919 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
920 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
921 mark existing mnenomics as aliases. Add "cc" suffix to edge
922 instructions generating condition codes, mark existing mnenomics
923 as aliases. Add "fp" prefix to VIS compare instructions, mark
924 existing mnenomics as aliases.
925
41702d50
NC		 9262013-04-03 Nick Clifton <nickc@redhat.com>
927
928 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
929 destination address by subtracting the operand from the current
930 address.
931 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
932 a positive value in the insn.
933 (extract_u16_loop): Do not negate the returned value.
934 (D16_LOOP): Add V850_INVERSE_PCREL flag.
935
936 (ceilf.sw): Remove duplicate entry.
937 (cvtf.hs): New entry.
938 (cvtf.sh): Likewise.
939 (fmaf.s): Likewise.
940 (fmsf.s): Likewise.
941 (fnmaf.s): Likewise.
942 (fnmsf.s): Likewise.
943 (maddf.s): Restrict to E3V5 architectures.
944 (msubf.s): Likewise.
945 (nmaddf.s): Likewise.
946 (nmsubf.s): Likewise.
947
55cf16e1
L		 9482013-03-27 H.J. Lu <hongjiu.lu@intel.com>
949
950 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
951 check address mode.
952 (print_insn): Pass sizeflag to get_sib.
953
51dcdd4d
NC		 9542013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
955
956 PR binutils/15068
957 * tic6x-dis.c: Add support for displaying 16-bit insns.
958
795b8e6b
NC		 9592013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
960
961 PR gas/15095
962 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
963 individual msb and lsb halves in src1 & src2 fields. Discard the
964 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
965 follow what Ti SDK does in that case as any value in the src1
966 field yields the same output with SDK disassembler.
967
314d60dd
ME		 9682013-03-12 Michael Eager <eager@eagercon.com>
969
795b8e6b 970 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 971
dad60f8e
SL		 9722013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
973
974 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
975
f5cb796a
SL		 9762013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
977
978 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
979
21fde85c
SL		 9802013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
981
982 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
983
dd5181d5
KT		 9842013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
985
986 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
987 (thumb32_opcodes): Likewise.
988 (print_insn_thumb32): Handle 'S' control char.
989
87a8d6cb
NC		 9902013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
991
992 * lm32-desc.c: Regenerate.
993
99dce992
L		 9942013-03-01 H.J. Lu <hongjiu.lu@intel.com>
995
996 * i386-reg.tbl (riz): Add RegRex64.
997 * i386-tbl.h: Regenerated.
998
e60bb1dd
YZ		 9992013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1000
1001 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1002 (aarch64_feature_crc): New static.
1003 (CRC): New macro.
1004 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1005 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1006 * aarch64-asm-2.c: Re-generate.
1007 * aarch64-dis-2.c: Ditto.
1008 * aarch64-opc-2.c: Ditto.
1009
c7570fcd
AM		 10102013-02-27 Alan Modra <amodra@gmail.com>
1011
1012 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1013 * rl78-decode.c: Regenerate.
1014
151fa98f
NC		 10152013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1016
1017 * rl78-decode.opc: Fix encoding of DIVWU insn.
1018 * rl78-decode.c: Regenerate.
1019
5c111e37
L		 10202013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1021
1022 PR gas/15159
1023 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1024
1025 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1026 (cpu_flags): Add CpuSMAP.
1027
1028 * i386-opc.h (CpuSMAP): New.
1029 (i386_cpu_flags): Add cpusmap.
1030
1031 * i386-opc.tbl: Add clac and stac.
1032
1033 * i386-init.h: Regenerated.
1034 * i386-tbl.h: Likewise.
1035
9d1df426
NC		 10362013-02-15 Markos Chandras <markos.chandras@imgtec.com>
1037
1038 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1039 which also makes the disassembler output be in little
1040 endian like it should be.
1041
a1ccaec9
YZ		 10422013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1043
1044 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1045 fields to NULL.
1046 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1047
ef068ef4 10482013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 1049
1050 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1051 section disassembled.
1052
6fe6ded9
RE		 10532013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1054
1055 * arm-dis.c: Update strht pattern.
1056
0aa27725
RS		 10572013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1058
1059 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1060 single-float. Disable ll, lld, sc and scd for EE. Disable the
1061 trunc.w.s macro for EE.
1062
36591ba1
SL		 10632013-02-06 Sandra Loosemore <sandra@codesourcery.com>
1064 Andrew Jenner <andrew@codesourcery.com>
1065
1066 Based on patches from Altera Corporation.
1067
1068 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1069 nios2-opc.c.
1070 * Makefile.in: Regenerated.
1071 * configure.in: Add case for bfd_nios2_arch.
1072 * configure: Regenerated.
1073 * disassemble.c (ARCH_nios2): Define.
1074 (disassembler): Add case for bfd_arch_nios2.
1075 * nios2-dis.c: New file.
1076 * nios2-opc.c: New file.
1077
545093a4
AM		 10782013-02-04 Alan Modra <amodra@gmail.com>
1079
1080 * po/POTFILES.in: Regenerate.
1081 * rl78-decode.c: Regenerate.
1082 * rx-decode.c: Regenerate.
1083
e30181a5
YZ		 10842013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1085
1086 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1087 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1088 * aarch64-asm.c (convert_xtl_to_shll): New function.
1089 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1090 calling convert_xtl_to_shll.
1091 * aarch64-dis.c (convert_shll_to_xtl): New function.
1092 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1093 calling convert_shll_to_xtl.
1094 * aarch64-gen.c: Update copyright year.
1095 * aarch64-asm-2.c: Re-generate.
1096 * aarch64-dis-2.c: Re-generate.
1097 * aarch64-opc-2.c: Re-generate.
1098
78c8d46c
NC		 10992013-01-24 Nick Clifton <nickc@redhat.com>
1100
1101 * v850-dis.c: Add support for e3v5 architecture.
1102 * v850-opc.c: Likewise.
1103
f5555712
YZ		 11042013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1105
1106 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1107 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1108 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 1109 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 1110 alignment check; change to call set_sft_amount_out_of_range_error
1111 instead of set_imm_out_of_range_error.
1112 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1113 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1114 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1115 SIMD_IMM_SFT.
1116
2f81ff92
L		 11172013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1118
1119 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1120
1121 * i386-init.h: Regenerated.
1122 * i386-tbl.h: Likewise.
1123
dd42f060
NC		 11242013-01-15 Nick Clifton <nickc@redhat.com>
1125
1126 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1127 values.
1128 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1129
a4533ed8
NC		 11302013-01-14 Will Newton <will.newton@imgtec.com>
1131
1132 * metag-dis.c (REG_WIDTH): Increase to 64.
1133
5817ffd1
PB		 11342013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1135
1136 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1137 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1138 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1139 (SH6): Update.
1140 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1141 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1142 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1143 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1144
a3c62988
NC		 11452013-01-10 Will Newton <will.newton@imgtec.com>
1146
1147 * Makefile.am: Add Meta.
1148 * configure.in: Add Meta.
1149 * disassemble.c: Add Meta support.
1150 * metag-dis.c: New file.
1151 * Makefile.in: Regenerate.
1152 * configure: Regenerate.
1153
73335eae
NC		 11542013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1155
1156 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1157 (match_opcode): Rename to cr16_match_opcode.
1158
e407c74b
NC		 11592013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1160
1161 * mips-dis.c: Add names for CP0 registers of r5900.
1162 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1163 instructions sq and lq.
1164 Add support for MIPS r5900 CPU.
1165 Add support for 128 bit MMI (Multimedia Instructions).
1166 Add support for EE instructions (Emotion Engine).
1167 Disable unsupported floating point instructions (64 bit and
1168 undefined compare operations).
1169 Enable instructions of MIPS ISA IV which are supported by r5900.
1170 Disable 64 bit co processor instructions.
1171 Disable 64 bit multiplication and division instructions.
1172 Disable instructions for co-processor 2 and 3, because these are
1173 not supported (preparation for later VU0 support (Vector Unit)).
1174 Disable cvt.w.s because this behaves like trunc.w.s and the
1175 correct execution can't be ensured on r5900.
1176 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1177 will confuse less developers and compilers.
1178
a32c3ff8
NC		 11792013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1180
fb098a1e
YZ		 1181 * aarch64-opc.c (aarch64_print_operand): Change to print
1182 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1183 in comment.
1184 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1185 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1186 OP_MOV_IMM_WIDE.
1187
11882013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1189
1190 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1191 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1192
62658407
L		 11932013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1194
1195 * i386-gen.c (process_copyright): Update copyright year to 2013.
1196
bab4becb 11972013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1198
bab4becb
NC		 1199 * cr16-dis.c (match_opcode,make_instruction): Remove static
1200 declaration.
1201 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1202 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1203
bab4becb 1204For older changes see ChangeLog-2012
252b5132 1205\f
bab4becb 1206Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1207
1208Copying and distribution of this file, with or without modification,
1209are permitted in any medium without royalty provided the copyright
1210notice and this notice are preserved.
1211
252b5132 1212Local Variables:
2f6d2f85
NC		 1213mode: change-log
1214left-margin: 8
1215fill-column: 74
252b5132
RH		 1216version-control: never
1217End:
GDB Binutils - Deliverables
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