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x86: adjust segment override prefix emission
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7deea9aa
JB		 12020-02-13 Jan Beulich <jbeulich@suse.com>
2
3 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
4 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
5 CPU_ANY_SSE4_FLAGS entry.
6 * i386-init.h: Re-generate.
7
6c0946d0
JB		 82020-02-12 Jan Beulich <jbeulich@suse.com>
9
10 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
11 with Unspecified, making the present one AT&T syntax only.
12 * i386-tbl.h: Re-generate.
13
ddb56fe6
JB		 142020-02-12 Jan Beulich <jbeulich@suse.com>
15
16 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
17 * i386-tbl.h: Re-generate.
18
5990e377
JB		 192020-02-12 Jan Beulich <jbeulich@suse.com>
20
21 PR gas/24546
22 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
23 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
24 Amd64 and Intel64 templates.
25 (call, jmp): Likewise for far indirect variants. Dro
26 Unspecified.
27 * i386-tbl.h: Re-generate.
28
50128d0c
JB		 292020-02-11 Jan Beulich <jbeulich@suse.com>
30
31 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
32 * i386-opc.h (ShortForm): Delete.
33 (struct i386_opcode_modifier): Remove shortform field.
34 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
35 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
36 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
37 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
38 Drop ShortForm.
39 * i386-tbl.h: Re-generate.
40
1e05b5c4
JB		 412020-02-11 Jan Beulich <jbeulich@suse.com>
42
43 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
44 fucompi): Drop ShortForm from operand-less templates.
45 * i386-tbl.h: Re-generate.
46
2f5dd314
AM		 472020-02-11 Alan Modra <amodra@gmail.com>
48
49 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
50 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
51 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
52 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
53 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
54
5aae9ae9
MM		 552020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
56
57 * arm-dis.c (print_insn_cde): Define 'V' parse character.
58 (cde_opcodes): Add VCX* instructions.
59
4934a27c
MM		 602020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
61 Matthew Malcomson <matthew.malcomson@arm.com>
62
63 * arm-dis.c (struct cdeopcode32): New.
64 (CDE_OPCODE): New macro.
65 (cde_opcodes): New disassembly table.
66 (regnames): New option to table.
67 (cde_coprocs): New global variable.
68 (print_insn_cde): New
69 (print_insn_thumb32): Use print_insn_cde.
70 (parse_arm_disassembler_options): Parse coprocN args.
71
4b5aaf5f
L		 722020-02-10 H.J. Lu <hongjiu.lu@intel.com>
73
74 PR gas/25516
75 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
76 with ISA64.
77 * i386-opc.h (AMD64): Removed.
78 (Intel64): Likewose.
79 (AMD64): New.
80 (INTEL64): Likewise.
81 (INTEL64ONLY): Likewise.
82 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
83 * i386-opc.tbl (Amd64): New.
84 (Intel64): Likewise.
85 (Intel64Only): Likewise.
86 Replace AMD64 with Amd64. Update sysenter/sysenter with
87 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
88 * i386-tbl.h: Regenerated.
89
9fc0b501
SB		 902020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
91
92 PR 25469
93 * z80-dis.c: Add support for GBZ80 opcodes.
94
c5d7be0c
AM		 952020-02-04 Alan Modra <amodra@gmail.com>
96
97 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
98
44e4546f
AM		 992020-02-03 Alan Modra <amodra@gmail.com>
100
101 * m32c-ibld.c: Regenerate.
102
b2b1453a
AM		 1032020-02-01 Alan Modra <amodra@gmail.com>
104
105 * frv-ibld.c: Regenerate.
106
4102be5c
JB		 1072020-01-31 Jan Beulich <jbeulich@suse.com>
108
109 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
110 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
111 (OP_E_memory): Replace xmm_mdq_mode case label by
112 vex_scalar_w_dq_mode one.
113 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
114
825bd36c
JB		 1152020-01-31 Jan Beulich <jbeulich@suse.com>
116
117 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
118 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
119 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
120 (intel_operand_size): Drop vex_w_dq_mode case label.
121
c3036ed0
RS		 1222020-01-31 Richard Sandiford <richard.sandiford@arm.com>
123
124 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
125 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
126
0c115f84
AM		 1272020-01-30 Alan Modra <amodra@gmail.com>
128
129 * m32c-ibld.c: Regenerate.
130
bd434cc4
JM		 1312020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
132
133 * bpf-opc.c: Regenerate.
134
aeab2b26
JB		 1352020-01-30 Jan Beulich <jbeulich@suse.com>
136
137 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
138 (dis386): Use them to replace C2/C3 table entries.
139 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
140 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
141 ones. Use Size64 instead of DefaultSize on Intel64 ones.
142 * i386-tbl.h: Re-generate.
143
62b3f548
JB		 1442020-01-30 Jan Beulich <jbeulich@suse.com>
145
146 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
147 forms.
148 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
149 DefaultSize.
150 * i386-tbl.h: Re-generate.
151
1bd8ae10
AM		 1522020-01-30 Alan Modra <amodra@gmail.com>
153
154 * tic4x-dis.c (tic4x_dp): Make unsigned.
155
bc31405e
L		 1562020-01-27 H.J. Lu <hongjiu.lu@intel.com>
157 Jan Beulich <jbeulich@suse.com>
158
159 PR binutils/25445
160 * i386-dis.c (MOVSXD_Fixup): New function.
161 (movsxd_mode): New enum.
162 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
163 (intel_operand_size): Handle movsxd_mode.
164 (OP_E_register): Likewise.
165 (OP_G): Likewise.
166 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
167 register on movsxd. Add movsxd with 16-bit destination register
168 for AMD64 and Intel64 ISAs.
169 * i386-tbl.h: Regenerated.
170
7568c93b
TC		 1712020-01-27 Tamar Christina <tamar.christina@arm.com>
172
173 PR 25403
174 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
175 * aarch64-asm-2.c: Regenerate
176 * aarch64-dis-2.c: Likewise.
177 * aarch64-opc-2.c: Likewise.
178
c006a730
JB		 1792020-01-21 Jan Beulich <jbeulich@suse.com>
180
181 * i386-opc.tbl (sysret): Drop DefaultSize.
182 * i386-tbl.h: Re-generate.
183
c906a69a
JB		 1842020-01-21 Jan Beulich <jbeulich@suse.com>
185
186 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
187 Dword.
188 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
189 * i386-tbl.h: Re-generate.
190
26916852
NC		 1912020-01-20 Nick Clifton <nickc@redhat.com>
192
193 * po/de.po: Updated German translation.
194 * po/pt_BR.po: Updated Brazilian Portuguese translation.
195 * po/uk.po: Updated Ukranian translation.
196
4d6cbb64
AM		 1972020-01-20 Alan Modra <amodra@gmail.com>
198
199 * hppa-dis.c (fput_const): Remove useless cast.
200
2bddb71a
AM		 2012020-01-20 Alan Modra <amodra@gmail.com>
202
203 * arm-dis.c (print_insn_arm): Wrap 'T' value.
204
1b1bb2c6
NC		 2052020-01-18 Nick Clifton <nickc@redhat.com>
206
207 * configure: Regenerate.
208 * po/opcodes.pot: Regenerate.
209
ae774686
NC		 2102020-01-18 Nick Clifton <nickc@redhat.com>
211
212 Binutils 2.34 branch created.
213
07f1f3aa
CB		 2142020-01-17 Christian Biesinger <cbiesinger@google.com>
215
216 * opintl.h: Fix spelling error (seperate).
217
42e04b36
L		 2182020-01-17 H.J. Lu <hongjiu.lu@intel.com>
219
220 * i386-opc.tbl: Add {vex} pseudo prefix.
221 * i386-tbl.h: Regenerated.
222
2da2eaf4
AV		 2232020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
224
225 PR 25376
226 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
227 (neon_opcodes): Likewise.
228 (select_arm_features): Make sure we enable MVE bits when selecting
229 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
230 any architecture.
231
d0849eed
JB		 2322020-01-16 Jan Beulich <jbeulich@suse.com>
233
234 * i386-opc.tbl: Drop stale comment from XOP section.
235
9cf70a44
JB		 2362020-01-16 Jan Beulich <jbeulich@suse.com>
237
238 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
239 (extractps): Add VexWIG to SSE2AVX forms.
240 * i386-tbl.h: Re-generate.
241
4814632e
JB		 2422020-01-16 Jan Beulich <jbeulich@suse.com>
243
244 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
245 Size64 from and use VexW1 on SSE2AVX forms.
246 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
247 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
248 * i386-tbl.h: Re-generate.
249
aad09917
AM		 2502020-01-15 Alan Modra <amodra@gmail.com>
251
252 * tic4x-dis.c (tic4x_version): Make unsigned long.
253 (optab, optab_special, registernames): New file scope vars.
254 (tic4x_print_register): Set up registernames rather than
255 malloc'd registertable.
256 (tic4x_disassemble): Delete optable and optable_special. Use
257 optab and optab_special instead. Throw away old optab,
258 optab_special and registernames when info->mach changes.
259
7a6bf3be
SB		 2602020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
261
262 PR 25377
263 * z80-dis.c (suffix): Use .db instruction to generate double
264 prefix.
265
ca1eaac0
AM		 2662020-01-14 Alan Modra <amodra@gmail.com>
267
268 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
269 values to unsigned before shifting.
270
1d67fe3b
TT		 2712020-01-13 Thomas Troeger <tstroege@gmx.de>
272
273 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
274 flow instructions.
275 (print_insn_thumb16, print_insn_thumb32): Likewise.
276 (print_insn): Initialize the insn info.
277 * i386-dis.c (print_insn): Initialize the insn info fields, and
278 detect jumps.
279
5e4f7e05
CZ		 2802012-01-13 Claudiu Zissulescu <claziss@gmail.com>
281
282 * arc-opc.c (C_NE): Make it required.
283
b9fe6b8a
CZ		 2842012-01-13 Claudiu Zissulescu <claziss@gmail.com>
285
286 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
287 reserved register name.
288
90dee485
AM		 2892020-01-13 Alan Modra <amodra@gmail.com>
290
291 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
292 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
293
febda64f
AM		 2942020-01-13 Alan Modra <amodra@gmail.com>
295
296 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
297 result of wasm_read_leb128 in a uint64_t and check that bits
298 are not lost when copying to other locals. Use uint32_t for
299 most locals. Use PRId64 when printing int64_t.
300
df08b588
AM		 3012020-01-13 Alan Modra <amodra@gmail.com>
302
303 * score-dis.c: Formatting.
304 * score7-dis.c: Formatting.
305
b2c759ce
AM		 3062020-01-13 Alan Modra <amodra@gmail.com>
307
308 * score-dis.c (print_insn_score48): Use unsigned variables for
309 unsigned values. Don't left shift negative values.
310 (print_insn_score32): Likewise.
311 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
312
5496abe1
AM		 3132020-01-13 Alan Modra <amodra@gmail.com>
314
315 * tic4x-dis.c (tic4x_print_register): Remove dead code.
316
202e762b
AM		 3172020-01-13 Alan Modra <amodra@gmail.com>
318
319 * fr30-ibld.c: Regenerate.
320
7ef412cf
AM		 3212020-01-13 Alan Modra <amodra@gmail.com>
322
323 * xgate-dis.c (print_insn): Don't left shift signed value.
324 (ripBits): Formatting, use 1u.
325
7f578b95
AM		 3262020-01-10 Alan Modra <amodra@gmail.com>
327
328 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
329 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
330
441af85b
AM		 3312020-01-10 Alan Modra <amodra@gmail.com>
332
333 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
334 and XRREG value earlier to avoid a shift with negative exponent.
335 * m10200-dis.c (disassemble): Similarly.
336
bce58db4
NC		 3372020-01-09 Nick Clifton <nickc@redhat.com>
338
339 PR 25224
340 * z80-dis.c (ld_ii_ii): Use correct cast.
341
40c75bc8
SB		 3422020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
343
344 PR 25224
345 * z80-dis.c (ld_ii_ii): Use character constant when checking
346 opcode byte value.
347
d835a58b
JB		 3482020-01-09 Jan Beulich <jbeulich@suse.com>
349
350 * i386-dis.c (SEP_Fixup): New.
351 (SEP): Define.
352 (dis386_twobyte): Use it for sysenter/sysexit.
353 (enum x86_64_isa): Change amd64 enumerator to value 1.
354 (OP_J): Compare isa64 against intel64 instead of amd64.
355 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
356 forms.
357 * i386-tbl.h: Re-generate.
358
030a2e78
AM		 3592020-01-08 Alan Modra <amodra@gmail.com>
360
361 * z8k-dis.c: Include libiberty.h
362 (instr_data_s): Make max_fetched unsigned.
363 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
364 Don't exceed byte_info bounds.
365 (output_instr): Make num_bytes unsigned.
366 (unpack_instr): Likewise for nibl_count and loop.
367 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
368 idx unsigned.
369 * z8k-opc.h: Regenerate.
370
bb82aefe
SV		 3712020-01-07 Shahab Vahedi <shahab@synopsys.com>
372
373 * arc-tbl.h (llock): Use 'LLOCK' as class.
374 (llockd): Likewise.
375 (scond): Use 'SCOND' as class.
376 (scondd): Likewise.
377 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
378 (scondd): Likewise.
379
cc6aa1a6
AM		 3802020-01-06 Alan Modra <amodra@gmail.com>
381
382 * m32c-ibld.c: Regenerate.
383
660e62b1
AM		 3842020-01-06 Alan Modra <amodra@gmail.com>
385
386 PR 25344
387 * z80-dis.c (suffix): Don't use a local struct buffer copy.
388 Peek at next byte to prevent recursion on repeated prefix bytes.
389 Ensure uninitialised "mybuf" is not accessed.
390 (print_insn_z80): Don't zero n_fetch and n_used here,..
391 (print_insn_z80_buf): ..do it here instead.
392
c9ae58fe
AM		 3932020-01-04 Alan Modra <amodra@gmail.com>
394
395 * m32r-ibld.c: Regenerate.
396
5f57d4ec
AM		 3972020-01-04 Alan Modra <amodra@gmail.com>
398
399 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
400
2c5c1196
AM		 4012020-01-04 Alan Modra <amodra@gmail.com>
402
403 * crx-dis.c (match_opcode): Avoid shift left of signed value.
404
2e98c6c5
AM		 4052020-01-04 Alan Modra <amodra@gmail.com>
406
407 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
408
567dfba2
JB		 4092020-01-03 Jan Beulich <jbeulich@suse.com>
410
5437a02a
JB		 411 * aarch64-tbl.h (aarch64_opcode_table): Use
412 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
413
4142020-01-03 Jan Beulich <jbeulich@suse.com>
415
416 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 417 forms of SUDOT and USDOT.
418
8c45011a
JB		 4192020-01-03 Jan Beulich <jbeulich@suse.com>
420
5437a02a 421 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 422 uzip{1,2}.
423 * opcodes/aarch64-dis-2.c: Re-generate.
424
f4950f76
JB		 4252020-01-03 Jan Beulich <jbeulich@suse.com>
426
5437a02a 427 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 428 FMMLA encoding.
429 * opcodes/aarch64-dis-2.c: Re-generate.
430
6655dba2
SB		 4312020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
432
433 * z80-dis.c: Add support for eZ80 and Z80 instructions.
434
b14ce8bf
AM		 4352020-01-01 Alan Modra <amodra@gmail.com>
436
437 Update year range in copyright notice of all files.
438
0b114740 439For older changes see ChangeLog-2019
3499769a 440\f
0b114740 441Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 442
443Copying and distribution of this file, with or without modification,
444are permitted in any medium without royalty provided the copyright
445notice and this notice are preserved.
446
447Local Variables:
448mode: change-log
449left-margin: 8
450fill-column: 74
451version-control: never
452End:
GDB Binutils - Deliverables
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