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dce08442
AK		 12016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
2
3 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
4
952c3f51
AK		 52016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
6
7 * s390-mkopc.c (main): Support alternate arch strings.
8
8b71537b
PS		 92016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
10
11 * s390-opc.txt: Fix kmctr instruction type.
12
5b64d091
L		 132016-09-07 H.J. Lu <hongjiu.lu@intel.com>
14
15 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
16 * i386-init.h: Regenerated.
17
7763838e
CM		 182016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
19
20 * opcodes/arc-dis.c (print_insn_arc): Changed.
21
1b8b6532
JM		 222016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
23
24 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
25 camellia_fl.
26
1a336194
TP		 272016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
28
29 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
30 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
31 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
32
6b40c462
L		 332016-08-24 H.J. Lu <hongjiu.lu@intel.com>
34
35 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
36 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
37 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
38 PREFIX_MOD_3_0FAE_REG_4.
39 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
40 PREFIX_MOD_3_0FAE_REG_4.
41 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
42 (cpu_flags): Add CpuPTWRITE.
43 * i386-opc.h (CpuPTWRITE): New.
44 (i386_cpu_flags): Add cpuptwrite.
45 * i386-opc.tbl: Add ptwrite instruction.
46 * i386-init.h: Regenerated.
47 * i386-tbl.h: Likewise.
48
ab548d2d
AK		 492016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
50
51 * arc-dis.h: Wrap around in extern "C".
52
344bde0a
RS		 532016-08-23 Richard Sandiford <richard.sandiford@arm.com>
54
55 * aarch64-tbl.h (V8_2_INSN): New macro.
56 (aarch64_opcode_table): Use it.
57
5ce912d8
RS		 582016-08-23 Richard Sandiford <richard.sandiford@arm.com>
59
60 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
61 CORE_INSN, __FP_INSN and SIMD_INSN.
62
9d30b0bd
RS		 632016-08-23 Richard Sandiford <richard.sandiford@arm.com>
64
65 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
66 (aarch64_opcode_table): Update uses accordingly.
67
dfdaec14
AJ		 682016-07-25 Andrew Jenner <andrew@codesourcery.com>
69 Kwok Cheung Yeung <kcy@codesourcery.com>
70
71 opcodes/
72 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
73 'e_cmplwi' to 'e_cmpli' instead.
74 (OPVUPRT, OPVUPRT_MASK): Define.
75 (powerpc_opcodes): Add E200Z4 insns.
76 (vle_opcodes): Add context save/restore insns.
77
7bd374a4
MR		 782016-07-27 Maciej W. Rozycki <macro@imgtec.com>
79
80 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
81 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
82 "j".
83
db18dbab
GM		 842016-07-27 Graham Markall <graham.markall@embecosm.com>
85
86 * arc-nps400-tbl.h: Change block comments to GNU format.
87 * arc-dis.c: Add new globals addrtypenames,
88 addrtypenames_max, and addtypeunknown.
89 (get_addrtype): New function.
90 (print_insn_arc): Print colons and address types when
91 required.
92 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
93 define insert and extract functions for all address types.
94 (arc_operands): Add operands for colon and all address
95 types.
96 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
97 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
98 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
99 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
100 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
101 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
102
fecd57f9
L		 1032016-07-21 H.J. Lu <hongjiu.lu@intel.com>
104
105 * configure: Regenerated.
106
37fd5ef3
CZ		 1072016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
108
109 * arc-dis.c (skipclass): New structure.
110 (decodelist): New variable.
111 (is_compatible_p): New function.
112 (new_element): Likewise.
113 (skip_class_p): Likewise.
114 (find_format_from_table): Use skip_class_p function.
115 (find_format): Decode first the extension instructions.
116 (print_insn_arc): Select either ARCEM or ARCHS based on elf
117 e_flags.
118 (parse_option): New function.
119 (parse_disassembler_options): Likewise.
120 (print_arc_disassembler_options): Likewise.
121 (print_insn_arc): Use parse_disassembler_options function. Proper
122 select ARCv2 cpu variant.
123 * disassemble.c (disassembler_usage): Add ARC disassembler
124 options.
125
92281a5b
MR		 1262016-07-13 Maciej W. Rozycki <macro@imgtec.com>
127
128 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
129 annotation from the "nal" entry and reorder it beyond "bltzal".
130
6e7ced37
JM		 1312016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
132
133 * sparc-opc.c (ldtxa): New macro.
134 (sparc_opcodes): Use the macro defined above to add entries for
135 the LDTXA instructions.
136 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
137 instruction.
138
2f831b9a 1392016-07-07 James Bowman <james.bowman@ftdichip.com>
140
141 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
142 and "jmpc".
143
c07315e0
JB		 1442016-07-01 Jan Beulich <jbeulich@suse.com>
145
146 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
147 (movzb): Adjust to cover all permitted suffixes.
148 (movzw): New.
149 * i386-tbl.h: Re-generate.
150
9243100a
JB		 1512016-07-01 Jan Beulich <jbeulich@suse.com>
152
153 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
154 (lgdt): Remove Tbyte from non-64-bit variant.
155 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
156 xsaves64, xsavec64): Remove Disp16.
157 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
158 Remove Disp32S from non-64-bit variants. Remove Disp16 from
159 64-bit variants.
160 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
161 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
162 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
163 64-bit variants.
164 * i386-tbl.h: Re-generate.
165
8325cc63
JB		 1662016-07-01 Jan Beulich <jbeulich@suse.com>
167
168 * i386-opc.tbl (xlat): Remove RepPrefixOk.
169 * i386-tbl.h: Re-generate.
170
838441e4
YQ		 1712016-06-30 Yao Qi <yao.qi@linaro.org>
172
173 * arm-dis.c (print_insn): Fix typo in comment.
174
dab26bf4
RS		 1752016-06-28 Richard Sandiford <richard.sandiford@arm.com>
176
177 * aarch64-opc.c (operand_general_constraint_met_p): Check the
178 range of ldst_elemlist operands.
179 (print_register_list): Use PRIi64 to print the index.
180 (aarch64_print_operand): Likewise.
181
5703197e
TS		 1822016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
183
184 * mcore-opc.h: Remove sentinal.
185 * mcore-dis.c (print_insn_mcore): Adjust.
186
ce440d63
GM		 1872016-06-23 Graham Markall <graham.markall@embecosm.com>
188
189 * arc-opc.c: Correct description of availability of NPS400
190 features.
191
6fd3a02d
PB		 1922016-06-22 Peter Bergner <bergner@vnet.ibm.com>
193
194 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
195 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
196 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
197 xor3>: New mnemonics.
198 <setb>: Change to a VX form instruction.
199 (insert_sh6): Add support for rldixor.
200 (extract_sh6): Likewise.
201
6b477896
TS		 2022016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
203
204 * arc-ext.h: Wrap in extern C.
205
bdd582db
GM		 2062016-06-21 Graham Markall <graham.markall@embecosm.com>
207
208 * arc-dis.c (arc_insn_length): Add comment on instruction length.
209 Use same method for determining instruction length on ARC700 and
210 NPS-400.
211 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
212 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
213 with the NPS400 subclass.
214 * arc-opc.c: Likewise.
215
96074adc
JM		 2162016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
217
218 * sparc-opc.c (rdasr): New macro.
219 (wrasr): Likewise.
220 (rdpr): Likewise.
221 (wrpr): Likewise.
222 (rdhpr): Likewise.
223 (wrhpr): Likewise.
224 (sparc_opcodes): Use the macros above to fix and expand the
225 definition of read/write instructions from/to
226 asr/privileged/hyperprivileged instructions.
227 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
228 %hva_mask_nz. Prefer softint_set and softint_clear over
229 set_softint and clear_softint.
230 (print_insn_sparc): Support %ver in Rd.
231
7a10c22f
JM		 2322016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
233
234 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
235 architecture according to the hardware capabilities they require.
236
4f26fb3a
JM		 2372016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
238
239 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
240 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
241 bfd_mach_sparc_v9{c,d,e,v,m}.
242 * sparc-opc.c (MASK_V9C): Define.
243 (MASK_V9D): Likewise.
244 (MASK_V9E): Likewise.
245 (MASK_V9V): Likewise.
246 (MASK_V9M): Likewise.
247 (v6): Add MASK_V9{C,D,E,V,M}.
248 (v6notlet): Likewise.
249 (v7): Likewise.
250 (v8): Likewise.
251 (v9): Likewise.
252 (v9andleon): Likewise.
253 (v9a): Likewise.
254 (v9b): Likewise.
255 (v9c): Define.
256 (v9d): Likewise.
257 (v9e): Likewise.
258 (v9v): Likewise.
259 (v9m): Likewise.
260 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
261
3ee6e4fb
NC		 2622016-06-15 Nick Clifton <nickc@redhat.com>
263
264 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
265 constants to match expected behaviour.
266 (nds32_parse_opcode): Likewise. Also for whitespace.
267
02f3be19
AB		 2682016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
269
270 * arc-opc.c (extract_rhv1): Extract value from insn.
271
6f9f37ed 2722016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 273
274 * arc-nps400-tbl.h: Add ldbit instruction.
275 * arc-opc.c: Add flag classes required for ldbit.
276
6f9f37ed 2772016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 278
279 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
280 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
281 support the above instructions.
282
6f9f37ed 2832016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 284
285 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
286 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
287 csma, cbba, zncv, and hofs.
288 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
289 support the above instructions.
290
2912016-06-06 Graham Markall <graham.markall@embecosm.com>
292
293 * arc-nps400-tbl.h: Add andab and orab instructions.
294
2952016-06-06 Graham Markall <graham.markall@embecosm.com>
296
297 * arc-nps400-tbl.h: Add addl-like instructions.
298
2992016-06-06 Graham Markall <graham.markall@embecosm.com>
300
301 * arc-nps400-tbl.h: Add mxb and imxb instructions.
302
3032016-06-06 Graham Markall <graham.markall@embecosm.com>
304
305 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
306 instructions.
307
b2cc3f6f
AK		 3082016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
309
310 * s390-dis.c (option_use_insn_len_bits_p): New file scope
311 variable.
312 (init_disasm): Handle new command line option "insnlength".
313 (print_s390_disassembler_options): Mention new option in help
314 output.
315 (print_insn_s390): Use the encoded insn length when dumping
316 unknown instructions.
317
1857fe72
DC		 3182016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
319
320 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
321 to the address and set as symbol address for LDS/ STS immediate operands.
322
14b57c7c
AM		 3232016-06-07 Alan Modra <amodra@gmail.com>
324
325 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
326 cpu for "vle" to e500.
327 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
328 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
329 (PPCNONE): Delete, substitute throughout.
330 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
331 except for major opcode 4 and 31.
332 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
333
4d1464f2
MW		 3342016-06-07 Matthew Wahab <matthew.wahab@arm.com>
335
336 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
337 ARM_EXT_RAS in relevant entries.
338
026122a6
PB		 3392016-06-03 Peter Bergner <bergner@vnet.ibm.com>
340
341 PR binutils/20196
342 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
343 opcodes for E6500.
344
07f5af7d
L		 3452016-06-03 H.J. Lu <hongjiu.lu@intel.com>
346
347 PR binutis/18386
348 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
349 (indir_v_mode): New.
350 Add comments for '&'.
351 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
352 (putop): Handle '&'.
353 (intel_operand_size): Handle indir_v_mode.
354 (OP_E_register): Likewise.
355 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
356 64-bit indirect call/jmp for AMD64.
357 * i386-tbl.h: Regenerated
358
4eb6f892
AB		 3592016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
360
361 * arc-dis.c (struct arc_operand_iterator): New structure.
362 (find_format_from_table): All the old content from find_format,
363 with some minor adjustments, and parameter renaming.
364 (find_format_long_instructions): New function.
365 (find_format): Rewritten.
366 (arc_insn_length): Add LSB parameter.
367 (extract_operand_value): New function.
368 (operand_iterator_next): New function.
369 (print_insn_arc): Use new functions to find opcode, and iterator
370 over operands.
371 * arc-opc.c (insert_nps_3bit_dst_short): New function.
372 (extract_nps_3bit_dst_short): New function.
373 (insert_nps_3bit_src2_short): New function.
374 (extract_nps_3bit_src2_short): New function.
375 (insert_nps_bitop1_size): New function.
376 (extract_nps_bitop1_size): New function.
377 (insert_nps_bitop2_size): New function.
378 (extract_nps_bitop2_size): New function.
379 (insert_nps_bitop_mod4_msb): New function.
380 (extract_nps_bitop_mod4_msb): New function.
381 (insert_nps_bitop_mod4_lsb): New function.
382 (extract_nps_bitop_mod4_lsb): New function.
383 (insert_nps_bitop_dst_pos3_pos4): New function.
384 (extract_nps_bitop_dst_pos3_pos4): New function.
385 (insert_nps_bitop_ins_ext): New function.
386 (extract_nps_bitop_ins_ext): New function.
387 (arc_operands): Add new operands.
388 (arc_long_opcodes): New global array.
389 (arc_num_long_opcodes): New global.
390 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
391
1fe0971e
TS		 3922016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
393
394 * nds32-asm.h: Add extern "C".
395 * sh-opc.h: Likewise.
396
315f180f
GM		 3972016-06-01 Graham Markall <graham.markall@embecosm.com>
398
399 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
400 0,b,limm to the rflt instruction.
401
a2b5fccc
TS		 4022016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
403
404 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
405 constant.
406
0cbd0046
L		 4072016-05-29 H.J. Lu <hongjiu.lu@intel.com>
408
409 PR gas/20145
410 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
411 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
412 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
413 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
414 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
415 * i386-init.h: Regenerated.
416
1848e567
L		 4172016-05-27 H.J. Lu <hongjiu.lu@intel.com>
418
419 PR gas/20145
420 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
421 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
422 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
423 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
424 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
425 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
426 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
427 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
428 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
429 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
430 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
431 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
432 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
433 CpuRegMask for AVX512.
434 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
435 and CpuRegMask.
436 (set_bitfield_from_cpu_flag_init): New function.
437 (set_bitfield): Remove const on f. Call
438 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
439 * i386-opc.h (CpuRegMMX): New.
440 (CpuRegXMM): Likewise.
441 (CpuRegYMM): Likewise.
442 (CpuRegZMM): Likewise.
443 (CpuRegMask): Likewise.
444 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
445 and cpuregmask.
446 * i386-init.h: Regenerated.
447 * i386-tbl.h: Likewise.
448
e92bae62
L		 4492016-05-27 H.J. Lu <hongjiu.lu@intel.com>
450
451 PR gas/20154
452 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
453 (opcode_modifiers): Add AMD64 and Intel64.
454 (main): Properly verify CpuMax.
455 * i386-opc.h (CpuAMD64): Removed.
456 (CpuIntel64): Likewise.
457 (CpuMax): Set to CpuNo64.
458 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
459 (AMD64): New.
460 (Intel64): Likewise.
461 (i386_opcode_modifier): Add amd64 and intel64.
462 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
463 on call and jmp.
464 * i386-init.h: Regenerated.
465 * i386-tbl.h: Likewise.
466
e89c5eaa
L		 4672016-05-27 H.J. Lu <hongjiu.lu@intel.com>
468
469 PR gas/20154
470 * i386-gen.c (main): Fail if CpuMax is incorrect.
471 * i386-opc.h (CpuMax): Set to CpuIntel64.
472 * i386-tbl.h: Regenerated.
473
77d66e7b
NC		 4742016-05-27 Nick Clifton <nickc@redhat.com>
475
476 PR target/20150
477 * msp430-dis.c (msp430dis_read_two_bytes): New function.
478 (msp430dis_opcode_unsigned): New function.
479 (msp430dis_opcode_signed): New function.
480 (msp430_singleoperand): Use the new opcode reading functions.
481 Only disassenmble bytes if they were successfully read.
482 (msp430_doubleoperand): Likewise.
483 (msp430_branchinstr): Likewise.
484 (msp430x_callx_instr): Likewise.
485 (print_insn_msp430): Check that it is safe to read bytes before
486 attempting disassembly. Use the new opcode reading functions.
487
19dfcc89
PB		 4882016-05-26 Peter Bergner <bergner@vnet.ibm.com>
489
490 * ppc-opc.c (CY): New define. Document it.
491 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
492
f3ad7637
L		 4932016-05-25 H.J. Lu <hongjiu.lu@intel.com>
494
495 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
496 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
497 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
498 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
499 CPU_ANY_AVX_FLAGS.
500 * i386-init.h: Regenerated.
501
f1360d58
L		 5022016-05-25 H.J. Lu <hongjiu.lu@intel.com>
503
504 PR gas/20141
505 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
506 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
507 * i386-init.h: Regenerated.
508
293f5f65
L		 5092016-05-25 H.J. Lu <hongjiu.lu@intel.com>
510
511 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
512 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
513 * i386-init.h: Regenerated.
514
d9eca1df
CZ		 5152016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
516
517 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
518 information.
519 (print_insn_arc): Set insn_type information.
520 * arc-opc.c (C_CC): Add F_CLASS_COND.
521 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
522 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
523 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
524 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
525 (brne, brne_s, jeq_s, jne_s): Likewise.
526
87789e08
CZ		 5272016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
528
529 * arc-tbl.h (neg): New instruction variant.
530
c810e0b8
CZ		 5312016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
532
533 * arc-dis.c (find_format, find_format, get_auxreg)
534 (print_insn_arc): Changed.
535 * arc-ext.h (INSERT_XOP): Likewise.
536
3d207518
TS		 5372016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
538
539 * tic54x-dis.c (sprint_mmr): Adjust.
540 * tic54x-opc.c: Likewise.
541
514e58b7
AM		 5422016-05-19 Alan Modra <amodra@gmail.com>
543
544 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
545
e43de63c
AM		 5462016-05-19 Alan Modra <amodra@gmail.com>
547
548 * ppc-opc.c: Formatting.
549 (NSISIGNOPT): Define.
550 (powerpc_opcodes <subis>): Use NSISIGNOPT.
551
1401d2fe
MR		 5522016-05-18 Maciej W. Rozycki <macro@imgtec.com>
553
554 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
555 replacing references to `micromips_ase' throughout.
556 (_print_insn_mips): Don't use file-level microMIPS annotation to
557 determine the disassembly mode with the symbol table.
558
1178da44
PB		 5592016-05-13 Peter Bergner <bergner@vnet.ibm.com>
560
561 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
562
8f4f9071
MF		 5632016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
564
565 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
566 mips64r6.
567 * mips-opc.c (D34): New macro.
568 (mips_builtin_opcodes): Define bposge32c for DSPr3.
569
8bc52696
AF		 5702016-05-10 Alexander Fomin <alexander.fomin@intel.com>
571
572 * i386-dis.c (prefix_table): Add RDPID instruction.
573 * i386-gen.c (cpu_flag_init): Add RDPID flag.
574 (cpu_flags): Add RDPID bitfield.
575 * i386-opc.h (enum): Add RDPID element.
576 (i386_cpu_flags): Add RDPID field.
577 * i386-opc.tbl: Add RDPID instruction.
578 * i386-init.h: Regenerate.
579 * i386-tbl.h: Regenerate.
580
39d911fc
TP		 5812016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
582
583 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
584 branch type of a symbol.
585 (print_insn): Likewise.
586
16a1fa25
TP		 5872016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
588
589 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
590 Mainline Security Extensions instructions.
591 (thumb_opcodes): Add entries for narrow ARMv8-M Security
592 Extensions instructions.
593 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
594 instructions.
595 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
596 special registers.
597
d751b79e
JM		 5982016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
599
600 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
601
945e0f82
CZ		 6022016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
603
604 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
605 (arcExtMap_genOpcode): Likewise.
606 * arc-opc.c (arg_32bit_rc): Define new variable.
607 (arg_32bit_u6): Likewise.
608 (arg_32bit_limm): Likewise.
609
20f55f38
SN		 6102016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
611
612 * aarch64-gen.c (VERIFIER): Define.
613 * aarch64-opc.c (VERIFIER): Define.
614 (verify_ldpsw): Use static linkage.
615 * aarch64-opc.h (verify_ldpsw): Remove.
616 * aarch64-tbl.h: Use VERIFIER for verifiers.
617
4bd13cde
NC		 6182016-04-28 Nick Clifton <nickc@redhat.com>
619
620 PR target/19722
621 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
622 * aarch64-opc.c (verify_ldpsw): New function.
623 * aarch64-opc.h (verify_ldpsw): New prototype.
624 * aarch64-tbl.h: Add initialiser for verifier field.
625 (LDPSW): Set verifier to verify_ldpsw.
626
c0f92bf9
L		 6272016-04-23 H.J. Lu <hongjiu.lu@intel.com>
628
629 PR binutils/19983
630 PR binutils/19984
631 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
632 smaller than address size.
633
e6c7cdec
TS		 6342016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
635
636 * alpha-dis.c: Regenerate.
637 * crx-dis.c: Likewise.
638 * disassemble.c: Likewise.
639 * epiphany-opc.c: Likewise.
640 * fr30-opc.c: Likewise.
641 * frv-opc.c: Likewise.
642 * ip2k-opc.c: Likewise.
643 * iq2000-opc.c: Likewise.
644 * lm32-opc.c: Likewise.
645 * lm32-opinst.c: Likewise.
646 * m32c-opc.c: Likewise.
647 * m32r-opc.c: Likewise.
648 * m32r-opinst.c: Likewise.
649 * mep-opc.c: Likewise.
650 * mt-opc.c: Likewise.
651 * or1k-opc.c: Likewise.
652 * or1k-opinst.c: Likewise.
653 * tic80-opc.c: Likewise.
654 * xc16x-opc.c: Likewise.
655 * xstormy16-opc.c: Likewise.
656
537aefaf
AB		 6572016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
658
659 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
660 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
661 calcsd, and calcxd instructions.
662 * arc-opc.c (insert_nps_bitop_size): Delete.
663 (extract_nps_bitop_size): Delete.
664 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
665 (extract_nps_qcmp_m3): Define.
666 (extract_nps_qcmp_m2): Define.
667 (extract_nps_qcmp_m1): Define.
668 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
669 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
670 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
671 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
672 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
673 NPS_QCMP_M3.
674
c8f785f2
AB		 6752016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
676
677 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
678
6fd8e7c2
L		 6792016-04-15 H.J. Lu <hongjiu.lu@intel.com>
680
681 * Makefile.in: Regenerated with automake 1.11.6.
682 * aclocal.m4: Likewise.
683
4b0c052e
AB		 6842016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
685
686 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
687 instructions.
688 * arc-opc.c (insert_nps_cmem_uimm16): New function.
689 (extract_nps_cmem_uimm16): New function.
690 (arc_operands): Add NPS_XLDST_UIMM16 operand.
691
cb040366
AB		 6922016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
693
694 * arc-dis.c (arc_insn_length): New function.
695 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
696 (find_format): Change insnLen parameter to unsigned.
697
accc0180
NC		 6982016-04-13 Nick Clifton <nickc@redhat.com>
699
700 PR target/19937
701 * v850-opc.c (v850_opcodes): Correct masks for long versions of
702 the LD.B and LD.BU instructions.
703
f36e33da
CZ		 7042016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
705
706 * arc-dis.c (find_format): Check for extension flags.
707 (print_flags): New function.
708 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
709 .extAuxRegister.
710 * arc-ext.c (arcExtMap_coreRegName): Use
711 LAST_EXTENSION_CORE_REGISTER.
712 (arcExtMap_coreReadWrite): Likewise.
713 (dump_ARC_extmap): Update printing.
714 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
715 (arc_aux_regs): Add cpu field.
716 * arc-regs.h: Add cpu field, lower case name aux registers.
717
1c2e355e
CZ		 7182016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
719
720 * arc-tbl.h: Add rtsc, sleep with no arguments.
721
b99747ae
CZ		 7222016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
723
724 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
725 Initialize.
726 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
727 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
728 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
729 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
730 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
731 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
732 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
733 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
734 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
735 (arc_opcode arc_opcodes): Null terminate the array.
736 (arc_num_opcodes): Remove.
737 * arc-ext.h (INSERT_XOP): Define.
738 (extInstruction_t): Likewise.
739 (arcExtMap_instName): Delete.
740 (arcExtMap_insn): New function.
741 (arcExtMap_genOpcode): Likewise.
742 * arc-ext.c (ExtInstruction): Remove.
743 (create_map): Zero initialize instruction fields.
744 (arcExtMap_instName): Remove.
745 (arcExtMap_insn): New function.
746 (dump_ARC_extmap): More info while debuging.
747 (arcExtMap_genOpcode): New function.
748 * arc-dis.c (find_format): New function.
749 (print_insn_arc): Use find_format.
750 (arc_get_disassembler): Enable dump_ARC_extmap only when
751 debugging.
752
92708cec
MR		 7532016-04-11 Maciej W. Rozycki <macro@imgtec.com>
754
755 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
756 instruction bits out.
757
a42a4f84
AB		 7582016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
759
760 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
761 * arc-opc.c (arc_flag_operands): Add new flags.
762 (arc_flag_classes): Add new classes.
763
1328504b
AB		 7642016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
765
766 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
767
820f03ff
AB		 7682016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
769
770 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
771 encode1, rflt, crc16, and crc32 instructions.
772 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
773 (arc_flag_classes): Add C_NPS_R.
774 (insert_nps_bitop_size_2b): New function.
775 (extract_nps_bitop_size_2b): Likewise.
776 (insert_nps_bitop_uimm8): Likewise.
777 (extract_nps_bitop_uimm8): Likewise.
778 (arc_operands): Add new operand entries.
779
8ddf6b2a
CZ		 7802016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
781
b99747ae
CZ		 782 * arc-regs.h: Add a new subclass field. Add double assist
783 accumulator register values.
784 * arc-tbl.h: Use DPA subclass to mark the double assist
785 instructions. Use DPX/SPX subclas to mark the FPX instructions.
786 * arc-opc.c (RSP): Define instead of SP.
787 (arc_aux_regs): Add the subclass field.
8ddf6b2a 788
589a7d88
JW		 7892016-04-05 Jiong Wang <jiong.wang@arm.com>
790
791 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
792
0a191de9 7932016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 794
795 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
796 NPS_R_SRC1.
797
0a106562
AB		 7982016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
799
800 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
801 issues. No functional changes.
802
bd05ac5f
CZ		 8032016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
804
b99747ae
CZ		 805 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
806 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
807 (RTT): Remove duplicate.
808 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
809 (PCT_CONFIG*): Remove.
810 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 811
9885948f
CZ		 8122016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
813
b99747ae 814 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 815
f2dd8838
CZ		 8162016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
817
b99747ae
CZ		 818 * arc-tbl.h (invld07): Remove.
819 * arc-ext-tbl.h: New file.
820 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
821 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 822
0d2f91fe
JK		 8232016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
824
825 Fix -Wstack-usage warnings.
826 * aarch64-dis.c (print_operands): Substitute size.
827 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
828
a6b71f42
JM		 8292016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
830
831 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
832 to get a proper diagnostic when an invalid ASR register is used.
833
9780e045
NC		 8342016-03-22 Nick Clifton <nickc@redhat.com>
835
836 * configure: Regenerate.
837
e23e8ebe
AB		 8382016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
839
840 * arc-nps400-tbl.h: New file.
841 * arc-opc.c: Add top level comment.
842 (insert_nps_3bit_dst): New function.
843 (extract_nps_3bit_dst): New function.
844 (insert_nps_3bit_src2): New function.
845 (extract_nps_3bit_src2): New function.
846 (insert_nps_bitop_size): New function.
847 (extract_nps_bitop_size): New function.
848 (arc_flag_operands): Add nps400 entries.
849 (arc_flag_classes): Add nps400 entries.
850 (arc_operands): Add nps400 entries.
851 (arc_opcodes): Add nps400 include.
852
1ae8ab47
AB		 8532016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
854
855 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
856 the new class enum values.
857
8699fc3e
AB		 8582016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
859
860 * arc-dis.c (print_insn_arc): Handle nps400.
861
24740d83
AB		 8622016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
863
864 * arc-opc.c (BASE): Delete.
865
8678914f
NC		 8662016-03-18 Nick Clifton <nickc@redhat.com>
867
868 PR target/19721
869 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
870 of MOV insn that aliases an ORR insn.
871
cc933301
JW		 8722016-03-16 Jiong Wang <jiong.wang@arm.com>
873
874 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
875
f86f5863
TS		 8762016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
877
878 * mcore-opc.h: Add const qualifiers.
879 * microblaze-opc.h (struct op_code_struct): Likewise.
880 * sh-opc.h: Likewise.
881 * tic4x-dis.c (tic4x_print_indirect): Likewise.
882 (tic4x_print_op): Likewise.
883
62de1c63
AM		 8842016-03-02 Alan Modra <amodra@gmail.com>
885
d11698cd 886 * or1k-desc.h: Regenerate.
62de1c63 887 * fr30-ibld.c: Regenerate.
c697cf0b 888 * rl78-decode.c: Regenerate.
62de1c63 889
020efce5
NC		 8902016-03-01 Nick Clifton <nickc@redhat.com>
891
892 PR target/19747
893 * rl78-dis.c (print_insn_rl78_common): Fix typo.
894
b0c11777
RL		 8952016-02-24 Renlin Li <renlin.li@arm.com>
896
897 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
898 (print_insn_coprocessor): Support fp16 instructions.
899
3e309328
RL		 9002016-02-24 Renlin Li <renlin.li@arm.com>
901
902 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
903 vminnm, vrint(mpna).
904
8afc7bea
RL		 9052016-02-24 Renlin Li <renlin.li@arm.com>
906
907 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
908 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
909
4fd7268a
L		 9102016-02-15 H.J. Lu <hongjiu.lu@intel.com>
911
912 * i386-dis.c (print_insn): Parenthesize expression to prevent
913 truncated addresses.
914 (OP_J): Likewise.
915
4670103e
CZ		 9162016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
917 Janek van Oirschot <jvanoirs@synopsys.com>
918
b99747ae
CZ		 919 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
920 variable.
4670103e 921
c1d9289f
NC		 9222016-02-04 Nick Clifton <nickc@redhat.com>
923
924 PR target/19561
925 * msp430-dis.c (print_insn_msp430): Add a special case for
926 decoding an RRC instruction with the ZC bit set in the extension
927 word.
928
a143b004
AB		 9292016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
930
931 * cgen-ibld.in (insert_normal): Rework calculation of shift.
932 * epiphany-ibld.c: Regenerate.
933 * fr30-ibld.c: Regenerate.
934 * frv-ibld.c: Regenerate.
935 * ip2k-ibld.c: Regenerate.
936 * iq2000-ibld.c: Regenerate.
937 * lm32-ibld.c: Regenerate.
938 * m32c-ibld.c: Regenerate.
939 * m32r-ibld.c: Regenerate.
940 * mep-ibld.c: Regenerate.
941 * mt-ibld.c: Regenerate.
942 * or1k-ibld.c: Regenerate.
943 * xc16x-ibld.c: Regenerate.
944 * xstormy16-ibld.c: Regenerate.
945
b89807c6
AB		 9462016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
947
948 * epiphany-dis.c: Regenerated from latest cpu files.
949
d8c823c8
MM		 9502016-02-01 Michael McConville <mmcco@mykolab.com>
951
952 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
953 test bit.
954
5bc5ae88
RL		 9552016-01-25 Renlin Li <renlin.li@arm.com>
956
957 * arm-dis.c (mapping_symbol_for_insn): New function.
958 (find_ifthen_state): Call mapping_symbol_for_insn().
959
0bff6e2d
MW		 9602016-01-20 Matthew Wahab <matthew.wahab@arm.com>
961
962 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
963 of MSR UAO immediate operand.
964
100b4f2e
MR		 9652016-01-18 Maciej W. Rozycki <macro@imgtec.com>
966
967 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
968 instruction support.
969
5c14705f
AM		 9702016-01-17 Alan Modra <amodra@gmail.com>
971
972 * configure: Regenerate.
973
4d82fe66
NC		 9742016-01-14 Nick Clifton <nickc@redhat.com>
975
976 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
977 instructions that can support stack pointer operations.
978 * rl78-decode.c: Regenerate.
979 * rl78-dis.c: Fix display of stack pointer in MOVW based
980 instructions.
981
651657fa
MW		 9822016-01-14 Matthew Wahab <matthew.wahab@arm.com>
983
984 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
985 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
986 erxtatus_el1 and erxaddr_el1.
987
105bde57
MW		 9882016-01-12 Matthew Wahab <matthew.wahab@arm.com>
989
990 * arm-dis.c (arm_opcodes): Add "esb".
991 (thumb_opcodes): Likewise.
992
afa8d405
PB		 9932016-01-11 Peter Bergner <bergner@vnet.ibm.com>
994
995 * ppc-opc.c <xscmpnedp>: Delete.
996 <xvcmpnedp>: Likewise.
997 <xvcmpnedp.>: Likewise.
998 <xvcmpnesp>: Likewise.
999 <xvcmpnesp.>: Likewise.
1000
83c3256e
AS		 10012016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1002
1003 PR gas/13050
1004 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1005 addition to ISA_A.
1006
6f2750fe
AM		 10072016-01-01 Alan Modra <amodra@gmail.com>
1008
1009 Update year range in copyright notice of all files.
1010
3499769a
AM		 1011For older changes see ChangeLog-2015
1012\f
1013Copyright (C) 2016 Free Software Foundation, Inc.
1014
1015Copying and distribution of this file, with or without modification,
1016are permitted in any medium without royalty provided the copyright
1017notice and this notice are preserved.
1018
1019Local Variables:
1020mode: change-log
1021left-margin: 8
1022fill-column: 74
1023version-control: never
1024End:
GDB Binutils - Deliverables
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