[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2006-05-14  Thiemo Seufer  <ths@mips.com>

	* mips16-opc.c (I1, I32, I64): New shortcut defines.
	(mips16_opcodes): Change membership of instructions to their
	lowest baseline ISA.

2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (grps): Update sgdt/sidt for 64bit.

2006-05-05  Julian Brown  <julian@codesourcery.com>

	* arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
	vldm/vstm.

2006-05-05  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

	* mips-opc.c: Add macro for cache instruction.

2006-05-04  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
	    David Ung  <davidu@mips.com>

	* mips-dis.c (mips_arch_choices): Add smartmips instruction
	decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
	2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
	MIPS64R2.
	* mips-opc.c: fix random typos in comments.
	(INSN_SMARTMIPS): New defines.
	(mips_builtin_opcodes): Add paired single support for MIPS32R2.
	Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
	flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
	FP_S and FP_D flags to denote single and double register
	accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
	Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
	for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
	variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
	release 2 ISAs.
	* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.

2006-05-03  Thiemo Seufer  <ths@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.

2006-05-02  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

	* mips-dis.c (print_insn_args): Force mips16 to odd addresses.
	(print_mips16_insn_arg): Force mips16 to odd addresses.

2006-04-30  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>

	* mips-opc.c (mips_builtin_opcodes): Add udi instructions
	"udi0" to "udi15".
	* mips-dis.c (print_insn_args): Adds udi argument handling.

2006-04-28  James E Wilson  <wilson@specifix.com>

	* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
	error message.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            David Ung  <davidu@mips.com>
	    Nigel Stephens  <nigel@mips.com>

	* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
	names.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>
            David Ung  <davidu@mips.com>

	* mips-dis.c (print_insn_args): Add mips_opcode argument.
	(print_insn_mips):  Adjust print_insn_args call.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

	* mips-dis.c (print_insn_args): Print $fcc only for FP
	instructions, use $cc elsewise.

2006-04-28  Thiemo Seufer  <ths@mips.com>
            Nigel Stephens  <nigel@mips.com>

	* opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
	Map MIPS16 registers to O32 names.
	(print_mips16_insn_arg): Use mips16_reg_names.

2006-04-26  Julian Brown  <julian@codesourcery.com>

	* arm-dis.c (print_insn_neon): Disassemble floating-point constant
	VMOV.

2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>

	* opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
	%<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
	Add unified load/store instruction names.
	(neon_opcode_table): New.
	(arm_opcodes): Expand meaning of %<bitfield>['`?].
	(arm_decode_bitfield): New.
	(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
	Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
	(print_insn_neon): New.
	(print_insn_arm): Adjust print_insn_coprocessor call. Call
	print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
	(print_insn_thumb32): Likewise.

2006-04-19  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.

2006-04-19  Alan Modra  <amodra@bigpond.net.au>

	* avr-dis.c (avr_operand): Warning fix.

	* configure: Regenerate.

2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>

	* po/POTFILES.in: Regenerated.

2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>

	PR binutils/2454
	* avr-dis.c (avr_operand): Arrange for a comment to appear before
	the symolic form of an address, so that the output of objdump -d
	can be reassembled.

2006-04-10  DJ Delorie  <dj@redhat.com>

	* m32c-asm.c: Regenerate.

2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>

	* Makefile.am: Add install-html target.
	* Makefile.in: Regenerate.

2006-04-06  Nick Clifton  <nickc@redhat.com>

	* po/vi/po: Updated Vietnamese translation.

2006-03-31  Paul Koning  <ni1d@arrl.net>

	* pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.

2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>

	* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
	logic to identify halfword shifts.

2006-03-16  Paul Brook  <paul@codesourcery.com>

	* arm-dis.c (arm_opcodes): Rename swi to svc.
	(thumb_opcodes): Ditto.

2006-03-13  DJ Delorie  <dj@redhat.com>

	* m32c-asm.c: Regenerate.
	* m32c-desc.c: Likewise.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-ibld.c: Likewise.
	* m32c-opc.c: Likewise.
	* m32c-opc.h: Likewise.

2006-03-10  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate with mul.l, mulu.l.
	* m32c-opc.c: Likewise.
	* m32c-opc.h: Likewise.


2006-03-09  Nick Clifton  <nickc@redhat.com>

	* po/sv.po: Updated Swedish translation.

2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/2428
	* i386-dis.c (REP_Fixup): New function.
	(AL): Remove duplicate.
	(Xbr): New.
	(Xvr): Likewise.
	(Ybr): Likewise.
	(Yvr): Likewise.
	(indirDXr): Likewise.
	(ALr): Likewise.
	(eAXr): Likewise.
	(dis386): Updated entries of ins, outs, movs, lods and stos.

2006-03-05  Nick Clifton  <nickc@redhat.com>

	* cgen-ibld.in (insert_normal): Cope with attempts to insert a
	signed 32-bit value into an unsigned 32-bit field when the host is
	a 64-bit machine.
	* fr30-ibld.c: Regenerate.
	* frv-ibld.c: Regenerate.
	* ip2k-ibld.c: Regenerate.
	* iq2000-asm.c: Regenerate.
	* iq2000-ibld.c: Regenerate.
	* m32c-ibld.c: Regenerate.
	* m32r-ibld.c: Regenerate.
	* openrisc-ibld.c: Regenerate.
	* xc16x-ibld.c: Regenerate.
	* xstormy16-ibld.c: Regenerate.

2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)

	* xc16x-asm.c: Regenerate.
	* xc16x-dis.c: Regenerate.

2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>

	* po/Make-in: Add html target.

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	Intel Merom New Instructions.
	(THREE_BYTE_0): Likewise.
	(THREE_BYTE_1): Likewise.
	(three_byte_table): Likewise.
	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	THREE_BYTE_1 for entry 0x3a.
	(twobyte_has_modrm): Updated.
	(twobyte_uses_SSE_prefix): Likewise.
	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	Instructions.

2006-02-24  David S. Miller  <davem@sunset.davemloft.net>

	* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
	(v9_hpriv_reg_names): New table.
	(print_insn_sparc): Allow values up to 16 for '?' and '!'.
	New cases '$' and '%' for read/write hyperprivileged register.
	* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
	window handling and rdhpr/wrhpr instructions.
	
2006-02-24  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate with linker relaxation attributes.
	* m32c-desc.h: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-opc.c: Likewise.

2006-02-24  Paul Brook  <paul@codesourcery.com>

	* arm-dis.c (arm_opcodes): Add V7 instructions.
	(thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
	(print_arm_address): New function.
	(print_insn_arm): Use it.  Add 'P' and 'U' cases.
	(psr_name): New function.
	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-opc-i.c (bXc): New.
	(mXc): Likewise.
	(OpX2TaTbYaXcC): Likewise.
	(TF). Likewise.
	(TFCM). Likewise.
	(ia64_opcodes_i): Add instructions for tf.

	* ia64-opc.h (IMMU5b): New.

	* ia64-asmtab.c: Regenerated.

2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c: Update copyright years.
	* ia64-opc-b.c: Likewise.

2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>

	* ia64-gen.c (lookup_regindex): Handle ".vm".
	(print_dependency_table): Handle '\"'.

	* ia64-ic.tbl: Updated from SDM 2.2.
	* ia64-raw.tbl: Likewise.
	* ia64-waw.tbl: Likewise.
	* ia64-asmtab.c: Regenerated.

	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.

2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
            Anil Paranjape   <anilp1@kpitcummins.com>
            Shilin Shakti    <shilins@kpitcummins.com>

	* xc16x-desc.h: New file
	* xc16x-desc.c: New file
	* xc16x-opc.h: New file	
	* xc16x-opc.c: New file
	* xc16x-ibld.c: New file
	* xc16x-asm.c: New file
	* xc16x-dis.c: New file
	* Makefile.am: Entries for xc16x 
	* Makefile.in: Regenerate 
	* cofigure.in: Add xc16x target information.
	* configure: Regenerate.
	* disassemble.c: Add xc16x target information.

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
	moves.

2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c ('Z'): Add a new macro.
	(dis386_twobyte): Use "movZ" for control register moves.

2006-02-10  Nick Clifton  <nickc@redhat.com>

	* iq2000-asm.c: Regenerate.

2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>

	* m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.

2006-01-26  David Ung  <davidu@mips.com>

	* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
	ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
	floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
	nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
	rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.

2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>

	* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
	ld_d_r, pref_xd_cb): Use signed char to hold data to be
	disassembled.	
	* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
	buffer overflows when disassembling instructions like
	ld (ix+123),0x23
	* z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
	operand, if the offset is negative.

2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>

	* z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
	unsigned char to hold data to be disassembled.

2006-01-17  Andreas Schwab  <schwab@suse.de>

	PR binutils/1486
	* disassemble.c (disassemble_init_for_target): Set
	disassembler_needs_relocs for bfd_arch_arm.

2006-01-16  Paul Brook  <paul@codesourcery.com>

	* m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
	f?add?, and f?sub? instructions.

2006-01-16  Nick Clifton  <nickc@redhat.com>

	* po/zh_CN.po: New Chinese (simplified) translation.
	* configure.in (ALL_LINGUAS): Add "zh_CH".
	* configure: Regenerate.

2006-01-05  Paul Brook  <paul@codesourcery.com>

	* m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.

2006-01-06  DJ Delorie  <dj@redhat.com>

	* m32c-desc.c: Regenerate.
	* m32c-opc.c: Regenerate.
	* m32c-opc.h: Regenerate.

2006-01-03  DJ Delorie  <dj@redhat.com>

	* cgen-ibld.in (extract_normal): Avoid memory range errors.
	* m32c-ibld.c: Regenerated.

For older changes see ChangeLog-2005
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
9b3f89ee TS	1	2006-05-14 Thiemo Seufer <ths@mips.com>
	2
	3	* mips16-opc.c (I1, I32, I64): New shortcut defines.
	4	(mips16_opcodes): Change membership of instructions to their
	5	lowest baseline ISA.
	6
cb6d3433 L	7	2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
	8
	9	* i386-dis.c (grps): Update sgdt/sidt for 64bit.
	10
1f3c39b9 JB	11	2006-05-05 Julian Brown <julian@codesourcery.com>
	12
	13	* arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
	14	vldm/vstm.
	15
d43b4baf TS	16	2006-05-05 Thiemo Seufer <ths@mips.com>
	17	David Ung <davidu@mips.com>
	18
	19	* mips-opc.c: Add macro for cache instruction.
	20
39a7806d TS	21	2006-05-04 Thiemo Seufer <ths@mips.com>
	22	Nigel Stephens <nigel@mips.com>
	23	David Ung <davidu@mips.com>
	24
	25	* mips-dis.c (mips_arch_choices): Add smartmips instruction
	26	decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
	27	2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
	28	MIPS64R2.
	29	* mips-opc.c: fix random typos in comments.
	30	(INSN_SMARTMIPS): New defines.
	31	(mips_builtin_opcodes): Add paired single support for MIPS32R2.
	32	Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
	33	flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
	34	FP_S and FP_D flags to denote single and double register
	35	accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
	36	Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
	37	for MIPS32R2. Add SmartMIPS instructions. Add two-argument
	38	variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
	39	release 2 ISAs.
	40	* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
	41
104b4fab TS	42	2006-05-03 Thiemo Seufer <ths@mips.com>
	43
	44	* mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
	45
022fac6d TS	46	2006-05-02 Thiemo Seufer <ths@mips.com>
	47	Nigel Stephens <nigel@mips.com>
	48	David Ung <davidu@mips.com>
	49
	50	* mips-dis.c (print_insn_args): Force mips16 to odd addresses.
	51	(print_mips16_insn_arg): Force mips16 to odd addresses.
	52
9bcd4f99 TS	53	2006-04-30 Thiemo Seufer <ths@mips.com>
	54	David Ung <davidu@mips.com>
	55
	56	* mips-opc.c (mips_builtin_opcodes): Add udi instructions
	57	"udi0" to "udi15".
	58	* mips-dis.c (print_insn_args): Adds udi argument handling.
	59
f095b97b JW	60	2006-04-28 James E Wilson <wilson@specifix.com>
	61
	62	* m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
	63	error message.
	64
59c455b3 TS	65	2006-04-28 Thiemo Seufer <ths@mips.com>
59c455b3 TS	66	David Ung <davidu@mips.com>
bdb09db1	67	Nigel Stephens <nigel@mips.com>
59c455b3 TS	68
	69	* mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
	70	names.
	71
cc0ca239	72	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	73	Nigel Stephens <nigel@mips.com>
cc0ca239 TS	74	David Ung <davidu@mips.com>
	75
	76	* mips-dis.c (print_insn_args): Add mips_opcode argument.
	77	(print_insn_mips): Adjust print_insn_args call.
	78
0d09bfe6	79	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	80	Nigel Stephens <nigel@mips.com>
0d09bfe6 TS	81
	82	* mips-dis.c (print_insn_args): Print $fcc only for FP
	83	instructions, use $cc elsewise.
	84
654c225a	85	2006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1	86	Nigel Stephens <nigel@mips.com>
654c225a TS	87
	88	* opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
	89	Map MIPS16 registers to O32 names.
	90	(print_mips16_insn_arg): Use mips16_reg_names.
	91
0dbde4cf JB	92	2006-04-26 Julian Brown <julian@codesourcery.com>
	93
	94	* arm-dis.c (print_insn_neon): Disassemble floating-point constant
	95	VMOV.
	96
16980d0b JB	97	2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
	98	Julian Brown <julian@codesourcery.com>
	99
	100	* opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
	101	%<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
	102	Add unified load/store instruction names.
	103	(neon_opcode_table): New.
	104	(arm_opcodes): Expand meaning of %<bitfield>['`?].
	105	(arm_decode_bitfield): New.
	106	(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
	107	Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
	108	(print_insn_neon): New.
	109	(print_insn_arm): Adjust print_insn_coprocessor call. Call
	110	print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
	111	(print_insn_thumb32): Likewise.
	112
ec3fcc56 AM	113	2006-04-19 Alan Modra <amodra@bigpond.net.au>
	114
	115	* Makefile.am: Run "make dep-am".
	116	* Makefile.in: Regenerate.
	117
241a6c40 AM	118	2006-04-19 Alan Modra <amodra@bigpond.net.au>
241a6c40 AM	119
7c6646cd AM	120	* avr-dis.c (avr_operand): Warning fix.
7c6646cd AM	121
241a6c40 AM	122	* configure: Regenerate.
241a6c40 AM	123
e7403566 DJ	124	2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
	125
	126	* po/POTFILES.in: Regenerated.
	127
52f16a0e NC	128	2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
	129
	130	PR binutils/2454
	131	* avr-dis.c (avr_operand): Arrange for a comment to appear before
	132	the symolic form of an address, so that the output of objdump -d
	133	can be reassembled.
	134
e78efa90 DD	135	2006-04-10 DJ Delorie <dj@redhat.com>
	136
	137	* m32c-asm.c: Regenerate.
	138
108a6f8e CD	139	2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
	140
	141	* Makefile.am: Add install-html target.
	142	* Makefile.in: Regenerate.
	143
a135cb2c NC	144	2006-04-06 Nick Clifton <nickc@redhat.com>
	145
	146	* po/vi/po: Updated Vietnamese translation.
	147
47426b41 AM	148	2006-03-31 Paul Koning <ni1d@arrl.net>
	149
	150	* pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
	151
331f1cbe BS	152	2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
	153
	154	* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
	155	logic to identify halfword shifts.
	156
c16d2bf0 PB	157	2006-03-16 Paul Brook <paul@codesourcery.com>
	158
	159	* arm-dis.c (arm_opcodes): Rename swi to svc.
	160	(thumb_opcodes): Ditto.
	161
5348b81e DD	162	2006-03-13 DJ Delorie <dj@redhat.com>
5348b81e DD	163
5398310a DD	164	* m32c-asm.c: Regenerate.
	165	* m32c-desc.c: Likewise.
	166	* m32c-desc.h: Likewise.
	167	* m32c-dis.c: Likewise.
	168	* m32c-ibld.c: Likewise.
5348b81e DD	169	* m32c-opc.c: Likewise.
	170	* m32c-opc.h: Likewise.
	171
253d272c DD	172	2006-03-10 DJ Delorie <dj@redhat.com>
	173
	174	* m32c-desc.c: Regenerate with mul.l, mulu.l.
	175	* m32c-opc.c: Likewise.
	176	* m32c-opc.h: Likewise.
	177
	178
f530741d NC	179	2006-03-09 Nick Clifton <nickc@redhat.com>
	180
	181	* po/sv.po: Updated Swedish translation.
	182
35c52694 L	183	2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
	184
	185	PR binutils/2428
	186	* i386-dis.c (REP_Fixup): New function.
	187	(AL): Remove duplicate.
	188	(Xbr): New.
	189	(Xvr): Likewise.
	190	(Ybr): Likewise.
	191	(Yvr): Likewise.
	192	(indirDXr): Likewise.
	193	(ALr): Likewise.
	194	(eAXr): Likewise.
	195	(dis386): Updated entries of ins, outs, movs, lods and stos.
	196
ed963e2d NC	197	2006-03-05 Nick Clifton <nickc@redhat.com>
	198
	199	* cgen-ibld.in (insert_normal): Cope with attempts to insert a
	200	signed 32-bit value into an unsigned 32-bit field when the host is
	201	a 64-bit machine.
	202	* fr30-ibld.c: Regenerate.
	203	* frv-ibld.c: Regenerate.
	204	* ip2k-ibld.c: Regenerate.
	205	* iq2000-asm.c: Regenerate.
	206	* iq2000-ibld.c: Regenerate.
	207	* m32c-ibld.c: Regenerate.
	208	* m32r-ibld.c: Regenerate.
	209	* openrisc-ibld.c: Regenerate.
	210	* xc16x-ibld.c: Regenerate.
	211	* xstormy16-ibld.c: Regenerate.
	212
c7d41dc5 NC	213	2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
	214
	215	* xc16x-asm.c: Regenerate.
	216	* xc16x-dis.c: Regenerate.
c7d41dc5	217
f7d9e5c3 CD	218	2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
	219
	220	* po/Make-in: Add html target.
	221
331d2d0d L	222	2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
	223
	224	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	225	Intel Merom New Instructions.
	226	(THREE_BYTE_0): Likewise.
	227	(THREE_BYTE_1): Likewise.
	228	(three_byte_table): Likewise.
	229	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	230	THREE_BYTE_1 for entry 0x3a.
	231	(twobyte_has_modrm): Updated.
	232	(twobyte_uses_SSE_prefix): Likewise.
	233	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	234	Instructions.
	235
ff3f9d5b DM	236	2006-02-24 David S. Miller <davem@sunset.davemloft.net>
	237
	238	* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
	239	(v9_hpriv_reg_names): New table.
	240	(print_insn_sparc): Allow values up to 16 for '?' and '!'.
	241	New cases '$' and '%' for read/write hyperprivileged register.
	242	* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
	243	window handling and rdhpr/wrhpr instructions.
	244
6772dd07 DD	245	2006-02-24 DJ Delorie <dj@redhat.com>
	246
	247	* m32c-desc.c: Regenerate with linker relaxation attributes.
	248	* m32c-desc.h: Likewise.
	249	* m32c-dis.c: Likewise.
	250	* m32c-opc.c: Likewise.
	251
62b3e311 PB	252	2006-02-24 Paul Brook <paul@codesourcery.com>
	253
	254	* arm-dis.c (arm_opcodes): Add V7 instructions.
	255	(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
	256	(print_arm_address): New function.
	257	(print_insn_arm): Use it. Add 'P' and 'U' cases.
	258	(psr_name): New function.
	259	(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
	260
59cf82fe L	261	2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
	262
	263	* ia64-opc-i.c (bXc): New.
	264	(mXc): Likewise.
	265	(OpX2TaTbYaXcC): Likewise.
	266	(TF). Likewise.
	267	(TFCM). Likewise.
	268	(ia64_opcodes_i): Add instructions for tf.
	269
	270	* ia64-opc.h (IMMU5b): New.
	271
	272	* ia64-asmtab.c: Regenerated.
	273
19a7219f L	274	2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
	275
	276	* ia64-gen.c: Update copyright years.
	277	* ia64-opc-b.c: Likewise.
	278
7f3dfb9c L	279	2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
	280
	281	* ia64-gen.c (lookup_regindex): Handle ".vm".
	282	(print_dependency_table): Handle '\"'.
	283
	284	* ia64-ic.tbl: Updated from SDM 2.2.
	285	* ia64-raw.tbl: Likewise.
	286	* ia64-waw.tbl: Likewise.
	287	* ia64-asmtab.c: Regenerated.
	288
	289	* ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
	290
d70c5fc7 NC	291	2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
	292	Anil Paranjape <anilp1@kpitcummins.com>
	293	Shilin Shakti <shilins@kpitcummins.com>
	294
	295	* xc16x-desc.h: New file
	296	* xc16x-desc.c: New file
	297	* xc16x-opc.h: New file
	298	* xc16x-opc.c: New file
	299	* xc16x-ibld.c: New file
	300	* xc16x-asm.c: New file
	301	* xc16x-dis.c: New file
	302	* Makefile.am: Entries for xc16x
	303	* Makefile.in: Regenerate
	304	* cofigure.in: Add xc16x target information.
	305	* configure: Regenerate.
	306	* disassemble.c: Add xc16x target information.
	307
a1cfb73e L	308	2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
	309
	310	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
	311	moves.
	312
6dd5059a L	313	2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
	314
	315	* i386-dis.c ('Z'): Add a new macro.
	316	(dis386_twobyte): Use "movZ" for control register moves.
	317
8536c657 NC	318	2006-02-10 Nick Clifton <nickc@redhat.com>
	319
	320	* iq2000-asm.c: Regenerate.
	321
266abb8f NS	322	2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
	323
	324	* m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
	325
f1a64f49 DU	326	2006-01-26 David Ung <davidu@mips.com>
	327
	328	* mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
	329	ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
	330	floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
	331	nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
	332	rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
	333
9e919b5f AM	334	2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
	335
	336	* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
	337	ld_d_r, pref_xd_cb): Use signed char to hold data to be
	338	disassembled.
	339	* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
	340	buffer overflows when disassembling instructions like
	341	ld (ix+123),0x23
	342	* z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
	343	operand, if the offset is negative.
	344
c9021189 AM	345	2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
	346
	347	* z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
	348	unsigned char to hold data to be disassembled.
	349
d99b6465 AS	350	2006-01-17 Andreas Schwab <schwab@suse.de>
	351
	352	PR binutils/1486
	353	* disassemble.c (disassemble_init_for_target): Set
	354	disassembler_needs_relocs for bfd_arch_arm.
	355
c2fe9327 PB	356	2006-01-16 Paul Brook <paul@codesourcery.com>
c2fe9327 PB	357
e88d958a	358	* m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
c2fe9327 PB	359	f?add?, and f?sub? instructions.
c2fe9327 PB	360
32fba81d NC	361	2006-01-16 Nick Clifton <nickc@redhat.com>
	362
	363	* po/zh_CN.po: New Chinese (simplified) translation.
	364	* configure.in (ALL_LINGUAS): Add "zh_CH".
	365	* configure: Regenerate.
	366
1b3a26b5 PB	367	2006-01-05 Paul Brook <paul@codesourcery.com>
	368
	369	* m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
	370
db313fa6 DD	371	2006-01-06 DJ Delorie <dj@redhat.com>
	372
	373	* m32c-desc.c: Regenerate.
	374	* m32c-opc.c: Regenerate.
	375	* m32c-opc.h: Regenerate.
	376
54d46aca DD	377	2006-01-03 DJ Delorie <dj@redhat.com>
	378
	379	* cgen-ibld.in (extract_normal): Avoid memory range errors.
	380	* m32c-ibld.c: Regenerated.
	381
e88d958a	382	For older changes see ChangeLog-2005
252b5132 RH	383	\f
252b5132 RH	384	Local Variables:
2f6d2f85 NC	385	mode: change-log
	386	left-margin: 8
	387	fill-column: 74
252b5132 RH	388	version-control: never
252b5132 RH	389	End: